Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T21,T22
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T13
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T12,T13
1	1	1	Covered	T4,T12,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T18
0	1	Covered	T12,T18,T20
1	0	Covered	T23,T24,T25

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T23,T24,T25

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T18
1	0	Covered	T26,T27,T28
1	1	Covered	T12,T18,T20

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T12

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T12

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T4,T12,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T4,T12,T18
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T29,T30,T31
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T31,T32,T33
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T34,T35,T36
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T17,T29,T37
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T4,T12,T18
TimeoutSt->Phase0St	167	Covered	T12,T18,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T35,T36
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T29,T37
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	974	0	0
CheckAccumTrig0_A	2147483647	2181	0	0
CheckAccumTrig1_A	2147483647	101	0	0
CheckClr_A	2147483647	991	0	0
CheckEn_A	2147483647	1059263070	0	0
CheckPhase0_A	2147483647	2515	0	0
CheckPhase1_A	2147483647	2467	0	0
CheckPhase2_A	2147483647	2429	0	0
CheckPhase3_A	2147483647	2393	0	0
CheckTimeout0_A	2147483647	4120	0	0
CheckTimeoutSt1_A	2147483647	480923	0	0
CheckTimeoutSt2_A	2147483647	3733	0	0
CheckTimeoutStTrig_A	2147483647	277	0	0
ErrorStAllEscAsserted_A	2147483647	5010	0	0
ErrorStIsTerminal_A	2147483647	4170	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	974	0	0
T5	2273372	0	0	0
T6	3270128	0	0	0
T9	68512	143	0	0
T10	0	307	0	0
T11	0	113	0	0
T14	1336352	0	0	0
T15	147164	0	0	0
T38	0	282	0	0
T39	0	129	0	0
T40	313028	0	0	0
T41	4356	0	0	0
T42	88296	0	0	0
T43	236108	0	0	0
T44	68812	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2181	0	0
T1	492906	3	0	0
T2	253470	1	0	0
T3	1824064	12	0	0
T4	560044	23	0	0
T5	0	16	0	0
T6	0	2	0	0
T9	17128	0	0	0
T12	1626944	16	0	0
T13	116244	1	0	0
T16	0	5	0	0
T17	526156	2	0	0
T18	337916	0	0	0
T19	92824	0	0	0
T20	316876	0	0	0
T23	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	5	0	0
T45	37798	6	0	0
T46	0	7	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	101	0	0
T23	61067	1	0	0
T24	4595	1	0	0
T25	709754	1	0	0
T26	0	1	0	0
T29	113592	1	0	0
T30	25283	0	0	0
T32	0	2	0	0
T34	18395	0	0	0
T37	118501	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	69942	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	5	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	39465	0	0	0
T62	646041	0	0	0
T63	64351	0	0	0
T64	6232	0	0	0
T65	323594	0	0	0
T66	352974	0	0	0
T67	19862	0	0	0
T68	494171	0	0	0
T69	58333	0	0	0
T70	393808	0	0	0
T71	152739	0	0	0
T72	32703	0	0	0
T73	217116	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	991	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	1824064	5	0	0
T4	560044	4	0	0
T5	0	1	0	0
T9	51384	0	0	0
T12	1626944	5	0	0
T13	116244	0	0	0
T16	0	2	0	0
T17	526156	1	0	0
T18	337916	0	0	0
T19	92824	0	0	0
T20	316876	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T29	0	4	0	0
T31	0	16	0	0
T32	0	6	0	0
T34	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T43	0	3	0	0
T45	113394	2	0	0
T46	0	3	0	0
T61	0	1	0	0
T64	0	1	0	0
T74	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1059263070	0	0
T1	657208	335690	0	0
T2	337960	112362	0	0
T3	1824064	484568	0	0
T4	560044	1377893	0	0
T12	1626944	1673606	0	0
T13	116244	87606	0	0
T17	526156	397633	0	0
T18	337916	54901	0	0
T19	92824	69988	0	0
T20	316876	116751	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2515	0	0
T1	492906	3	0	0
T2	253470	1	0	0
T3	1824064	12	0	0
T4	560044	23	0	0
T5	0	16	0	0
T6	0	2	0	0
T9	17128	0	0	0
T12	1626944	17	0	0
T13	116244	1	0	0
T16	0	4	0	0
T17	526156	2	0	0
T18	337916	2	0	0
T19	92824	0	0	0
T20	316876	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	5	0	0
T45	37798	6	0	0
T46	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2467	0	0
T1	492906	3	0	0
T2	253470	1	0	0
T3	1824064	12	0	0
T4	560044	23	0	0
T5	0	16	0	0
T6	0	2	0	0
T9	17128	0	0	0
T12	1626944	17	0	0
T13	116244	1	0	0
T16	0	4	0	0
T17	526156	2	0	0
T18	337916	2	0	0
T19	92824	0	0	0
T20	316876	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	5	0	0
T45	37798	6	0	0
T46	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2429	0	0
T1	492906	3	0	0
T2	253470	1	0	0
T3	1824064	12	0	0
T4	560044	23	0	0
T5	0	16	0	0
T6	0	2	0	0
T9	17128	0	0	0
T12	1626944	17	0	0
T13	116244	1	0	0
T16	0	4	0	0
T17	526156	2	0	0
T18	337916	2	0	0
T19	92824	0	0	0
T20	316876	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	5	0	0
T45	37798	6	0	0
T46	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2393	0	0
T1	492906	3	0	0
T2	253470	1	0	0
T3	1824064	12	0	0
T4	560044	23	0	0
T5	0	16	0	0
T6	0	2	0	0
T9	17128	0	0	0
T12	1626944	17	0	0
T13	116244	1	0	0
T16	0	4	0	0
T17	526156	1	0	0
T18	337916	2	0	0
T19	92824	0	0	0
T20	316876	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	5	0	0
T45	37798	6	0	0
T46	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4120	0	0
T4	140011	2	0	0
T5	2273372	3	0	0
T9	68512	0	0	0
T12	1220208	2	0	0
T13	87183	0	0	0
T14	334088	0	0	0
T17	131539	0	0	0
T18	337916	16	0	0
T19	92824	0	0	0
T20	316876	18	0	0
T23	0	3	0	0
T24	0	1	0	0
T25	0	9	0	0
T29	0	21	0	0
T31	0	3	0	0
T32	0	5	0	0
T34	0	6	0	0
T37	0	7	0	0
T40	234771	0	0	0
T41	3267	0	0	0
T42	22074	0	0	0
T43	0	1	0	0
T45	151192	0	0	0
T46	0	1	0	0
T63	0	1	0	0
T64	0	4	0	0
T67	0	3	0	0
T75	0	8	0	0
T76	0	2	0	0
T77	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	480923	0	0
T4	140011	82	0	0
T5	2273372	470	0	0
T9	68512	0	0	0
T12	1220208	323	0	0
T13	87183	0	0	0
T14	334088	0	0	0
T17	131539	0	0	0
T18	337916	2952	0	0
T19	92824	0	0	0
T20	316876	1937	0	0
T23	0	107	0	0
T24	0	10	0	0
T25	0	831	0	0
T29	0	2086	0	0
T31	0	727	0	0
T32	0	459	0	0
T34	0	336	0	0
T37	0	593	0	0
T40	234771	0	0	0
T41	3267	0	0	0
T42	22074	0	0	0
T43	0	198	0	0
T45	151192	0	0	0
T46	0	119	0	0
T63	0	124	0	0
T64	0	252	0	0
T67	0	473	0	0
T75	0	1051	0	0
T76	0	218	0	0
T77	0	232	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3733	0	0
T4	140011	2	0	0
T5	2273372	1	0	0
T9	68512	0	0	0
T12	813472	1	0	0
T13	58122	0	0	0
T14	668176	0	0	0
T17	131539	0	0	0
T18	337916	14	0	0
T19	92824	0	0	0
T20	316876	16	0	0
T23	0	1	0	0
T25	0	7	0	0
T29	0	15	0	0
T31	0	2	0	0
T32	0	4	0	0
T34	0	5	0	0
T37	0	4	0	0
T40	234771	0	0	0
T41	3267	0	0	0
T42	44148	0	0	0
T43	0	1	0	0
T45	151192	0	0	0
T46	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T75	0	17	0	0
T76	0	12	0	0
T77	0	12	0	0
T78	0	1	0	0
T79	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	277	0	0
T5	2273372	1	0	0
T6	817532	0	0	0
T9	51384	0	0	0
T12	406736	1	0	0
T13	29061	0	0	0
T14	1002264	0	0	0
T15	73582	0	0	0
T16	433332	0	0	0
T18	168958	1	0	0
T19	46412	0	0	0
T20	237657	1	0	0
T23	0	1	0	0
T29	0	2	0	0
T31	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T40	313028	0	0	0
T41	4356	0	0	0
T42	66222	0	0	0
T43	118054	0	0	0
T44	17203	0	0	0
T45	113394	0	0	0
T52	0	3	0	0
T64	0	1	0	0
T73	0	1	0	0
T77	0	5	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5010	0	0
T5	2273372	0	0	0
T6	3270128	0	0	0
T9	68512	692	0	0
T10	0	1419	0	0
T11	0	727	0	0
T14	1336352	0	0	0
T15	147164	0	0	0
T38	0	1388	0	0
T39	0	784	0	0
T40	313028	0	0	0
T41	4356	0	0	0
T42	88296	0	0	0
T43	236108	0	0	0
T44	68812	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4170	0	0
T5	2273372	0	0	0
T6	3270128	0	0	0
T9	68512	572	0	0
T10	0	1179	0	0
T11	0	607	0	0
T14	1336352	0	0	0
T15	147164	0	0	0
T38	0	1148	0	0
T39	0	664	0	0
T40	313028	0	0	0
T41	4356	0	0	0
T42	88296	0	0	0
T43	236108	0	0	0
T44	68812	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657208	657188	0	0
T2	337960	337672	0	0
T3	1824064	1824044	0	0
T4	560044	559724	0	0
T12	1626944	1626784	0	0
T13	116244	116024	0	0
T17	526156	525844	0	0
T18	337916	337620	0	0
T19	92824	92528	0	0
T20	316876	316644	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T21
1	1	1	Covered	T1,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T18
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T4,T12,T18
1	1	1	Covered	T12,T18,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T18,T20
0	1	Covered	T12,T18,T23
1	0	Covered	T25,T37,T32

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T37,T32

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T18,T20
1	0	Not Covered
1	1	Covered	T12,T18,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T12,T45

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T18,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T12,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T12,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T3,T4
IdleSt->TimeoutSt	154	Covered	T12,T18,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T29,T31,T58
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T86,T87,T88
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T89,T60,T90
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T29,T31,T71
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T4,T12
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T18,T20,T25
TimeoutSt->Phase0St	167	Covered	T12,T18,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T31,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T86,T87,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T89,T60,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T31,T71
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	633039078	224	0	0
CheckAccumTrig0_A	633039078	483	0	0
CheckAccumTrig1_A	633039078	23	0	0
CheckClr_A	633039078	224	0	0
CheckEn_A	632902808	276372593	0	0
CheckPhase0_A	633039078	575	0	0
CheckPhase1_A	633039078	568	0	0
CheckPhase2_A	633039078	564	0	0
CheckPhase3_A	633039078	553	0	0
CheckTimeout0_A	633039078	1072	0	0
CheckTimeoutSt1_A	633039078	114082	0	0
CheckTimeoutSt2_A	633039078	973	0	0
CheckTimeoutStTrig_A	633039078	75	0	0
ErrorStAllEscAsserted_A	633039078	1221	0	0
ErrorStIsTerminal_A	633039078	1011	0	0
u_state_regs_A	633039078	632880984	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	224	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	39	0	0
T10	0	75	0	0
T11	0	29	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	64	0	0
T39	0	17	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	483	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2	0	0
T4	140011	7	0	0
T5	0	3	0	0
T6	0	1	0	0
T12	406736	2	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	23	0	0
T25	354877	1	0	0
T29	113592	0	0	0
T30	25283	0	0	0
T32	0	1	0	0
T34	18395	0	0	0
T37	118501	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T65	161797	0	0	0
T66	176487	0	0	0
T67	9931	0	0	0
T68	494171	0	0	0
T69	58333	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	224	0	0
T3	456016	1	0	0
T4	140011	2	0	0
T9	17128	0	0	0
T12	406736	2	0	0
T13	29061	0	0	0
T16	0	1	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T25	0	2	0	0
T29	0	4	0	0
T31	0	7	0	0
T45	37798	1	0	0
T46	0	1	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632902808	276372593	0	0
T1	164302	1956	0	0
T2	84490	8326	0	0
T3	456016	7202	0	0
T4	140011	234438	0	0
T12	406736	393936	0	0
T13	29061	29005	0	0
T17	131539	131460	0	0
T18	84479	20899	0	0
T19	23206	23131	0	0
T20	79219	29488	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	575	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2	0	0
T4	140011	7	0	0
T5	0	3	0	0
T6	0	1	0	0
T12	406736	3	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	1	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	568	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2	0	0
T4	140011	7	0	0
T5	0	3	0	0
T6	0	1	0	0
T12	406736	3	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	1	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	564	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2	0	0
T4	140011	7	0	0
T5	0	3	0	0
T6	0	1	0	0
T12	406736	3	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	1	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	553	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2	0	0
T4	140011	7	0	0
T5	0	3	0	0
T6	0	1	0	0
T12	406736	3	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	1	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1072	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	1	0	0
T13	29061	0	0	0
T18	84479	4	0	0
T19	23206	0	0	0
T20	79219	4	0	0
T23	0	1	0	0
T25	0	5	0	0
T29	0	5	0	0
T31	0	1	0	0
T32	0	3	0	0
T37	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T45	37798	0	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	114082	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	117	0	0
T13	29061	0	0	0
T18	84479	736	0	0
T19	23206	0	0	0
T20	79219	458	0	0
T23	0	40	0	0
T25	0	499	0	0
T29	0	764	0	0
T31	0	692	0	0
T32	0	296	0	0
T37	0	46	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T45	37798	0	0	0
T75	0	128	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	973	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T14	334088	0	0	0
T18	84479	3	0	0
T19	23206	0	0	0
T20	79219	4	0	0
T25	0	4	0	0
T29	0	4	0	0
T32	0	2	0	0
T37	0	1	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T45	37798	0	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	10	0	0
T79	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	75	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	1	0	0
T13	29061	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T31	0	1	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T45	37798	0	0	0
T52	0	3	0	0
T73	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1221	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	171	0	0
T10	0	353	0	0
T11	0	203	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	332	0	0
T39	0	162	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1011	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	141	0	0
T10	0	293	0	0
T11	0	173	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	272	0	0
T39	0	132	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	632880984	0	0
T1	164302	164297	0	0
T2	84490	84418	0	0
T3	456016	456011	0	0
T4	140011	139931	0	0
T12	406736	406696	0	0
T13	29061	29006	0	0
T17	131539	131461	0	0
T18	84479	84405	0	0
T19	23206	23132	0	0
T20	79219	79161	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T12

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T13
1	0	1	Covered	T2,T4,T12
1	1	0	Covered	T4,T12,T18
1	1	1	Covered	T12,T18,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T18,T20
0	1	Covered	T20,T34,T79
1	0	Covered	T50,T52,T54

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T50,T52,T54

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T18,T20
1	0	Covered	T28
1	1	Covered	T20,T34,T79

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T12,T46,T77

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T4,T20,T43

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T3,T4,T12

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T3,T12,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T45

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T4,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T12
Phase1St	193	Covered	T3,T4,T12
Phase2St	210	Covered	T3,T4,T12
Phase3St	228	Covered	T3,T4,T12
TerminalSt	244	Covered	T3,T4,T12
TimeoutSt	154	Covered	T12,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T3,T4,T12
IdleSt->TimeoutSt	154	Covered	T12,T18,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T92,T93,T94
Phase0St->Phase1St	193	Covered	T3,T4,T12
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T31,T32,T95
Phase1St->Phase2St	210	Covered	T3,T4,T12
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T34,T35,T96
Phase2St->Phase3St	228	Covered	T3,T4,T12
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T31,T97,T98
Phase3St->TerminalSt	244	Covered	T3,T4,T12
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T4,T12
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T12,T18,T20
TimeoutSt->Phase0St	167	Covered	T20,T34,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T34,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T93,T94,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T95
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T35,T96
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T97,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	633039078	295	0	0
CheckAccumTrig0_A	633039078	467	0	0
CheckAccumTrig1_A	633039078	13	0	0
CheckClr_A	633039078	194	0	0
CheckEn_A	632902808	299744619	0	0
CheckPhase0_A	633039078	524	0	0
CheckPhase1_A	633039078	512	0	0
CheckPhase2_A	633039078	504	0	0
CheckPhase3_A	633039078	499	0	0
CheckTimeout0_A	633039078	922	0	0
CheckTimeoutSt1_A	633039078	114839	0	0
CheckTimeoutSt2_A	633039078	852	0	0
CheckTimeoutStTrig_A	633039078	54	0	0
ErrorStAllEscAsserted_A	633039078	1268	0	0
ErrorStIsTerminal_A	633039078	1058	0	0
u_state_regs_A	633039078	632880984	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	295	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	32	0	0
T10	0	80	0	0
T11	0	53	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	89	0	0
T39	0	41	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	467	0	0
T3	456016	2	0	0
T4	140011	3	0	0
T5	0	1	0	0
T6	0	1	0	0
T9	17128	0	0	0
T12	406736	6	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T23	0	1	0	0
T43	0	3	0	0
T45	37798	1	0	0
T46	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	13	0	0
T50	69942	1	0	0
T51	348291	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T58	0	1	0	0
T70	393808	0	0	0
T71	152739	0	0	0
T72	32703	0	0	0
T73	217116	0	0	0
T85	12952	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	22786	0	0	0
T107	31480	0	0	0
T108	27459	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	194	0	0
T3	456016	2	0	0
T4	140011	0	0	0
T9	17128	0	0	0
T12	406736	3	0	0
T13	29061	0	0	0
T16	0	1	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T25	0	1	0	0
T31	0	9	0	0
T32	0	6	0	0
T34	0	2	0	0
T37	0	1	0	0
T43	0	3	0	0
T45	37798	0	0	0
T74	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632902808	299744619	0	0
T1	164302	164297	0	0
T2	84490	64039	0	0
T3	456016	453918	0	0
T4	140011	103060	0	0
T12	406736	496998	0	0
T13	29061	27241	0	0
T17	131539	131460	0	0
T18	84479	17920	0	0
T19	23206	2263	0	0
T20	79219	18757	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	524	0	0
T3	456016	2	0	0
T4	140011	3	0	0
T5	0	1	0	0
T6	0	1	0	0
T9	17128	0	0	0
T12	406736	6	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	3	0	0
T45	37798	1	0	0
T46	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	512	0	0
T3	456016	2	0	0
T4	140011	3	0	0
T5	0	1	0	0
T6	0	1	0	0
T9	17128	0	0	0
T12	406736	6	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	3	0	0
T45	37798	1	0	0
T46	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	504	0	0
T3	456016	2	0	0
T4	140011	3	0	0
T5	0	1	0	0
T6	0	1	0	0
T9	17128	0	0	0
T12	406736	6	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	3	0	0
T45	37798	1	0	0
T46	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	499	0	0
T3	456016	2	0	0
T4	140011	3	0	0
T5	0	1	0	0
T6	0	1	0	0
T9	17128	0	0	0
T12	406736	6	0	0
T13	29061	0	0	0
T16	0	2	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	3	0	0
T45	37798	1	0	0
T46	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	922	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	1	0	0
T13	29061	0	0	0
T18	84479	4	0	0
T19	23206	0	0	0
T20	79219	5	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T45	37798	0	0	0
T75	0	7	0	0
T76	0	2	0	0
T77	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	114839	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	206	0	0
T13	29061	0	0	0
T18	84479	768	0	0
T19	23206	0	0	0
T20	79219	532	0	0
T31	0	35	0	0
T32	0	163	0	0
T34	0	33	0	0
T37	0	94	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T45	37798	0	0	0
T75	0	923	0	0
T76	0	218	0	0
T77	0	232	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	852	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	1	0	0
T13	29061	0	0	0
T18	84479	4	0	0
T19	23206	0	0	0
T20	79219	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T37	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T45	37798	0	0	0
T75	0	7	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	54	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T20	79219	1	0	0
T26	0	1	0	0
T34	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T45	37798	0	0	0
T51	0	2	0	0
T79	0	2	0	0
T82	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1268	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	180	0	0
T10	0	341	0	0
T11	0	191	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	358	0	0
T39	0	198	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1058	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	150	0	0
T10	0	281	0	0
T11	0	161	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	298	0	0
T39	0	168	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	632880984	0	0
T1	164302	164297	0	0
T2	84490	84418	0	0
T3	456016	456011	0	0
T4	140011	139931	0	0
T12	406736	406696	0	0
T13	29061	29006	0	0
T17	131539	131461	0	0
T18	84479	84405	0	0
T19	23206	23132	0	0
T20	79219	79161	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T18
1	0	1	Covered	T2,T4,T12
1	1	0	Covered	T4,T20,T45
1	1	1	Covered	T4,T18,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T18,T20
0	1	Covered	T18,T20,T64
1	0	Covered	T25,T29,T113

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T29,T113

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T20
1	0	Covered	T26
1	1	Covered	T18,T20,T64

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T12,T29

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T12,T45

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T12,T20

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T4,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T4,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T4,T18,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T114,T93
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T29,T77,T115
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T78,T116,T97
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T97,T117,T118
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T4,T12
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T4,T20,T46
TimeoutSt->Phase0St	167	Covered	T18,T20,T64

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T64
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T20,T46
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T114,T93,T119
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T77,T115
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T78,T116,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T97,T117,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	633039078	236	0	0
CheckAccumTrig0_A	633039078	458	0	0
CheckAccumTrig1_A	633039078	21	0	0
CheckClr_A	633039078	185	0	0
CheckEn_A	632902808	251388286	0	0
CheckPhase0_A	633039078	533	0	0
CheckPhase1_A	633039078	524	0	0
CheckPhase2_A	633039078	514	0	0
CheckPhase3_A	633039078	507	0	0
CheckTimeout0_A	633039078	1340	0	0
CheckTimeoutSt1_A	633039078	161319	0	0
CheckTimeoutSt2_A	633039078	1256	0	0
CheckTimeoutStTrig_A	633039078	61	0	0
ErrorStAllEscAsserted_A	633039078	1248	0	0
ErrorStIsTerminal_A	633039078	1038	0	0
u_state_regs_A	633039078	632880984	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	236	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	38	0	0
T10	0	79	0	0
T11	0	10	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	63	0	0
T39	0	46	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	458	0	0
T1	164302	1	0	0
T2	84490	1	0	0
T3	456016	5	0	0
T4	140011	9	0	0
T5	0	9	0	0
T12	406736	4	0	0
T13	29061	0	0	0
T16	0	1	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	21	0	0
T25	354877	1	0	0
T29	113592	1	0	0
T30	25283	0	0	0
T34	18395	0	0	0
T37	118501	0	0	0
T56	0	1	0	0
T65	161797	0	0	0
T66	176487	0	0	0
T67	9931	0	0	0
T68	494171	0	0	0
T69	58333	0	0	0
T92	0	1	0	0
T103	0	2	0	0
T111	0	1	0	0
T113	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	185	0	0
T3	456016	4	0	0
T4	140011	3	0	0
T5	0	5	0	0
T9	17128	0	0	0
T12	406736	1	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T25	0	1	0	0
T29	0	3	0	0
T37	0	1	0	0
T43	0	1	0	0
T45	37798	0	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632902808	251388286	0	0
T1	164302	5786	0	0
T2	84490	13744	0	0
T3	456016	9848	0	0
T4	140011	316552	0	0
T12	406736	496601	0	0
T13	29061	29005	0	0
T17	131539	131460	0	0
T18	84479	2071	0	0
T19	23206	21463	0	0
T20	79219	40665	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	533	0	0
T1	164302	1	0	0
T2	84490	1	0	0
T3	456016	5	0	0
T4	140011	9	0	0
T5	0	8	0	0
T12	406736	4	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	524	0	0
T1	164302	1	0	0
T2	84490	1	0	0
T3	456016	5	0	0
T4	140011	9	0	0
T5	0	8	0	0
T12	406736	4	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	514	0	0
T1	164302	1	0	0
T2	84490	1	0	0
T3	456016	5	0	0
T4	140011	9	0	0
T5	0	8	0	0
T12	406736	4	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	507	0	0
T1	164302	1	0	0
T2	84490	1	0	0
T3	456016	5	0	0
T4	140011	9	0	0
T5	0	8	0	0
T12	406736	4	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T43	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1340	0	0
T4	140011	2	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	0	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	5	0	0
T25	0	4	0	0
T29	0	6	0	0
T34	0	4	0	0
T37	0	1	0	0
T45	37798	0	0	0
T46	0	1	0	0
T64	0	2	0	0
T67	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	161319	0	0
T4	140011	82	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	0	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	148	0	0
T19	23206	0	0	0
T20	79219	510	0	0
T25	0	332	0	0
T29	0	753	0	0
T34	0	303	0	0
T37	0	39	0	0
T45	37798	0	0	0
T46	0	119	0	0
T64	0	24	0	0
T67	0	473	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1256	0	0
T4	140011	2	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T12	406736	0	0	0
T13	29061	0	0	0
T17	131539	0	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	4	0	0
T25	0	3	0	0
T29	0	3	0	0
T34	0	4	0	0
T37	0	1	0	0
T45	37798	0	0	0
T46	0	1	0	0
T64	0	1	0	0
T67	0	3	0	0
T76	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	61	0	0
T5	568343	0	0	0
T9	17128	0	0	0
T14	334088	0	0	0
T18	84479	1	0	0
T19	23206	0	0	0
T20	79219	1	0	0
T29	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T45	37798	0	0	0
T58	0	1	0	0
T64	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0
T101	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1248	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	167	0	0
T10	0	351	0	0
T11	0	172	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	369	0	0
T39	0	189	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1038	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	137	0	0
T10	0	291	0	0
T11	0	142	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	309	0	0
T39	0	159	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	632880984	0	0
T1	164302	164297	0	0
T2	84490	84418	0	0
T3	456016	456011	0	0
T4	140011	139931	0	0
T12	406736	406696	0	0
T13	29061	29006	0	0
T17	131539	131461	0	0
T18	84479	84405	0	0
T19	23206	23132	0	0
T20	79219	79161	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T1,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T13
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T12,T13
1	1	1	Covered	T18,T20,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T5
0	1	Covered	T5,T64,T29
1	0	Covered	T23,T24,T29

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T20,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T24,T29

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T5
1	0	Covered	T27
1	1	Covered	T5,T64,T29

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T12

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T13

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T3,T17

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T42,T16,T46

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T12,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T18,T20,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T1,T3,T4
IdleSt->TimeoutSt	154	Covered	T18,T20,T5
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T30,T124,T84
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T33,T52,T101
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T36,T125,T26
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T17,T37,T71
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T18,T20,T5
TimeoutSt->Phase0St	167	Covered	T5,T23,T64

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T23,T64
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T124,T126
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T101,T55
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T36,T125,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T37,T71
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	633039078	219	0	0
CheckAccumTrig0_A	633039078	773	0	0
CheckAccumTrig1_A	633039078	44	0	0
CheckClr_A	633039078	388	0	0
CheckEn_A	632902808	231757572	0	0
CheckPhase0_A	633039078	883	0	0
CheckPhase1_A	633039078	863	0	0
CheckPhase2_A	633039078	847	0	0
CheckPhase3_A	633039078	834	0	0
CheckTimeout0_A	633039078	786	0	0
CheckTimeoutSt1_A	633039078	90683	0	0
CheckTimeoutSt2_A	633039078	652	0	0
CheckTimeoutStTrig_A	633039078	87	0	0
ErrorStAllEscAsserted_A	633039078	1273	0	0
ErrorStIsTerminal_A	633039078	1063	0	0
u_state_regs_A	633039078	632880984	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	219	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	34	0	0
T10	0	73	0	0
T11	0	21	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	66	0	0
T39	0	25	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	773	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	3	0	0
T4	140011	4	0	0
T5	0	3	0	0
T12	406736	4	0	0
T13	29061	1	0	0
T17	131539	2	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	44	0	0
T23	61067	1	0	0
T24	4595	1	0	0
T25	354877	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T55	0	5	0	0
T58	0	1	0	0
T61	39465	0	0	0
T62	646041	0	0	0
T63	64351	0	0	0
T64	6232	0	0	0
T65	161797	0	0	0
T66	176487	0	0	0
T67	9931	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	388	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	2	0	0
T4	140011	2	0	0
T5	0	1	0	0
T12	406736	0	0	0
T13	29061	0	0	0
T17	131539	1	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T23	0	2	0	0
T40	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T61	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	632902808	231757572	0	0
T1	164302	163651	0	0
T2	84490	26253	0	0
T3	456016	13600	0	0
T4	140011	723843	0	0
T12	406736	286071	0	0
T13	29061	2355	0	0
T17	131539	3253	0	0
T18	84479	14011	0	0
T19	23206	23131	0	0
T20	79219	27841	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	883	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	3	0	0
T4	140011	4	0	0
T5	0	4	0	0
T12	406736	4	0	0
T13	29061	1	0	0
T17	131539	2	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	863	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	3	0	0
T4	140011	4	0	0
T5	0	4	0	0
T12	406736	4	0	0
T13	29061	1	0	0
T17	131539	2	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	847	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	3	0	0
T4	140011	4	0	0
T5	0	4	0	0
T12	406736	4	0	0
T13	29061	1	0	0
T17	131539	2	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	834	0	0
T1	164302	1	0	0
T2	84490	0	0	0
T3	456016	3	0	0
T4	140011	4	0	0
T5	0	4	0	0
T12	406736	4	0	0
T13	29061	1	0	0
T17	131539	1	0	0
T18	84479	0	0	0
T19	23206	0	0	0
T20	79219	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	786	0	0
T5	568343	3	0	0
T9	17128	0	0	0
T14	334088	0	0	0
T18	84479	7	0	0
T19	23206	0	0	0
T20	79219	4	0	0
T23	0	2	0	0
T24	0	1	0	0
T29	0	10	0	0
T37	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	0	1	0	0
T45	37798	0	0	0
T63	0	1	0	0
T64	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	90683	0	0
T5	568343	470	0	0
T9	17128	0	0	0
T14	334088	0	0	0
T18	84479	1300	0	0
T19	23206	0	0	0
T20	79219	437	0	0
T23	0	67	0	0
T24	0	10	0	0
T29	0	569	0	0
T37	0	414	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	0	198	0	0
T45	37798	0	0	0
T63	0	124	0	0
T64	0	228	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	652	0	0
T5	568343	1	0	0
T9	17128	0	0	0
T14	334088	0	0	0
T18	84479	7	0	0
T19	23206	0	0	0
T20	79219	4	0	0
T23	0	1	0	0
T29	0	8	0	0
T34	0	1	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	0	1	0	0
T45	37798	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T75	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	87	0	0
T5	568343	1	0	0
T6	817532	0	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T16	433332	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T37	0	2	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0
T64	0	1	0	0
T77	0	5	0	0
T78	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1273	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	174	0	0
T10	0	374	0	0
T11	0	161	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	329	0	0
T39	0	235	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	1063	0	0
T5	568343	0	0	0
T6	817532	0	0	0
T9	17128	144	0	0
T10	0	314	0	0
T11	0	131	0	0
T14	334088	0	0	0
T15	36791	0	0	0
T38	0	269	0	0
T39	0	205	0	0
T40	78257	0	0	0
T41	1089	0	0	0
T42	22074	0	0	0
T43	59027	0	0	0
T44	17203	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633039078	632880984	0	0
T1	164302	164297	0	0
T2	84490	84418	0	0
T3	456016	456011	0	0
T4	140011	139931	0	0
T12	406736	406696	0	0
T13	29061	29006	0	0
T17	131539	131461	0	0
T18	84479	84405	0	0
T19	23206	23132	0	0
T20	79219	79161	0	0