Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65144109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31465207

1

T1

97761

T2

148548

T3

153286

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14377303	1			T1	37805		T2	58770		T3	59443
values[0x0]	40142607	1			T1	135482		T2	205055		T3	211372
values[0x1]	42089406	1			T1	134330		T2	205171		T3	212020

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55714978	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40894338

1

T1

123564

T2

187750

T3

193506

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	291220	1			T1	1185		T14	1568		T15	32
valid_sources[0x01]	308103	1			T1	1209		T14	1404		T15	25
valid_sources[0x02]	301453	1			T1	1215		T14	1670		T15	39
valid_sources[0x03]	301725	1			T1	1190		T14	1341		T15	24
valid_sources[0x04]	283413	1			T1	1198		T14	1332		T15	31
valid_sources[0x05]	291148	1			T1	1137		T14	1624		T15	30
valid_sources[0x06]	296658	1			T1	1215		T14	1411		T15	30
valid_sources[0x07]	598330	1			T1	1192		T14	1388		T15	34
valid_sources[0x08]	291084	1			T1	1183		T14	1411		T15	31
valid_sources[0x09]	320135	1			T1	1213		T14	1464		T15	38
valid_sources[0x0a]	298234	1			T1	1185		T14	1490		T15	25
valid_sources[0x0b]	759910	1			T1	1182		T2	468996		T14	1491
valid_sources[0x0c]	287788	1			T1	1251		T14	1652		T15	28
valid_sources[0x0d]	289265	1			T1	1234		T14	1466		T15	28
valid_sources[0x0e]	290881	1			T1	1232		T14	1270		T15	41
valid_sources[0x0f]	287395	1			T1	1216		T14	1365		T15	27
valid_sources[0x10]	298697	1			T1	1232		T14	1435		T15	38
valid_sources[0x11]	362386	1			T1	1267		T14	1545		T15	34
valid_sources[0x12]	306985	1			T1	1149		T14	1519		T15	42
valid_sources[0x13]	288313	1			T1	1176		T14	1410		T15	33
valid_sources[0x14]	294759	1			T1	1247		T14	1488		T15	29
valid_sources[0x15]	305081	1			T1	1184		T14	1421		T15	24
valid_sources[0x16]	293548	1			T1	1196		T14	1402		T15	41
valid_sources[0x17]	752920	1			T1	1203		T14	1379		T15	16
valid_sources[0x18]	293376	1			T1	1237		T14	1451		T15	32
valid_sources[0x19]	288090	1			T1	1165		T14	1620		T15	32
valid_sources[0x1a]	292538	1			T1	1208		T14	1487		T15	25
valid_sources[0x1b]	297820	1			T1	1259		T14	1551		T15	29
valid_sources[0x1c]	284258	1			T1	1172		T14	1311		T15	36
valid_sources[0x1d]	294533	1			T1	1243		T14	1372		T15	39
valid_sources[0x1e]	292576	1			T1	1219		T14	1444		T15	35
valid_sources[0x1f]	294656	1			T1	1167		T14	1518		T15	30
valid_sources[0x20]	296330	1			T1	1165		T14	1405		T15	36
valid_sources[0x21]	299113	1			T1	1237		T14	1529		T15	33
valid_sources[0x22]	780506	1			T1	1222		T14	1507		T15	32
valid_sources[0x23]	596793	1			T1	1156		T14	1436		T15	28
valid_sources[0x24]	298745	1			T1	1158		T14	1651		T15	25
valid_sources[0x25]	296316	1			T1	1194		T14	1481		T15	38
valid_sources[0x26]	296318	1			T1	1264		T14	1240		T15	31
valid_sources[0x27]	286416	1			T1	1181		T14	1501		T15	30
valid_sources[0x28]	289161	1			T1	1158		T14	1460		T15	30
valid_sources[0x29]	299166	1			T1	1232		T14	1503		T15	36
valid_sources[0x2a]	316144	1			T1	1178		T14	1446		T15	35
valid_sources[0x2b]	603392	1			T1	1263		T14	1523		T15	33
valid_sources[0x2c]	287702	1			T1	1216		T14	1452		T15	38
valid_sources[0x2d]	283825	1			T1	1197		T14	1564		T15	35
valid_sources[0x2e]	531057	1			T1	1207		T14	1415		T15	27
valid_sources[0x2f]	310234	1			T1	1172		T14	1483		T15	31
valid_sources[0x30]	304678	1			T1	1212		T14	1317		T15	23
valid_sources[0x31]	291952	1			T1	1213		T14	1508		T15	38
valid_sources[0x32]	297866	1			T1	1240		T14	1544		T15	36
valid_sources[0x33]	305645	1			T1	1199		T14	1353		T15	33
valid_sources[0x34]	299717	1			T1	1185		T14	1446		T15	22
valid_sources[0x35]	292132	1			T1	1140		T14	1521		T15	27
valid_sources[0x36]	292930	1			T1	1109		T14	1409		T15	29
valid_sources[0x37]	289230	1			T1	1229		T14	1419		T15	38
valid_sources[0x38]	295397	1			T1	1192		T14	1395		T15	33
valid_sources[0x39]	292939	1			T1	1176		T14	1458		T15	28
valid_sources[0x3a]	284970	1			T1	1227		T14	1474		T15	38
valid_sources[0x3b]	288126	1			T1	1177		T14	1593		T15	37
valid_sources[0x3c]	296910	1			T1	1197		T14	1455		T15	33
valid_sources[0x3d]	327508	1			T1	1166		T14	1500		T15	34
valid_sources[0x3e]	877260	1			T1	1158		T14	1395		T15	35
valid_sources[0x3f]	294380	1			T1	1217		T14	1315		T15	35
valid_sources[0x40]	294726	1			T1	1223		T14	1425		T15	34
valid_sources[0x41]	293097	1			T1	1187		T14	1600		T15	36
valid_sources[0x42]	927073	1			T1	1242		T14	1490		T15	35
valid_sources[0x43]	754185	1			T1	1222		T14	1535		T15	33
valid_sources[0x44]	501879	1			T1	1215		T14	1363		T15	28
valid_sources[0x45]	330587	1			T1	1153		T14	1431		T15	28
valid_sources[0x46]	295165	1			T1	1168		T14	1482		T15	38
valid_sources[0x47]	289290	1			T1	1185		T14	1523		T15	32
valid_sources[0x48]	689690	1			T1	1177		T14	1492		T15	27
valid_sources[0x49]	703523	1			T1	1223		T14	1411		T15	40
valid_sources[0x4a]	301066	1			T1	1182		T14	1593		T15	34
valid_sources[0x4b]	289113	1			T1	1213		T14	1339		T15	28
valid_sources[0x4c]	302032	1			T1	1241		T14	1356		T15	38
valid_sources[0x4d]	775618	1			T1	1271		T3	482835		T14	1418
valid_sources[0x4e]	305742	1			T1	1206		T14	1681		T15	23
valid_sources[0x4f]	296102	1			T1	1204		T14	1593		T15	28
valid_sources[0x50]	292532	1			T1	1158		T14	1383		T15	33
valid_sources[0x51]	304051	1			T1	1163		T14	1439		T15	33
valid_sources[0x52]	290690	1			T1	1212		T14	1482		T15	32
valid_sources[0x53]	292308	1			T1	1180		T14	1302		T15	52
valid_sources[0x54]	672739	1			T1	1119		T14	1592		T15	31
valid_sources[0x55]	328542	1			T1	1263		T14	1395		T15	35
valid_sources[0x56]	299316	1			T1	1202		T14	1518		T15	26
valid_sources[0x57]	299010	1			T1	1170		T14	1488		T15	30
valid_sources[0x58]	657902	1			T1	1168		T14	1488		T15	26
valid_sources[0x59]	310417	1			T1	1214		T14	1525		T15	30
valid_sources[0x5a]	701159	1			T1	1166		T14	1405		T15	27
valid_sources[0x5b]	644069	1			T1	1155		T14	1543		T15	29
valid_sources[0x5c]	290019	1			T1	1254		T14	1492		T15	42
valid_sources[0x5d]	300377	1			T1	1250		T14	1624		T15	50
valid_sources[0x5e]	294628	1			T1	1229		T14	1376		T15	33
valid_sources[0x5f]	288356	1			T1	1208		T14	1565		T15	29
valid_sources[0x60]	295306	1			T1	1183		T14	1599		T15	29
valid_sources[0x61]	298162	1			T1	1225		T14	1349		T15	31
valid_sources[0x62]	318036	1			T1	1257		T14	1430		T15	32
valid_sources[0x63]	315542	1			T1	1203		T14	1419		T15	31
valid_sources[0x64]	289509	1			T1	1182		T14	1432		T15	36
valid_sources[0x65]	628742	1			T1	1159		T14	1484		T15	52
valid_sources[0x66]	745541	1			T1	1210		T14	1528		T15	45
valid_sources[0x67]	770725	1			T1	1185		T14	1409		T15	25
valid_sources[0x68]	297920	1			T1	1218		T14	1434		T15	37
valid_sources[0x69]	291047	1			T1	1171		T14	1325		T15	34
valid_sources[0x6a]	292451	1			T1	1169		T14	1413		T15	40
valid_sources[0x6b]	297757	1			T1	1256		T14	1308		T15	25
valid_sources[0x6c]	298057	1			T1	1207		T14	1429		T15	29
valid_sources[0x6d]	287605	1			T1	1223		T14	1561		T15	33
valid_sources[0x6e]	302705	1			T1	1207		T14	1451		T15	40
valid_sources[0x6f]	299985	1			T1	1190		T14	1510		T15	29
valid_sources[0x70]	557971	1			T1	1178		T14	1421		T15	30
valid_sources[0x71]	638733	1			T1	1177		T14	1626		T15	30
valid_sources[0x72]	587557	1			T1	1215		T14	1572		T15	36
valid_sources[0x73]	291236	1			T1	1225		T14	1418		T15	45
valid_sources[0x74]	304279	1			T1	1160		T14	1556		T15	43
valid_sources[0x75]	304500	1			T1	1225		T14	1401		T15	32
valid_sources[0x76]	938433	1			T1	1248		T14	1345		T15	36
valid_sources[0x77]	615229	1			T1	1161		T14	1457		T15	27
valid_sources[0x78]	290367	1			T1	1230		T14	1512		T15	36
valid_sources[0x79]	310552	1			T1	1233		T14	1383		T15	25
valid_sources[0x7a]	292182	1			T1	1244		T14	1464		T15	28
valid_sources[0x7b]	295663	1			T1	1141		T14	1437		T15	34
valid_sources[0x7c]	283351	1			T1	1202		T14	1468		T15	30
valid_sources[0x7d]	291617	1			T1	1259		T14	1454		T15	29
valid_sources[0x7e]	293071	1			T1	1155		T14	1540		T15	41
valid_sources[0x7f]	291529	1			T1	1170		T14	1461		T15	33
valid_sources[0x80]	837216	1			T1	1169		T14	1419		T15	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7159411

1

T1

18940

T2

29302

T3

29852

values[0x0]

all_enables

biggest_size

15349400

1

T1

50605

T2

76621

T3

78830

values[0x1]

all_enables

biggest_size

8956396

1

T1

28216

T2

42625

T3

44604