Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T70,T126
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13740	0	0
DisabledNoTrigBkwd_A	2147483647	752564	0	0
DisabledNoTrigFwd_A	2147483647	1685533388	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13740	0	0
T23	110391	0	0	0
T26	85374	0	0	0
T37	3973	613	0	0
T38	3514	425	0	0
T70	0	316	0	0
T74	148316	0	0	0
T75	547820	0	0	0
T81	56864	0	0	0
T83	34826	0	0	0
T89	118697	0	0	0
T126	1196	399	0	0
T197	1646	579	0	0
T198	0	700	0	0
T199	0	890	0	0
T200	0	914	0	0
T201	0	681	0	0
T202	0	727	0	0
T203	0	184	0	0
T204	0	621	0	0
T205	0	1363	0	0
T206	0	1166	0	0
T207	0	589	0	0
T208	0	535	0	0
T209	0	454	0	0
T210	0	362	0	0
T211	0	718	0	0
T212	0	1504	0	0
T213	65498	0	0	0
T214	16704	0	0	0
T215	37641	0	0	0
T216	224893	0	0	0
T217	56324	0	0	0
T218	266261	0	0	0
T219	49186	0	0	0
T220	81332	0	0	0
T221	970830	0	0	0
T222	497321	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	752564	0	0
T1	716340	317	0	0
T2	760376	4918	0	0
T3	2158956	2075	0	0
T4	526148	1	0	0
T5	494776	0	0	0
T6	0	6	0	0
T10	675944	7303	0	0
T11	0	187	0	0
T12	0	8	0	0
T14	1653160	1508	0	0
T15	117524	103	0	0
T16	238772	22	0	0
T17	66532	0	0	0
T18	0	364	0	0
T19	0	228	0	0
T20	0	2	0	0
T39	34069	69	0	0
T40	0	54	0	0
T41	0	14	0	0
T43	0	1822	0	0
T44	0	394	0	0
T45	0	13	0	0
T46	0	67	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1685533388	0	0
T1	955120	715647	0	0
T2	760376	383519	0	0
T3	2158956	1621190	0	0
T4	526148	1311554	0	0
T5	494776	259791	0	0
T10	675944	193101	0	0
T14	1653160	1624570	0	0
T15	117524	89590	0	0
T16	238772	176898	0	0
T17	66532	28360	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T14
1	1	Covered	T2,T3,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T70,T209
1	1	Covered	T2,T3,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744510807	1711	0	0
DisabledNoTrigBkwd_A	744510807	279037	0	0
DisabledNoTrigFwd_A	744510807	367527903	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	1711	0	0
T23	110391	0	0	0
T26	85374	0	0	0
T70	0	316	0	0
T74	148316	0	0	0
T75	547820	0	0	0
T81	56864	0	0	0
T83	34826	0	0	0
T197	1646	579	0	0
T209	0	454	0	0
T210	0	362	0	0
T213	65498	0	0	0
T214	16704	0	0	0
T215	37641	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	279037	0	0
T2	190094	1930	0	0
T3	539739	2075	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	6056	0	0
T14	413290	175	0	0
T15	29381	103	0	0
T16	59693	22	0	0
T17	16633	0	0	0
T18	0	109	0	0
T20	0	2	0	0
T39	34069	69	0	0
T40	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	367527903	0	0
T1	238780	238772	0	0
T2	190094	4563	0	0
T3	539739	3078	0	0
T4	131537	39370	0	0
T5	123694	14635	0	0
T10	168986	9460	0	0
T14	413290	336234	0	0
T15	29381	3360	0	0
T16	59693	3151	0	0
T17	16633	785	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T200,T203
1	1	Covered	T1,T2,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744510807	3215	0	0
DisabledNoTrigBkwd_A	744510807	153229	0	0
DisabledNoTrigFwd_A	744510807	426090811	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	3215	0	0
T37	3973	613	0	0
T38	3514	0	0	0
T89	118697	0	0	0
T200	0	914	0	0
T203	0	184	0	0
T212	0	1504	0	0
T216	224893	0	0	0
T217	56324	0	0	0
T218	266261	0	0	0
T219	49186	0	0	0
T220	81332	0	0	0
T221	970830	0	0	0
T222	497321	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	153229	0	0
T1	238780	4	0	0
T2	190094	3	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T6	0	6	0	0
T10	168986	467	0	0
T11	0	129	0	0
T14	413290	136	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	228	0	0
T40	0	19	0	0
T45	0	13	0	0
T46	0	67	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	426090811	0	0
T1	238780	237240	0	0
T2	190094	189024	0	0
T3	539739	539732	0	0
T4	131537	988254	0	0
T5	123694	95190	0	0
T10	168986	12997	0	0
T14	413290	356521	0	0
T15	29381	29305	0	0
T16	59693	59578	0	0
T17	16633	13315	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T126,T198,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744510807	4622	0	0
DisabledNoTrigBkwd_A	744510807	147927	0	0
DisabledNoTrigFwd_A	744510807	429916074	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	4622	0	0
T7	41784	0	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T52	429473	0	0	0
T88	11321	0	0	0
T126	1196	399	0	0
T198	0	700	0	0
T199	0	890	0	0
T201	0	681	0	0
T205	0	1363	0	0
T207	0	589	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	147927	0	0
T1	238780	2	0	0
T2	190094	5	0	0
T3	539739	0	0	0
T4	131537	1	0	0
T5	123694	0	0	0
T10	168986	3	0	0
T11	0	53	0	0
T14	413290	160	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	103	0	0
T41	0	7	0	0
T43	0	1822	0	0
T44	0	394	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	429916074	0	0
T1	238780	237628	0	0
T2	190094	189338	0	0
T3	539739	538648	0	0
T4	131537	156147	0	0
T5	123694	118838	0	0
T10	168986	168571	0	0
T14	413290	376405	0	0
T15	29381	27620	0	0
T16	59693	59578	0	0
T17	16633	4044	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T3,T14,T4
1	1	Covered	T1,T2,T14

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T202,T204
1	1	Covered	T1,T2,T14

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744510807	4192	0	0
DisabledNoTrigBkwd_A	744510807	172371	0	0
DisabledNoTrigFwd_A	744510807	461998600	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	4192	0	0
T38	3514	425	0	0
T89	118697	0	0	0
T105	103145	0	0	0
T202	0	727	0	0
T204	0	621	0	0
T206	0	1166	0	0
T208	0	535	0	0
T211	0	718	0	0
T216	224893	0	0	0
T217	56324	0	0	0
T218	266261	0	0	0
T219	49186	0	0	0
T220	81332	0	0	0
T221	970830	0	0	0
T222	497321	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	172371	0	0
T1	238780	311	0	0
T2	190094	2980	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	777	0	0
T11	0	5	0	0
T12	0	8	0	0
T14	413290	1037	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	152	0	0
T40	0	27	0	0
T41	0	7	0	0
T42	0	4084	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	461998600	0	0
T1	238780	2007	0	0
T2	190094	594	0	0
T3	539739	539732	0	0
T4	131537	127783	0	0
T5	123694	31128	0	0
T10	168986	2073	0	0
T14	413290	555410	0	0
T15	29381	29305	0	0
T16	59693	54591	0	0
T17	16633	10216	0	0