Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T15,T16
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T14,T15,T16
1	1	1	Covered	T14,T10,T17

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T10,T17
0	1	Covered	T14,T17,T19
1	0	Covered	T14,T20,T11

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T10,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T14,T20,T11

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T10,T17
1	0	Covered	T21,T22
1	1	Covered	T14,T17,T19

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T10

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T14,T6

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T14,T15

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T7,T8,T9
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T14,T10,T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T7,T8,T9
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T14,T10,T17
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T11,T23,T24
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T10,T20,T25
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T3,T17,T19
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T19,T26,T27
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T2,T14,T10
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T14,T10,T17
TimeoutSt->Phase0St	167	Covered	T14,T17,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T10,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T10,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T10,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T23,T24
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T20,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T17,T19
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T26,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T14,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	767	0	0
CheckAccumTrig0_A	2147483647	2336	0	0
CheckAccumTrig1_A	2147483647	99	0	0
CheckClr_A	2147483647	1033	0	0
CheckEn_A	2147483647	1373380158	0	0
CheckPhase0_A	2147483647	2647	0	0
CheckPhase1_A	2147483647	2607	0	0
CheckPhase2_A	2147483647	2569	0	0
CheckPhase3_A	2147483647	2526	0	0
CheckTimeout0_A	2147483647	2671	0	0
CheckTimeoutSt1_A	2147483647	328635	0	0
CheckTimeoutSt2_A	2147483647	2297	0	0
CheckTimeoutStTrig_A	2147483647	262	0	0
ErrorStAllEscAsserted_A	2147483647	4266	0	0
ErrorStIsTerminal_A	2147483647	3546	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	767	0	0
T7	167136	262	0	0
T8	0	117	0	0
T9	0	142	0	0
T28	0	142	0	0
T29	0	104	0	0
T30	58992	0	0	0
T31	21716	0	0	0
T32	175240	0	0	0
T33	176592	0	0	0
T34	591536	0	0	0
T35	270548	0	0	0
T36	77324	0	0	0
T37	15892	0	0	0
T38	14056	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2336	0	0
T1	716340	3	0	0
T2	760376	5	0	0
T3	2158956	2	0	0
T4	526148	1	0	0
T5	494776	0	0	0
T6	0	1	0	0
T10	675944	9	0	0
T11	0	11	0	0
T12	0	1	0	0
T14	1653160	13	0	0
T15	117524	1	0	0
T16	238772	1	0	0
T17	66532	0	0	0
T18	0	3	0	0
T19	0	3	0	0
T39	34069	2	0	0
T40	0	3	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99	0	0
T6	149575	0	0	0
T11	1376654	1	0	0
T12	1831954	0	0	0
T13	249150	0	0	0
T18	90635	0	0	0
T19	557456	0	0	0
T20	22810	2	0	0
T24	0	2	0	0
T27	0	1	0	0
T40	158007	0	0	0
T41	87614	0	0	0
T42	942742	0	0	0
T43	330284	0	0	0
T44	371016	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	590046	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	209316	0	0	0
T65	10266	0	0	0
T66	12903	0	0	0
T67	41085	0	0	0
T68	30437	0	0	0
T69	761973	0	0	0
T70	2752	0	0	0
T71	65220	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1033	0	0
T2	380188	2	0	0
T3	1079478	1	0	0
T4	526148	0	0	0
T5	494776	0	0	0
T10	675944	6	0	0
T11	0	3	0	0
T14	1653160	6	0	0
T15	117524	0	0	0
T16	238772	0	0	0
T17	66532	1	0	0
T19	0	14	0	0
T20	45620	1	0	0
T23	0	3	0	0
T24	0	9	0	0
T25	0	2	0	0
T39	136276	1	0	0
T40	316014	0	0	0
T46	0	5	0	0
T47	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	7	0	0
T78	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1373380158	0	0
T1	955120	255841	0	0
T2	760376	194771	0	0
T3	2158956	1621190	0	0
T4	526148	1252569	0	0
T5	494776	259789	0	0
T10	675944	193101	0	0
T14	1653160	1666527	0	0
T15	117524	89587	0	0
T16	238772	176891	0	0
T17	66532	28359	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2647	0	0
T1	716340	2	0	0
T2	760376	4	0	0
T3	2158956	2	0	0
T4	526148	1	0	0
T5	494776	0	0	0
T6	0	1	0	0
T10	675944	6	0	0
T11	0	3	0	0
T14	1653160	9	0	0
T15	117524	1	0	0
T16	238772	1	0	0
T17	66532	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T39	34069	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2607	0	0
T1	716340	2	0	0
T2	760376	4	0	0
T3	2158956	2	0	0
T4	526148	1	0	0
T5	494776	0	0	0
T6	0	1	0	0
T10	675944	6	0	0
T11	0	3	0	0
T14	1653160	9	0	0
T15	117524	1	0	0
T16	238772	1	0	0
T17	66532	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T39	34069	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2569	0	0
T1	716340	2	0	0
T2	760376	4	0	0
T3	2158956	1	0	0
T4	526148	1	0	0
T5	494776	0	0	0
T6	0	1	0	0
T10	675944	6	0	0
T11	0	3	0	0
T14	1653160	9	0	0
T15	117524	1	0	0
T16	238772	1	0	0
T17	66532	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T39	34069	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2526	0	0
T1	716340	2	0	0
T2	760376	4	0	0
T3	2158956	1	0	0
T4	526148	1	0	0
T5	494776	0	0	0
T6	0	1	0	0
T10	675944	6	0	0
T11	0	3	0	0
T14	1653160	9	0	0
T15	117524	1	0	0
T16	238772	1	0	0
T17	66532	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T39	34069	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2671	0	0
T4	394611	0	0	0
T5	371082	0	0	0
T6	149575	0	0	0
T10	506958	2	0	0
T11	688327	7	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T14	1239870	32	0	0
T15	88143	0	0	0
T16	179079	0	0	0
T17	66532	5	0	0
T18	90635	0	0	0
T19	0	12	0	0
T20	91240	2	0	0
T24	0	2	0	0
T25	0	11	0	0
T27	0	22	0	0
T39	136276	0	0	0
T40	632028	0	0	0
T41	43807	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	15	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	5	0	0
T77	0	7	0	0
T79	0	2	0	0
T80	0	7	0	0
T81	0	1	0	0
T82	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328635	0	0
T4	394611	0	0	0
T5	371082	0	0	0
T6	149575	0	0	0
T10	506958	61	0	0
T11	688327	462	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T14	1239870	5533	0	0
T15	88143	0	0	0
T16	179079	0	0	0
T17	66532	355	0	0
T18	90635	0	0	0
T19	0	904	0	0
T20	91240	8	0	0
T24	0	252	0	0
T25	0	1177	0	0
T27	0	3125	0	0
T39	136276	0	0	0
T40	632028	0	0	0
T41	43807	0	0	0
T42	0	46	0	0
T45	0	21	0	0
T46	0	2131	0	0
T65	0	81	0	0
T74	0	40	0	0
T75	0	550	0	0
T77	0	1074	0	0
T79	0	221	0	0
T80	0	940	0	0
T81	0	80	0	0
T82	0	502	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2297	0	0
T4	394611	0	0	0
T5	371082	0	0	0
T6	149575	0	0	0
T10	506958	2	0	0
T11	688327	4	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T14	1239870	29	0	0
T15	88143	0	0	0
T16	179079	0	0	0
T17	66532	3	0	0
T18	90635	0	0	0
T19	0	8	0	0
T20	91240	0	0	0
T24	0	2	0	0
T25	0	10	0	0
T27	0	22	0	0
T39	136276	0	0	0
T40	632028	0	0	0
T41	43807	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	11	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	5	0	0
T76	0	2	0	0
T77	0	6	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	7	0	0
T82	0	3	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	262	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	2	0	0
T19	557456	1	0	0
T20	22810	0	0	0
T24	0	1	0	0
T25	686226	0	0	0
T27	0	1	0	0
T33	0	2	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T45	11297	0	0	0
T46	1247014	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T52	0	1	0	0
T68	0	1	0	0
T72	975608	0	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	272214	0	0	0
T82	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	238784	0	0	0
T91	803564	0	0	0
T92	200050	0	0	0
T93	97248	0	0	0
T94	125773	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4266	0	0
T7	167136	1460	0	0
T8	0	699	0	0
T9	0	679	0	0
T28	0	705	0	0
T29	0	723	0	0
T30	58992	0	0	0
T31	21716	0	0	0
T32	175240	0	0	0
T33	176592	0	0	0
T34	591536	0	0	0
T35	270548	0	0	0
T36	77324	0	0	0
T37	15892	0	0	0
T38	14056	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3546	0	0
T7	167136	1220	0	0
T8	0	579	0	0
T9	0	559	0	0
T28	0	585	0	0
T29	0	603	0	0
T30	58992	0	0	0
T31	21716	0	0	0
T32	175240	0	0	0
T33	176592	0	0	0
T34	591536	0	0	0
T35	270548	0	0	0
T36	77324	0	0	0
T37	15892	0	0	0
T38	14056	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	955120	955088	0	0
T2	760376	760352	0	0
T3	2158956	2158928	0	0
T4	526148	526112	0	0
T5	494776	494460	0	0
T10	675944	675916	0	0
T14	1653160	1652928	0	0
T15	117524	117220	0	0
T16	238772	238312	0	0
T17	66532	66284	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T14

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T15,T17
1	0	1	Covered	T2,T14,T4
1	1	0	Covered	T15,T11,T42
1	1	1	Covered	T14,T17,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T20
0	1	Covered	T14,T17,T46
1	0	Covered	T14,T20,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T17,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T20,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T20
1	0	Not Covered
1	1	Covered	T14,T17,T46

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T2,T3,T14

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T14,T15,T10

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T16,T17,T39

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T14,T19,T45

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T14,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T3,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T14,T15,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T7,T8,T9
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T14
Phase1St	193	Covered	T2,T3,T14
Phase2St	210	Covered	T2,T3,T14
Phase3St	228	Covered	T2,T3,T14
TerminalSt	244	Covered	T2,T3,T14
TimeoutSt	154	Covered	T14,T17,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T7,T8,T9
IdleSt->Phase0St	147	Covered	T2,T3,T14
IdleSt->TimeoutSt	154	Covered	T14,T17,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T11,T24,T78
Phase0St->Phase1St	193	Covered	T2,T3,T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T20,T25,T75
Phase1St->Phase2St	210	Covered	T2,T3,T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T3,T17,T46
Phase2St->Phase3St	228	Covered	T2,T3,T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T19,T26,T95
Phase3St->TerminalSt	244	Covered	T2,T3,T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T14,T10
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14,T11,T65
TimeoutSt->Phase0St	167	Covered	T14,T17,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T11,T65
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T11,T24,T78
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T25,T75
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T17,T46
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T26,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T14,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744510807	225	0	0
CheckAccumTrig0_A	744510807	923	0	0
CheckAccumTrig1_A	744510807	42	0	0
CheckClr_A	744510807	447	0	0
CheckEn_A	744396728	287359398	0	0
CheckPhase0_A	744510807	1004	0	0
CheckPhase1_A	744510807	987	0	0
CheckPhase2_A	744510807	963	0	0
CheckPhase3_A	744510807	945	0	0
CheckTimeout0_A	744510807	498	0	0
CheckTimeoutSt1_A	744510807	65228	0	0
CheckTimeoutSt2_A	744510807	396	0	0
CheckTimeoutStTrig_A	744510807	57	0	0
ErrorStAllEscAsserted_A	744510807	1105	0	0
ErrorStIsTerminal_A	744510807	925	0	0
u_state_regs_A	744510807	744359385	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	225	0	0
T7	41784	97	0	0
T8	0	35	0	0
T9	0	16	0	0
T28	0	55	0	0
T29	0	22	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	923	0	0
T2	190094	2	0	0
T3	539739	2	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	4	0	0
T11	0	6	0	0
T14	413290	3	0	0
T15	29381	1	0	0
T16	59693	1	0	0
T17	16633	0	0	0
T18	0	1	0	0
T39	34069	2	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	42	0	0
T6	149575	0	0	0
T11	688327	0	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T18	90635	0	0	0
T20	22810	2	0	0
T24	0	2	0	0
T40	158007	0	0	0
T41	43807	0	0	0
T42	471371	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T64	104658	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	447	0	0
T2	190094	1	0	0
T3	539739	1	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	3	0	0
T11	0	2	0	0
T14	413290	1	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	1	0	0
T19	0	7	0	0
T20	0	1	0	0
T39	34069	1	0	0
T46	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744396728	287359398	0	0
T1	238780	238772	0	0
T2	190094	4563	0	0
T3	539739	3078	0	0
T4	131537	39370	0	0
T5	123694	14635	0	0
T10	168986	9460	0	0
T14	413290	381723	0	0
T15	29381	3360	0	0
T16	59693	3150	0	0
T17	16633	785	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	1004	0	0
T2	190094	2	0	0
T3	539739	2	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	4	0	0
T14	413290	5	0	0
T15	29381	1	0	0
T16	59693	1	0	0
T17	16633	2	0	0
T20	0	2	0	0
T39	34069	2	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	987	0	0
T2	190094	2	0	0
T3	539739	2	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	4	0	0
T14	413290	5	0	0
T15	29381	1	0	0
T16	59693	1	0	0
T17	16633	2	0	0
T20	0	1	0	0
T39	34069	2	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	963	0	0
T2	190094	2	0	0
T3	539739	1	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	4	0	0
T14	413290	5	0	0
T15	29381	1	0	0
T16	59693	1	0	0
T17	16633	1	0	0
T20	0	1	0	0
T39	34069	2	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	945	0	0
T2	190094	2	0	0
T3	539739	1	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	4	0	0
T14	413290	5	0	0
T15	29381	1	0	0
T16	59693	1	0	0
T17	16633	1	0	0
T20	0	1	0	0
T39	34069	2	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	498	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T11	0	2	0	0
T14	413290	10	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	2	0	0
T19	0	2	0	0
T20	22810	2	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	5	0	0
T65	0	1	0	0
T75	0	2	0	0
T79	0	1	0	0
T80	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	65228	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T11	0	225	0	0
T14	413290	2313	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	126	0	0
T19	0	200	0	0
T20	22810	8	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	843	0	0
T65	0	81	0	0
T75	0	232	0	0
T79	0	89	0	0
T80	0	339	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	396	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T11	0	2	0	0
T14	413290	8	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	2	0	0
T20	22810	0	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	4	0	0
T65	0	1	0	0
T75	0	2	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	3	0	0
T83	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	57	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	2	0	0
T20	22810	0	0	0
T27	0	1	0	0
T33	0	1	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T68	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	1105	0	0
T7	41784	401	0	0
T8	0	181	0	0
T9	0	163	0	0
T28	0	190	0	0
T29	0	170	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	925	0	0
T7	41784	341	0	0
T8	0	151	0	0
T9	0	133	0	0
T28	0	160	0	0
T29	0	140	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	744359385	0	0
T1	238780	238772	0	0
T2	190094	190088	0	0
T3	539739	539732	0	0
T4	131537	131528	0	0
T5	123694	123615	0	0
T10	168986	168979	0	0
T14	413290	413232	0	0
T15	29381	29305	0	0
T16	59693	59578	0	0
T17	16633	16571	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T14

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T10,T17
1	0	1	Covered	T1,T2,T14
1	1	0	Covered	T14,T17,T11
1	1	1	Covered	T14,T10,T11

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T10,T11
0	1	Covered	T19,T24,T82
1	0	Covered	T11,T27,T47

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T10,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T27,T47

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T10,T11
1	0	Not Covered
1	1	Covered	T19,T24,T82

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T11,T19,T46

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T14,T11,T46

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T6
1	Covered	T1,T10,T40

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T14,T10
1	Covered	T2,T6,T45

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T10,T40

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T14,T40

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T14,T40

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T7,T8,T9
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T14
Phase1St	193	Covered	T1,T2,T14
Phase2St	210	Covered	T1,T2,T14
Phase3St	228	Covered	T1,T2,T14
TerminalSt	244	Covered	T1,T2,T14
TimeoutSt	154	Covered	T14,T10,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T7,T8,T9
IdleSt->Phase0St	147	Covered	T1,T2,T14
IdleSt->TimeoutSt	154	Covered	T14,T10,T11
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T11,T23,T24
Phase0St->Phase1St	193	Covered	T1,T2,T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T23,T96,T97
Phase1St->Phase2St	210	Covered	T1,T2,T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T53,T98,T99
Phase2St->Phase3St	228	Covered	T1,T2,T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T52,T100,T101
Phase3St->TerminalSt	244	Covered	T1,T2,T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T14,T11
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14,T10,T11
TimeoutSt->Phase0St	167	Covered	T11,T19,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T10,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T19,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T10,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T10,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T24,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T96,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T53,T98,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T52,T100,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T14,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744510807	143	0	0
CheckAccumTrig0_A	744510807	499	0	0
CheckAccumTrig1_A	744510807	15	0	0
CheckClr_A	744510807	208	0	0
CheckEn_A	744396728	335270656	0	0
CheckPhase0_A	744510807	574	0	0
CheckPhase1_A	744510807	571	0	0
CheckPhase2_A	744510807	567	0	0
CheckPhase3_A	744510807	558	0	0
CheckTimeout0_A	744510807	700	0	0
CheckTimeoutSt1_A	744510807	93896	0	0
CheckTimeoutSt2_A	744510807	605	0	0
CheckTimeoutStTrig_A	744510807	75	0	0
ErrorStAllEscAsserted_A	744510807	1041	0	0
ErrorStIsTerminal_A	744510807	861	0	0
u_state_regs_A	744510807	744359385	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	143	0	0
T7	41784	40	0	0
T8	0	25	0	0
T9	0	34	0	0
T28	0	26	0	0
T29	0	18	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	499	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T6	0	1	0	0
T10	168986	1	0	0
T11	0	2	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	3	0	0
T40	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	15	0	0
T11	688327	1	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T19	557456	0	0	0
T27	0	1	0	0
T41	43807	0	0	0
T42	471371	0	0	0
T43	330284	0	0	0
T44	371016	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T62	0	3	0	0
T63	0	1	0	0
T64	104658	0	0	0
T65	10266	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	208	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T14	413290	1	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	1	0	0
T23	0	3	0	0
T24	0	3	0	0
T25	0	1	0	0
T39	34069	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744396728	335270656	0	0
T1	238780	13070	0	0
T2	190094	189024	0	0
T3	539739	539732	0	0
T4	131537	988253	0	0
T5	123694	95190	0	0
T10	168986	12997	0	0
T14	413290	355618	0	0
T15	29381	29304	0	0
T16	59693	59576	0	0
T17	16633	13314	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	574	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T6	0	1	0	0
T10	168986	1	0	0
T11	0	2	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	4	0	0
T40	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	571	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T6	0	1	0	0
T10	168986	1	0	0
T11	0	2	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	4	0	0
T40	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	567	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T6	0	1	0	0
T10	168986	1	0	0
T11	0	2	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	4	0	0
T40	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	558	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T6	0	1	0	0
T10	168986	1	0	0
T11	0	2	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	4	0	0
T40	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	700	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	2	0	0
T11	0	3	0	0
T14	413290	15	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	1	0	0
T20	22810	0	0	0
T25	0	6	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T75	0	1	0	0
T80	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	93896	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	61	0	0
T11	0	106	0	0
T14	413290	1802	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	363	0	0
T20	22810	0	0	0
T25	0	681	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T42	0	46	0	0
T45	0	21	0	0
T46	0	338	0	0
T75	0	90	0	0
T80	0	376	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	605	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	2	0	0
T11	0	1	0	0
T14	413290	15	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T20	22810	0	0	0
T25	0	6	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T75	0	1	0	0
T80	0	3	0	0
T81	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	75	0	0
T19	557456	1	0	0
T24	0	1	0	0
T25	343113	0	0	0
T33	0	1	0	0
T45	11297	0	0	0
T46	623507	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T72	487804	0	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	136107	0	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T90	238784	0	0	0
T91	803564	0	0	0
T92	200050	0	0	0
T93	48624	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	1041	0	0
T7	41784	348	0	0
T8	0	163	0	0
T9	0	186	0	0
T28	0	185	0	0
T29	0	159	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	861	0	0
T7	41784	288	0	0
T8	0	133	0	0
T9	0	156	0	0
T28	0	155	0	0
T29	0	129	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	744359385	0	0
T1	238780	238772	0	0
T2	190094	190088	0	0
T3	539739	539732	0	0
T4	131537	131528	0	0
T5	123694	123615	0	0
T10	168986	168979	0	0
T14	413290	413232	0	0
T15	29381	29305	0	0
T16	59693	59578	0	0
T17	16633	16571	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T14

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T16,T17
1	0	1	Covered	T14,T10,T40
1	1	0	Covered	T16,T17,T11
1	1	1	Covered	T14,T17,T11

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T11
0	1	Covered	T14,T46,T25
1	0	Covered	T19,T77,T52

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T14,T17,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T77,T52

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T11
1	0	Not Covered
1	1	Covered	T14,T46,T25

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T10
1	Covered	T1,T14,T10

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T14,T42,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T14,T10
1	Covered	T2,T14,T10

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T14,T12,T41

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T14,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T14,T10,T40

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T14,T10,T42

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T7,T8,T9
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T14
Phase1St	193	Covered	T1,T2,T14
Phase2St	210	Covered	T1,T2,T14
Phase3St	228	Covered	T1,T2,T14
TerminalSt	244	Covered	T1,T2,T14
TimeoutSt	154	Covered	T14,T17,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T7,T8,T9
IdleSt->Phase0St	147	Covered	T1,T2,T14
IdleSt->TimeoutSt	154	Covered	T14,T17,T11
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T103,T104
Phase0St->Phase1St	193	Covered	T1,T2,T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T10,T105,T106
Phase1St->Phase2St	210	Covered	T1,T2,T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T19,T107,T98
Phase2St->Phase3St	228	Covered	T1,T2,T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T19,T74,T105
Phase3St->TerminalSt	244	Covered	T1,T2,T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14,T10,T11
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T14,T17,T11
TimeoutSt->Phase0St	167	Covered	T14,T19,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T19,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T14,T17,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T103,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T105,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T107,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T74,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T10,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744510807	199	0	0
CheckAccumTrig0_A	744510807	459	0	0
CheckAccumTrig1_A	744510807	22	0	0
CheckClr_A	744510807	186	0	0
CheckEn_A	744396728	390611465	0	0
CheckPhase0_A	744510807	531	0	0
CheckPhase1_A	744510807	517	0	0
CheckPhase2_A	744510807	512	0	0
CheckPhase3_A	744510807	504	0	0
CheckTimeout0_A	744510807	782	0	0
CheckTimeoutSt1_A	744510807	83636	0	0
CheckTimeoutSt2_A	744510807	702	0	0
CheckTimeoutStTrig_A	744510807	56	0	0
ErrorStAllEscAsserted_A	744510807	1049	0	0
ErrorStIsTerminal_A	744510807	869	0	0
u_state_regs_A	744510807	744359385	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	199	0	0
T7	41784	55	0	0
T8	0	26	0	0
T9	0	44	0	0
T28	0	34	0	0
T29	0	40	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	459	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	413290	6	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	22	0	0
T19	557456	3	0	0
T25	343113	0	0	0
T45	11297	0	0	0
T46	623507	0	0	0
T52	0	1	0	0
T59	0	1	0	0
T72	487804	0	0	0
T77	0	1	0	0
T79	136107	0	0	0
T90	238784	0	0	0
T91	803564	0	0	0
T92	200050	0	0	0
T93	48624	0	0	0
T100	0	1	0	0
T104	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	186	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	2	0	0
T11	0	1	0	0
T14	413290	3	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	5	0	0
T20	22810	0	0	0
T24	0	3	0	0
T27	0	2	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	1	0	0
T74	0	3	0	0
T77	0	6	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744396728	390611465	0	0
T1	238780	2007	0	0
T2	190094	594	0	0
T3	539739	539732	0	0
T4	131537	127783	0	0
T5	123694	31127	0	0
T10	168986	2073	0	0
T14	413290	553402	0	0
T15	29381	29304	0	0
T16	59693	54589	0	0
T17	16633	10216	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	531	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	413290	7	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	517	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	413290	7	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	512	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	413290	7	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	504	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	413290	7	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	782	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T11	0	2	0	0
T14	413290	7	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	1	0	0
T19	0	7	0	0
T20	22810	0	0	0
T25	0	1	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	83636	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T11	0	131	0	0
T14	413290	1418	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	91	0	0
T19	0	203	0	0
T20	22810	0	0	0
T25	0	44	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	618	0	0
T74	0	40	0	0
T75	0	114	0	0
T80	0	225	0	0
T81	0	80	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	702	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T11	0	1	0	0
T14	413290	6	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	1	0	0
T19	0	4	0	0
T20	22810	0	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	56	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	0	0	0
T14	413290	1	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T20	22810	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T33	0	2	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	1049	0	0
T7	41784	335	0	0
T8	0	183	0	0
T9	0	159	0	0
T28	0	176	0	0
T29	0	196	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	869	0	0
T7	41784	275	0	0
T8	0	153	0	0
T9	0	129	0	0
T28	0	146	0	0
T29	0	166	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	744359385	0	0
T1	238780	238772	0	0
T2	190094	190088	0	0
T3	539739	539732	0	0
T4	131537	131528	0	0
T5	123694	123615	0	0
T10	168986	168979	0	0
T14	413290	413232	0	0
T15	29381	29305	0	0
T16	59693	59578	0	0
T17	16633	16571	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T14

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T14

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T15,T17
1	0	1	Covered	T3,T14,T4
1	1	0	Covered	T14,T16,T10
1	1	1	Covered	T17,T19,T46

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T46
0	1	Covered	T46,T77,T47
1	0	Covered	T47,T50,T54

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T19,T46
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T50,T54

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T46
1	0	Covered	T21,T22
1	1	Covered	T46,T77,T47

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T4
1	Covered	T1,T14,T11

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T14,T41,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T14,T11
1	Covered	T2,T4,T10

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T14
1	Covered	T19,T91,T46

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T18,T41,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T14,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T4,T44

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T7,T8,T9
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T14
Phase1St	193	Covered	T1,T2,T14
Phase2St	210	Covered	T1,T2,T14
Phase3St	228	Covered	T1,T2,T14
TerminalSt	244	Covered	T1,T2,T14
TimeoutSt	154	Covered	T17,T19,T46

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T7,T8,T9
IdleSt->Phase0St	147	Covered	T1,T2,T14
IdleSt->TimeoutSt	154	Covered	T17,T19,T46
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T102,T109,T113
Phase0St->Phase1St	193	Covered	T1,T2,T14
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T114,T115,T116
Phase1St->Phase2St	210	Covered	T1,T2,T14
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T103,T115,T117
Phase2St->Phase3St	228	Covered	T1,T2,T14
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T27,T105,T118
Phase3St->TerminalSt	244	Covered	T1,T2,T14
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T14,T10,T11
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T17,T19,T46
TimeoutSt->Phase0St	167	Covered	T46,T77,T47

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T46
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T46,T77,T47
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T46
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T19,T46
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T102,T109,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T14
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T114,T115,T116
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T14
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T115,T117,T119
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T105,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T10,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744510807	200	0	0
CheckAccumTrig0_A	744510807	455	0	0
CheckAccumTrig1_A	744510807	20	0	0
CheckClr_A	744510807	192	0	0
CheckEn_A	744396728	360138639	0	0
CheckPhase0_A	744510807	538	0	0
CheckPhase1_A	744510807	532	0	0
CheckPhase2_A	744510807	527	0	0
CheckPhase3_A	744510807	519	0	0
CheckTimeout0_A	744510807	691	0	0
CheckTimeoutSt1_A	744510807	85875	0	0
CheckTimeoutSt2_A	744510807	594	0	0
CheckTimeoutStTrig_A	744510807	74	0	0
ErrorStAllEscAsserted_A	744510807	1071	0	0
ErrorStIsTerminal_A	744510807	891	0	0
u_state_regs_A	744510807	744359385	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	200	0	0
T7	41784	70	0	0
T8	0	31	0	0
T9	0	48	0	0
T28	0	27	0	0
T29	0	24	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	455	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	1	0	0
T5	123694	0	0	0
T10	168986	1	0	0
T11	0	1	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	20	0	0
T22	0	1	0	0
T50	590046	1	0	0
T51	113662	0	0	0
T52	429473	0	0	0
T54	0	1	0	0
T66	12903	0	0	0
T67	41085	0	0	0
T68	30437	0	0	0
T69	761973	0	0	0
T70	2752	0	0	0
T71	65220	0	0	0
T104	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	1196	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	192	0	0
T4	131537	0	0	0
T5	123694	0	0	0
T10	168986	1	0	0
T14	413290	1	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T19	0	1	0	0
T20	22810	0	0	0
T24	0	3	0	0
T25	0	1	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T46	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744396728	360138639	0	0
T1	238780	1992	0	0
T2	190094	590	0	0
T3	539739	538648	0	0
T4	131537	97163	0	0
T5	123694	118837	0	0
T10	168986	168571	0	0
T14	413290	375784	0	0
T15	29381	27619	0	0
T16	59693	59576	0	0
T17	16633	4044	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	538	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	1	0	0
T5	123694	0	0	0
T10	168986	1	0	0
T11	0	1	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	532	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	1	0	0
T5	123694	0	0	0
T10	168986	1	0	0
T11	0	1	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	527	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	1	0	0
T5	123694	0	0	0
T10	168986	1	0	0
T11	0	1	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	519	0	0
T1	238780	1	0	0
T2	190094	1	0	0
T3	539739	0	0	0
T4	131537	1	0	0
T5	123694	0	0	0
T10	168986	1	0	0
T11	0	1	0	0
T14	413290	2	0	0
T15	29381	0	0	0
T16	59693	0	0	0
T17	16633	0	0	0
T18	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	691	0	0
T6	149575	0	0	0
T11	688327	0	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T17	16633	2	0	0
T18	90635	0	0	0
T19	0	2	0	0
T20	22810	0	0	0
T24	0	2	0	0
T25	0	4	0	0
T27	0	22	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T41	43807	0	0	0
T46	0	4	0	0
T75	0	1	0	0
T77	0	7	0	0
T79	0	1	0	0
T82	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	85875	0	0
T6	149575	0	0	0
T11	688327	0	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T17	16633	138	0	0
T18	90635	0	0	0
T19	0	138	0	0
T20	22810	0	0	0
T24	0	252	0	0
T25	0	452	0	0
T27	0	3125	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T41	43807	0	0	0
T46	0	332	0	0
T75	0	114	0	0
T77	0	1074	0	0
T79	0	132	0	0
T82	0	502	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	594	0	0
T6	149575	0	0	0
T11	688327	0	0	0
T12	915977	0	0	0
T13	124575	0	0	0
T17	16633	2	0	0
T18	90635	0	0	0
T19	0	2	0	0
T20	22810	0	0	0
T24	0	2	0	0
T25	0	4	0	0
T27	0	22	0	0
T39	34069	0	0	0
T40	158007	0	0	0
T41	43807	0	0	0
T46	0	2	0	0
T75	0	1	0	0
T77	0	6	0	0
T79	0	1	0	0
T82	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	74	0	0
T25	343113	0	0	0
T46	623507	2	0	0
T47	0	1	0	0
T54	0	1	0	0
T72	487804	0	0	0
T73	777116	0	0	0
T77	0	1	0	0
T79	136107	0	0	0
T80	46754	0	0	0
T84	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T93	48624	0	0	0
T94	125773	0	0	0
T100	0	6	0	0
T120	0	1	0	0
T127	0	1	0	0
T128	21342	0	0	0
T129	854504	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	1071	0	0
T7	41784	376	0	0
T8	0	172	0	0
T9	0	171	0	0
T28	0	154	0	0
T29	0	198	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	891	0	0
T7	41784	316	0	0
T8	0	142	0	0
T9	0	141	0	0
T28	0	124	0	0
T29	0	168	0	0
T30	14748	0	0	0
T31	5429	0	0	0
T32	43810	0	0	0
T33	44148	0	0	0
T34	147884	0	0	0
T35	67637	0	0	0
T36	19331	0	0	0
T37	3973	0	0	0
T38	3514	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744510807	744359385	0	0
T1	238780	238772	0	0
T2	190094	190088	0	0
T3	539739	539732	0	0
T4	131537	131528	0	0
T5	123694	123615	0	0
T10	168986	168979	0	0
T14	413290	413232	0	0
T15	29381	29305	0	0
T16	59693	59578	0	0
T17	16633	16571	0	0