Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T111,T36
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14567	0	0
DisabledNoTrigBkwd_A	2147483647	844322	0	0
DisabledNoTrigFwd_A	2147483647	1424454425	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14567	0	0
T16	38243	0	0	0
T36	0	380	0	0
T43	1444	646	0	0
T51	4794	0	0	0
T57	705990	0	0	0
T85	457757	0	0	0
T92	535541	0	0	0
T111	0	834	0	0
T113	574554	0	0	0
T199	0	549	0	0
T200	3341	845	0	0
T201	0	563	0	0
T202	0	991	0	0
T203	3085	635	0	0
T204	0	603	0	0
T205	0	396	0	0
T206	0	302	0	0
T207	0	670	0	0
T208	0	310	0	0
T209	0	330	0	0
T210	0	1644	0	0
T211	0	600	0	0
T212	0	511	0	0
T213	0	1606	0	0
T214	0	633	0	0
T215	0	1519	0	0
T216	17967	0	0	0
T217	51491	0	0	0
T218	26252	0	0	0
T219	275322	0	0	0
T220	18615	0	0	0
T221	50845	0	0	0
T222	57749	0	0	0
T223	17588	0	0	0
T224	14702	0	0	0
T225	105395	0	0	0
T226	847961	0	0	0
T227	412288	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	844322	0	0
T1	43473	442	0	0
T2	2144068	5796	0	0
T3	2364456	352	0	0
T4	3854224	5	0	0
T5	445488	1864	0	0
T6	31680	15	0	0
T7	3652652	4716	0	0
T8	0	2049	0	0
T9	0	2977	0	0
T10	0	3147	0	0
T11	605328	8546	0	0
T18	0	9279	0	0
T19	0	100	0	0
T21	1942612	443	0	0
T22	282928	0	0	0
T23	48152	6	0	0
T26	0	36	0	0
T31	0	8	0	0
T43	0	36	0	0
T44	0	264	0	0
T69	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1424454425	0	0
T1	57964	24684	0	0
T2	2144068	2298725	0	0
T3	2364456	1199715	0	0
T4	3854224	2681224	0	0
T5	445488	336363	0	0
T6	31680	24334	0	0
T7	3652652	922945	0	0
T21	1942612	512745	0	0
T22	282928	209736	0	0
T23	48152	34754	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T202,T215
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	698857116	3355	0	0
DisabledNoTrigBkwd_A	698857116	244262	0	0
DisabledNoTrigFwd_A	698857116	308748951	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	3355	0	0
T16	38243	0	0	0
T51	4794	0	0	0
T85	457757	0	0	0
T92	535541	0	0	0
T200	3341	845	0	0
T202	0	991	0	0
T215	0	1519	0	0
T216	17967	0	0	0
T217	51491	0	0	0
T218	26252	0	0	0
T219	275322	0	0	0
T220	18615	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	244262	0	0
T1	14491	428	0	0
T2	536017	5742	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	15	0	0
T7	913163	1522	0	0
T9	0	1460	0	0
T11	0	1070	0	0
T18	0	177	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	2	0	0
T26	0	36	0	0
T31	0	8	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	308748951	0	0
T1	14491	1948	0	0
T2	536017	694611	0	0
T3	591114	575543	0	0
T4	963556	791230	0	0
T5	111372	111227	0	0
T6	7920	844	0	0
T7	913163	6643	0	0
T21	485653	485587	0	0
T22	70732	65292	0	0
T23	12038	9177	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T203,T204,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	698857116	3108	0	0
DisabledNoTrigBkwd_A	698857116	185795	0	0
DisabledNoTrigFwd_A	698857116	388182445	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	3108	0	0
T57	705990	0	0	0
T113	574554	0	0	0
T203	3085	635	0	0
T204	0	603	0	0
T205	0	396	0	0
T209	0	330	0	0
T212	0	511	0	0
T214	0	633	0	0
T221	50845	0	0	0
T222	57749	0	0	0
T223	17588	0	0	0
T224	14702	0	0	0
T225	105395	0	0	0
T226	847961	0	0	0
T227	412288	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	185795	0	0
T1	14491	11	0	0
T2	536017	1	0	0
T3	591114	99	0	0
T4	963556	0	0	0
T5	111372	18	0	0
T6	7920	0	0	0
T7	913163	1205	0	0
T8	0	2049	0	0
T10	0	1746	0	0
T11	0	1498	0	0
T18	0	3	0	0
T21	485653	225	0	0
T22	70732	0	0	0
T23	12038	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	388182445	0	0
T1	14491	7280	0	0
T2	536017	534301	0	0
T3	591114	41874	0	0
T4	963556	899668	0	0
T5	111372	109901	0	0
T6	7920	7830	0	0
T7	913163	1600	0	0
T21	485653	2718	0	0
T22	70732	70665	0	0
T23	12038	9188	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T111,T199
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	698857116	5480	0	0
DisabledNoTrigBkwd_A	698857116	203675	0	0
DisabledNoTrigFwd_A	698857116	346380980	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	5480	0	0
T12	975149	0	0	0
T13	275499	0	0	0
T28	684706	0	0	0
T43	1444	646	0	0
T44	26872	0	0	0
T64	194060	0	0	0
T65	770408	0	0	0
T69	403434	0	0	0
T111	0	834	0	0
T199	0	549	0	0
T201	0	563	0	0
T206	0	302	0	0
T207	0	670	0	0
T208	0	310	0	0
T213	0	1606	0	0
T228	137985	0	0	0
T229	127478	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	203675	0	0
T1	14491	3	0	0
T2	536017	0	0	0
T3	591114	253	0	0
T4	963556	5	0	0
T5	111372	1846	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	1894	0	0
T18	0	2	0	0
T19	0	100	0	0
T21	485653	77	0	0
T22	70732	0	0	0
T23	12038	2	0	0
T43	0	36	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	346380980	0	0
T1	14491	5619	0	0
T2	536017	535225	0	0
T3	591114	3104	0	0
T4	963556	299488	0	0
T5	111372	3872	0	0
T6	7920	7830	0	0
T7	913163	913094	0	0
T21	485653	12044	0	0
T22	70732	3114	0	0
T23	12038	8198	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T210,T211
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T21,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	698857116	2624	0	0
DisabledNoTrigBkwd_A	698857116	210590	0	0
DisabledNoTrigFwd_A	698857116	381142049	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	2624	0	0
T36	3673	380	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0
T48	324183	0	0	0
T210	0	1644	0	0
T211	0	600	0	0
T230	16661	0	0	0
T231	61758	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	210590	0	0
T2	536017	53	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	1989	0	0
T9	0	1517	0	0
T10	0	1401	0	0
T11	605328	4084	0	0
T18	0	9097	0	0
T21	485653	141	0	0
T22	70732	0	0	0
T23	12038	2	0	0
T44	0	264	0	0
T69	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	381142049	0	0
T1	14491	9837	0	0
T2	536017	534588	0	0
T3	591114	579194	0	0
T4	963556	690838	0	0
T5	111372	111363	0	0
T6	7920	7830	0	0
T7	913163	1608	0	0
T21	485653	12396	0	0
T22	70732	70665	0	0
T23	12038	8191	0	0