Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T25
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T6,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T22
0	1	Covered	T1,T11,T18
1	0	Covered	T1,T23,T26

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T6,T22
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T23,T26

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T22
1	0	Covered	T27
1	1	Covered	T1,T11,T18

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T21,T23

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T15,T16,T17
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T6,T22

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T15,T16,T17
IdleSt->Phase0St	147	Covered	T1,T2,T3
IdleSt->TimeoutSt	154	Covered	T1,T6,T22
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T5,T28,T29
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T11,T18,T10
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T18,T10,T30
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T5,T11,T31
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T2,T5
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T6,T22
TimeoutSt->Phase0St	167	Covered	T1,T23,T11

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T11
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T28,T29
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T11,T18,T10
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T10,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T11,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1003	0	0
CheckAccumTrig0_A	2147483647	2344	0	0
CheckAccumTrig1_A	2147483647	110	0	0
CheckClr_A	2147483647	1159	0	0
CheckEn_A	2147483647	1115546756	0	0
CheckPhase0_A	2147483647	2681	0	0
CheckPhase1_A	2147483647	2628	0	0
CheckPhase2_A	2147483647	2575	0	0
CheckPhase3_A	2147483647	2522	0	0
CheckTimeout0_A	2147483647	4041	0	0
CheckTimeoutSt1_A	2147483647	426774	0	0
CheckTimeoutSt2_A	2147483647	3652	0	0
CheckTimeoutStTrig_A	2147483647	273	0	0
ErrorStAllEscAsserted_A	2147483647	5121	0	0
ErrorStIsTerminal_A	2147483647	4281	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1003	0	0
T15	77440	147	0	0
T16	0	293	0	0
T17	0	276	0	0
T32	0	152	0	0
T33	0	135	0	0
T34	46328	0	0	0
T35	653340	0	0	0
T36	14692	0	0	0
T37	230628	0	0	0
T38	181536	0	0	0
T39	495592	0	0	0
T40	731652	0	0	0
T41	642920	0	0	0
T42	2778064	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2344	0	0
T1	14491	2	0	0
T2	1608051	3	0	0
T3	2364456	2	0	0
T4	3854224	1	0	0
T5	445488	6	0	0
T6	31680	1	0	0
T7	3652652	4	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	7	0	0
T11	1815984	19	0	0
T12	0	1	0	0
T13	0	1	0	0
T18	0	9	0	0
T19	0	1	0	0
T21	1942612	2	0	0
T22	282928	0	0	0
T23	48152	1	0	0
T24	39143	0	0	0
T26	0	3	0	0
T31	0	7	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T10	354320	0	0	0
T11	605328	0	0	0
T19	273128	0	0	0
T20	15975	0	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	24076	1	0	0
T25	0	1	0	0
T26	95206	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	64210	0	0	0
T43	1444	0	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T60	71636	0	0	0
T61	11827	0	0	0
T62	12411	0	0	0
T63	64978	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1159	0	0
T1	14491	1	0	0
T2	1072034	2	0	0
T3	1182228	0	0	0
T4	1927112	0	0	0
T5	222744	4	0	0
T6	15840	0	0	0
T7	1826326	2	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T10	354320	6	0	0
T11	605328	8	0	0
T18	343210	9	0	0
T19	136564	0	0	0
T20	15975	0	0	0
T21	971306	0	0	0
T22	141464	0	0	0
T23	24076	0	0	0
T25	0	2	0	0
T26	47603	3	0	0
T28	0	6	0	0
T29	0	4	0	0
T31	32105	7	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	6	0	0
T60	35818	0	0	0
T61	11827	1	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	0	5	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1115546756	0	0
T1	57964	16260	0	0
T2	2144068	2288254	0	0
T3	2364456	1199713	0	0
T4	3854224	2474649	0	0
T5	445488	226263	0	0
T6	31680	24331	0	0
T7	3652652	920916	0	0
T21	1942612	512744	0	0
T22	282928	209733	0	0
T23	48152	28718	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T1	57964	5	0	0
T2	2144068	4	0	0
T3	2364456	2	0	0
T4	3854224	1	0	0
T5	445488	4	0	0
T6	31680	1	0	0
T7	3652652	6	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	8	0	0
T11	0	25	0	0
T18	0	19	0	0
T19	0	1	0	0
T21	1942612	3	0	0
T22	282928	0	0	0
T23	48152	3	0	0
T26	0	4	0	0
T31	0	7	0	0
T43	0	1	0	0
T44	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2628	0	0
T1	57964	5	0	0
T2	2144068	4	0	0
T3	2364456	2	0	0
T4	3854224	1	0	0
T5	445488	4	0	0
T6	31680	1	0	0
T7	3652652	6	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	7	0	0
T11	0	24	0	0
T18	0	18	0	0
T19	0	1	0	0
T21	1942612	3	0	0
T22	282928	0	0	0
T23	48152	3	0	0
T26	0	4	0	0
T31	0	7	0	0
T43	0	1	0	0
T44	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2575	0	0
T1	57964	5	0	0
T2	2144068	4	0	0
T3	2364456	2	0	0
T4	3854224	1	0	0
T5	445488	4	0	0
T6	31680	1	0	0
T7	3652652	6	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	0	6	0	0
T11	0	24	0	0
T18	0	16	0	0
T19	0	1	0	0
T21	1942612	3	0	0
T22	282928	0	0	0
T23	48152	3	0	0
T26	0	4	0	0
T31	0	7	0	0
T43	0	1	0	0
T44	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2522	0	0
T1	57964	5	0	0
T2	2144068	4	0	0
T3	2364456	2	0	0
T4	3854224	1	0	0
T5	445488	3	0	0
T6	31680	1	0	0
T7	3652652	6	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	23	0	0
T18	0	16	0	0
T19	0	1	0	0
T21	1942612	3	0	0
T22	282928	0	0	0
T23	48152	3	0	0
T26	0	4	0	0
T31	0	6	0	0
T43	0	1	0	0
T44	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4041	0	0
T1	43473	4	0	0
T2	1608051	0	0	0
T3	1773342	0	0	0
T4	2890668	0	0	0
T5	334116	0	0	0
T6	31680	1	0	0
T7	3652652	4	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	383	0	0
T18	343210	23	0	0
T21	1942612	0	0	0
T22	282928	6	0	0
T23	48152	1	0	0
T24	39143	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T30	0	1	0	0
T44	0	2	0	0
T45	0	19	0	0
T62	0	13	0	0
T65	0	5	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	10	0	0
T72	0	1	0	0
T73	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	426774	0	0
T1	43473	570	0	0
T2	1608051	0	0	0
T3	1773342	0	0	0
T4	2890668	0	0	0
T5	334116	0	0	0
T6	31680	128	0	0
T7	3652652	141	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	26657	0	0
T18	343210	5599	0	0
T21	1942612	0	0	0
T22	282928	1034	0	0
T23	48152	1	0	0
T24	39143	0	0	0
T25	0	314	0	0
T26	0	43	0	0
T28	0	27	0	0
T29	0	265	0	0
T30	0	1	0	0
T44	0	999	0	0
T45	0	1451	0	0
T62	0	2014	0	0
T65	0	232	0	0
T69	0	41	0	0
T70	0	240	0	0
T71	0	1167	0	0
T72	0	61	0	0
T73	0	453	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3652	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	15840	1	0	0
T7	2739489	4	0	0
T8	325440	0	0	0
T9	497202	0	0	0
T10	354320	0	0	0
T11	1815984	381	0	0
T18	1029630	15	0	0
T19	136564	0	0	0
T21	971306	0	0	0
T22	212196	6	0	0
T23	36114	0	0	0
T24	117429	0	0	0
T25	0	1	0	0
T26	95206	0	0	0
T31	32105	0	0	0
T44	0	1	0	0
T45	0	94	0	0
T46	0	1	0	0
T60	71636	0	0	0
T62	0	13	0	0
T65	0	5	0	0
T70	0	2	0	0
T71	0	11	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	273	0	0
T1	14491	1	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T10	354320	0	0	0
T11	0	2	0	0
T14	139266	0	0	0
T18	343210	7	0	0
T19	136564	0	0	0
T20	15975	0	0	0
T26	47603	0	0	0
T31	32105	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	403675	3	0	0
T46	0	3	0	0
T52	0	1	0	0
T60	35818	0	0	0
T61	11827	0	0	0
T68	307664	0	0	0
T71	74428	3	0	0
T72	5778	0	0	0
T73	78657	2	0	0
T74	57303	1	0	0
T75	70745	0	0	0
T77	0	4	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	354183	0	0	0
T87	632854	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5121	0	0
T15	77440	722	0	0
T16	0	1484	0	0
T17	0	1447	0	0
T32	0	720	0	0
T33	0	748	0	0
T34	46328	0	0	0
T35	653340	0	0	0
T36	14692	0	0	0
T37	230628	0	0	0
T38	181536	0	0	0
T39	495592	0	0	0
T40	731652	0	0	0
T41	642920	0	0	0
T42	2778064	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4281	0	0
T15	77440	602	0	0
T16	0	1244	0	0
T17	0	1207	0	0
T32	0	600	0	0
T33	0	628	0	0
T34	46328	0	0	0
T35	653340	0	0	0
T36	14692	0	0	0
T37	230628	0	0	0
T38	181536	0	0	0
T39	495592	0	0	0
T40	731652	0	0	0
T41	642920	0	0	0
T42	2778064	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	57964	57656	0	0
T2	2144068	2143956	0	0
T3	2364456	2364112	0	0
T4	3854224	3853832	0	0
T5	445488	445452	0	0
T6	31680	31320	0	0
T7	3652652	3652376	0	0
T21	1942612	1942348	0	0
T22	282928	282660	0	0
T23	48152	47812	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T22,T23
1	1	1	Covered	T6,T22,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T22,T7
0	1	Covered	T18,T71,T74
1	0	Covered	T26,T25,T29

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T22,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T25,T29

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T22,T7
1	0	Not Covered
1	1	Covered	T18,T71,T74

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T23
1	Covered	T1,T2,T7

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T6,T23,T11

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T11,T18

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T18,T9,T63

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T6,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T15,T16,T17
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T6
Phase1St	193	Covered	T1,T2,T6
Phase2St	210	Covered	T1,T2,T6
Phase3St	228	Covered	T1,T2,T6
TerminalSt	244	Covered	T1,T2,T6
TimeoutSt	154	Covered	T6,T22,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T15,T16,T17
IdleSt->Phase0St	147	Covered	T1,T2,T6
IdleSt->TimeoutSt	154	Covered	T6,T22,T7
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T28,T45,T88
Phase0St->Phase1St	193	Covered	T1,T2,T6
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T18,T25,T41
Phase1St->Phase2St	210	Covered	T1,T2,T6
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T18,T30,T45
Phase2St->Phase3St	228	Covered	T1,T2,T6
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T11,T31,T28
Phase3St->TerminalSt	244	Covered	T1,T2,T6
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T2,T7
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T6,T22,T7
TimeoutSt->Phase0St	167	Covered	T18,T26,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T22,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T26,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T22,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T22,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T45,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T25,T41
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T30,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T11,T31,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	698857116	296	0	0
CheckAccumTrig0_A	698857116	824	0	0
CheckAccumTrig1_A	698857116	38	0	0
CheckClr_A	698857116	421	0	0
CheckEn_A	698714488	236278230	0	0
CheckPhase0_A	698857116	927	0	0
CheckPhase1_A	698857116	915	0	0
CheckPhase2_A	698857116	897	0	0
CheckPhase3_A	698857116	875	0	0
CheckTimeout0_A	698857116	1072	0	0
CheckTimeoutSt1_A	698857116	120270	0	0
CheckTimeoutSt2_A	698857116	952	0	0
CheckTimeoutStTrig_A	698857116	81	0	0
ErrorStAllEscAsserted_A	698857116	1280	0	0
ErrorStIsTerminal_A	698857116	1070	0	0
u_state_regs_A	698857116	698701957	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	296	0	0
T15	19360	51	0	0
T16	0	84	0	0
T17	0	88	0	0
T32	0	39	0	0
T33	0	34	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	824	0	0
T1	14491	2	0	0
T2	536017	2	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	1	0	0
T7	913163	2	0	0
T9	0	1	0	0
T11	0	10	0	0
T18	0	6	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T26	0	3	0	0
T31	0	7	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	38	0	0
T10	354320	0	0	0
T19	136564	0	0	0
T20	15975	0	0	0
T25	0	1	0	0
T26	47603	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	32105	0	0	0
T43	1444	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T60	35818	0	0	0
T61	11827	0	0	0
T62	12411	0	0	0
T63	64978	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	421	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	1	0	0
T11	0	6	0	0
T18	0	6	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T25	0	2	0	0
T26	0	3	0	0
T28	0	6	0	0
T31	0	7	0	0
T61	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698714488	236278230	0	0
T1	14491	1948	0	0
T2	536017	684140	0	0
T3	591114	575542	0	0
T4	963556	791229	0	0
T5	111372	111227	0	0
T6	7920	844	0	0
T7	913163	6643	0	0
T21	485653	485586	0	0
T22	70732	65291	0	0
T23	12038	9177	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	927	0	0
T1	14491	2	0	0
T2	536017	2	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	1	0	0
T7	913163	2	0	0
T9	0	1	0	0
T11	0	10	0	0
T18	0	10	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T26	0	4	0	0
T31	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	915	0	0
T1	14491	2	0	0
T2	536017	2	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	1	0	0
T7	913163	2	0	0
T9	0	1	0	0
T11	0	10	0	0
T18	0	9	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T26	0	4	0	0
T31	0	7	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	897	0	0
T1	14491	2	0	0
T2	536017	2	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	1	0	0
T7	913163	2	0	0
T9	0	1	0	0
T11	0	10	0	0
T18	0	7	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T26	0	4	0	0
T31	0	7	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	875	0	0
T1	14491	2	0	0
T2	536017	2	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	1	0	0
T7	913163	2	0	0
T9	0	1	0	0
T11	0	9	0	0
T18	0	7	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T26	0	4	0	0
T31	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1072	0	0
T6	7920	1	0	0
T7	913163	3	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	10	0	0
T18	343210	4	0	0
T21	485653	0	0	0
T22	70732	1	0	0
T23	12038	0	0	0
T24	39143	0	0	0
T25	0	2	0	0
T26	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T62	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	120270	0	0
T6	7920	128	0	0
T7	913163	114	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	1043	0	0
T18	343210	876	0	0
T21	485653	0	0	0
T22	70732	160	0	0
T23	12038	0	0	0
T24	39143	0	0	0
T25	0	314	0	0
T26	0	43	0	0
T29	0	82	0	0
T30	0	1	0	0
T62	0	47	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	952	0	0
T6	7920	1	0	0
T7	913163	3	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	10	0	0
T18	343210	0	0	0
T21	485653	0	0	0
T22	70732	1	0	0
T23	12038	0	0	0
T24	39143	0	0	0
T25	0	1	0	0
T62	0	1	0	0
T71	0	2	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	81	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T10	354320	0	0	0
T18	343210	4	0	0
T19	136564	0	0	0
T20	15975	0	0	0
T26	47603	0	0	0
T31	32105	0	0	0
T46	0	1	0	0
T60	35818	0	0	0
T61	11827	0	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T77	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1280	0	0
T15	19360	181	0	0
T16	0	348	0	0
T17	0	380	0	0
T32	0	183	0	0
T33	0	188	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1070	0	0
T15	19360	151	0	0
T16	0	288	0	0
T17	0	320	0	0
T32	0	153	0	0
T33	0	158	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	698701957	0	0
T1	14491	14414	0	0
T2	536017	535989	0	0
T3	591114	591028	0	0
T4	963556	963458	0	0
T5	111372	111363	0	0
T6	7920	7830	0	0
T7	913163	913094	0	0
T21	485653	485587	0	0
T22	70732	70665	0	0
T23	12038	11953	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T22
1	0	1	Covered	T3,T21,T11
1	1	0	Covered	T7,T11,T18
1	1	1	Covered	T1,T22,T23

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T23
0	1	Covered	T1,T11,T18
1	0	Covered	T23,T45,T47

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T22,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T45,T47

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T22,T23
1	0	Not Covered
1	1	Covered	T1,T11,T18

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T18,T43,T13

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T21
1	Covered	T4,T5,T11

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T23,T18,T12

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T1,T3,T21

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T4,T5,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T3,T21,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T15,T16,T17
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T1,T22,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T15,T16,T17
IdleSt->Phase0St	147	Covered	T3,T4,T5
IdleSt->TimeoutSt	154	Covered	T1,T22,T23
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T29,T89,T90
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T91,T92,T93
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T49,T94,T59
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T47,T91,T92
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T11,T18,T65
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T22,T11,T18
TimeoutSt->Phase0St	167	Covered	T1,T23,T11

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T11
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T11,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T89,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T91,T92,T93
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T49,T94,T59
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T47,T91,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T65,T66
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	698857116	192	0	0
CheckAccumTrig0_A	698857116	537	0	0
CheckAccumTrig1_A	698857116	26	0	0
CheckClr_A	698857116	260	0	0
CheckEn_A	698714488	281269341	0	0
CheckPhase0_A	698857116	616	0	0
CheckPhase1_A	698857116	603	0	0
CheckPhase2_A	698857116	592	0	0
CheckPhase3_A	698857116	579	0	0
CheckTimeout0_A	698857116	1002	0	0
CheckTimeoutSt1_A	698857116	104265	0	0
CheckTimeoutSt2_A	698857116	915	0	0
CheckTimeoutStTrig_A	698857116	61	0	0
ErrorStAllEscAsserted_A	698857116	1276	0	0
ErrorStIsTerminal_A	698857116	1066	0	0
u_state_regs_A	698857116	698701957	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	192	0	0
T15	19360	13	0	0
T16	0	55	0	0
T17	0	56	0	0
T32	0	33	0	0
T33	0	35	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	537	0	0
T3	591114	1	0	0
T4	963556	1	0	0
T5	111372	1	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	605328	4	0	0
T12	0	1	0	0
T13	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T24	39143	0	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	26	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	0	0	0
T18	343210	0	0	0
T19	136564	0	0	0
T23	12038	1	0	0
T24	39143	0	0	0
T26	47603	0	0	0
T31	32105	0	0	0
T45	0	2	0	0
T47	0	3	0	0
T49	0	1	0	0
T60	35818	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	260	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T10	354320	0	0	0
T18	343210	3	0	0
T19	136564	0	0	0
T20	15975	0	0	0
T26	47603	0	0	0
T29	0	2	0	0
T31	32105	0	0	0
T41	0	5	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	6	0	0
T49	0	2	0	0
T60	35818	0	0	0
T61	11827	0	0	0
T65	0	2	0	0
T66	0	4	0	0
T88	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698714488	281269341	0	0
T1	14491	590	0	0
T2	536017	535225	0	0
T3	591114	3104	0	0
T4	963556	92916	0	0
T5	111372	1946	0	0
T6	7920	7829	0	0
T7	913163	913093	0	0
T21	485653	12044	0	0
T22	70732	3114	0	0
T23	12038	2163	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	616	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	1	0	0
T4	963556	1	0	0
T5	111372	1	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	6	0	0
T18	0	4	0	0
T19	0	1	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	603	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	1	0	0
T4	963556	1	0	0
T5	111372	1	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	6	0	0
T18	0	4	0	0
T19	0	1	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	592	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	1	0	0
T4	963556	1	0	0
T5	111372	1	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	6	0	0
T18	0	4	0	0
T19	0	1	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	579	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	1	0	0
T4	963556	1	0	0
T5	111372	1	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	6	0	0
T18	0	4	0	0
T19	0	1	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T43	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1002	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	43	0	0
T18	0	7	0	0
T21	485653	0	0	0
T22	70732	5	0	0
T23	12038	1	0	0
T44	0	1	0	0
T62	0	1	0	0
T65	0	2	0	0
T70	0	1	0	0
T71	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	104265	0	0
T1	14491	545	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	3075	0	0
T18	0	2091	0	0
T21	485653	0	0	0
T22	70732	874	0	0
T23	12038	1	0	0
T44	0	552	0	0
T62	0	47	0	0
T65	0	115	0	0
T70	0	120	0	0
T71	0	1013	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	915	0	0
T7	913163	0	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T11	605328	41	0	0
T18	343210	4	0	0
T22	70732	5	0	0
T23	12038	0	0	0
T24	39143	0	0	0
T26	47603	0	0	0
T45	0	79	0	0
T46	0	1	0	0
T60	35818	0	0	0
T62	0	1	0	0
T65	0	2	0	0
T70	0	1	0	0
T71	0	8	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	61	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	2	0	0
T18	0	3	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T79	0	1	0	0
T88	0	1	0	0
T99	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1276	0	0
T15	19360	184	0	0
T16	0	371	0	0
T17	0	357	0	0
T32	0	165	0	0
T33	0	199	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1066	0	0
T15	19360	154	0	0
T16	0	311	0	0
T17	0	297	0	0
T32	0	135	0	0
T33	0	169	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	698701957	0	0
T1	14491	14414	0	0
T2	536017	535989	0	0
T3	591114	591028	0	0
T4	963556	963458	0	0
T5	111372	111363	0	0
T6	7920	7830	0	0
T7	913163	913094	0	0
T21	485653	485587	0	0
T22	70732	70665	0	0
T23	12038	11953	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T21,T7

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T23
1	0	1	Covered	T3,T4,T21
1	1	0	Covered	T1,T5,T22
1	1	1	Covered	T1,T7,T11

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T18,T73
1	0	Covered	T29,T88,T100

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T7,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T88,T100

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Not Covered
1	1	Covered	T1,T18,T73

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T18,T9,T44

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T21,T7
1	Covered	T1,T11,T18

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T21
1	Covered	T7,T11,T45

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T11
1	Covered	T2,T21,T7

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T2,T7,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T2,T7,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T15,T16,T17
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T21
Phase1St	193	Covered	T1,T2,T21
Phase2St	210	Covered	T1,T2,T21
Phase3St	228	Covered	T1,T2,T21
TerminalSt	244	Covered	T1,T2,T21
TimeoutSt	154	Covered	T1,T7,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T15,T16,T17
IdleSt->Phase0St	147	Covered	T2,T21,T7
IdleSt->TimeoutSt	154	Covered	T1,T7,T11
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T45,T39,T101
Phase0St->Phase1St	193	Covered	T1,T2,T21
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T45,T73,T39
Phase1St->Phase2St	210	Covered	T1,T2,T21
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T80,T82,T88
Phase2St->Phase3St	228	Covered	T1,T2,T21
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T9,T102,T103
Phase3St->TerminalSt	244	Covered	T1,T2,T21
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T2,T7
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T7,T11
TimeoutSt->Phase0St	167	Covered	T1,T18,T29

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T29
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T7,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T45,T39,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T45,T73,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T80,T82,T88
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T9,T102,T103
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T7,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	698857116	255	0	0
CheckAccumTrig0_A	698857116	509	0	0
CheckAccumTrig1_A	698857116	20	0	0
CheckClr_A	698857116	247	0	0
CheckEn_A	698714488	302086692	0	0
CheckPhase0_A	698857116	581	0	0
CheckPhase1_A	698857116	570	0	0
CheckPhase2_A	698857116	555	0	0
CheckPhase3_A	698857116	549	0	0
CheckTimeout0_A	698857116	1044	0	0
CheckTimeoutSt1_A	698857116	98511	0	0
CheckTimeoutSt2_A	698857116	955	0	0
CheckTimeoutStTrig_A	698857116	68	0	0
ErrorStAllEscAsserted_A	698857116	1218	0	0
ErrorStIsTerminal_A	698857116	1008	0	0
u_state_regs_A	698857116	698701957	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	255	0	0
T15	19360	50	0	0
T16	0	59	0	0
T17	0	64	0	0
T32	0	46	0	0
T33	0	36	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	509	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	605328	4	0	0
T18	0	2	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T44	0	2	0	0
T69	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	20	0	0
T14	139266	0	0	0
T29	11426	1	0	0
T30	18110	0	0	0
T45	403675	0	0	0
T68	307664	0	0	0
T71	74428	0	0	0
T74	57303	0	0	0
T75	70745	0	0	0
T86	354183	0	0	0
T88	0	2	0	0
T100	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	3206	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	247	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	1	0	0
T9	0	1	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T44	0	1	0	0
T45	0	9	0	0
T46	0	4	0	0
T67	0	1	0	0
T73	0	2	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698714488	302086692	0	0
T1	14491	9836	0	0
T2	536017	534588	0	0
T3	591114	579193	0	0
T4	963556	690837	0	0
T5	111372	111363	0	0
T6	7920	7829	0	0
T7	913163	594	0	0
T21	485653	12396	0	0
T22	70732	70664	0	0
T23	12038	8190	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	581	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	4	0	0
T18	0	3	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T44	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	570	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	4	0	0
T18	0	3	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T44	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	555	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	4	0	0
T18	0	3	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T44	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	549	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	0	4	0	0
T18	0	3	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	1	0	0
T44	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1044	0	0
T1	14491	2	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	1	0	0
T11	0	187	0	0
T18	0	6	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T44	0	1	0	0
T62	0	6	0	0
T65	0	3	0	0
T69	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	98511	0	0
T1	14491	23	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	27	0	0
T11	0	12868	0	0
T18	0	1169	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T28	0	27	0	0
T29	0	182	0	0
T44	0	447	0	0
T62	0	1074	0	0
T65	0	117	0	0
T69	0	41	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	955	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	1	0	0
T11	0	187	0	0
T18	0	5	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T28	0	1	0	0
T29	0	1	0	0
T44	0	1	0	0
T62	0	6	0	0
T65	0	3	0	0
T69	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	68	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T18	0	1	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T46	0	1	0	0
T52	0	2	0	0
T73	0	2	0	0
T82	0	1	0	0
T84	0	5	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1218	0	0
T15	19360	163	0	0
T16	0	375	0	0
T17	0	338	0	0
T32	0	168	0	0
T33	0	174	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1008	0	0
T15	19360	133	0	0
T16	0	315	0	0
T17	0	278	0	0
T32	0	138	0	0
T33	0	144	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	698701957	0	0
T1	14491	14414	0	0
T2	536017	535989	0	0
T3	591114	591028	0	0
T4	963556	963458	0	0
T5	111372	111363	0	0
T6	7920	7830	0	0
T7	913163	913094	0	0
T21	485653	485587	0	0
T22	70732	70665	0	0
T23	12038	11953	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T25
1	1	1	Covered	T2,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T3,T21,T11
1	1	0	Covered	T1,T22,T23
1	1	1	Covered	T1,T11,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T18
0	1	Covered	T71,T45,T73
1	0	Covered	T1,T29,T45

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T11,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T29,T45

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T18
1	0	Covered	T27
1	1	Covered	T71,T45,T73

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T2,T7,T11

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T18,T45

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T21,T11

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T3,T5,T7

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T2,T5,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T2,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T15,T16,T17
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T11,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T15,T16,T17
IdleSt->Phase0St	147	Covered	T2,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T11,T18
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T112,T113
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T11,T10,T45
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T10,T45,T114
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T5,T10,T115
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T5,T7
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T11,T18,T62
TimeoutSt->Phase0St	167	Covered	T1,T29,T71

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T29,T71
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T11,T18,T62
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T112,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T11,T10,T45
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T45,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T10,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T5,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	698857116	260	0	0
CheckAccumTrig0_A	698857116	474	0	0
CheckAccumTrig1_A	698857116	26	0	0
CheckClr_A	698857116	231	0	0
CheckEn_A	698714488	295912493	0	0
CheckPhase0_A	698857116	557	0	0
CheckPhase1_A	698857116	540	0	0
CheckPhase2_A	698857116	531	0	0
CheckPhase3_A	698857116	519	0	0
CheckTimeout0_A	698857116	923	0	0
CheckTimeoutSt1_A	698857116	103728	0	0
CheckTimeoutSt2_A	698857116	830	0	0
CheckTimeoutStTrig_A	698857116	63	0	0
ErrorStAllEscAsserted_A	698857116	1347	0	0
ErrorStIsTerminal_A	698857116	1137	0	0
u_state_regs_A	698857116	698701957	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	260	0	0
T15	19360	33	0	0
T16	0	95	0	0
T17	0	68	0	0
T32	0	34	0	0
T33	0	30	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	474	0	0
T2	536017	1	0	0
T3	591114	1	0	0
T4	963556	0	0	0
T5	111372	5	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T8	0	1	0	0
T10	0	7	0	0
T11	605328	5	0	0
T18	0	2	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	26	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T29	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	231	0	0
T2	536017	1	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	4	0	0
T6	7920	0	0	0
T7	913163	1	0	0
T10	0	6	0	0
T11	605328	2	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T29	0	2	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698714488	295912493	0	0
T1	14491	3886	0	0
T2	536017	534301	0	0
T3	591114	41874	0	0
T4	963556	899667	0	0
T5	111372	1727	0	0
T6	7920	7829	0	0
T7	913163	586	0	0
T21	485653	2718	0	0
T22	70732	70664	0	0
T23	12038	9188	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	557	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	1	0	0
T4	963556	0	0	0
T5	111372	3	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T8	0	1	0	0
T10	0	7	0	0
T11	0	5	0	0
T18	0	2	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	540	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	1	0	0
T4	963556	0	0	0
T5	111372	3	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T8	0	1	0	0
T10	0	6	0	0
T11	0	4	0	0
T18	0	2	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	531	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	1	0	0
T4	963556	0	0	0
T5	111372	3	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T8	0	1	0	0
T10	0	5	0	0
T11	0	4	0	0
T18	0	2	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	519	0	0
T1	14491	1	0	0
T2	536017	1	0	0
T3	591114	1	0	0
T4	963556	0	0	0
T5	111372	2	0	0
T6	7920	0	0	0
T7	913163	2	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	4	0	0
T18	0	2	0	0
T21	485653	1	0	0
T22	70732	0	0	0
T23	12038	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	923	0	0
T1	14491	1	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	143	0	0
T18	0	6	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T29	0	1	0	0
T45	0	19	0	0
T62	0	5	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	103728	0	0
T1	14491	2	0	0
T2	536017	0	0	0
T3	591114	0	0	0
T4	963556	0	0	0
T5	111372	0	0	0
T6	7920	0	0	0
T7	913163	0	0	0
T11	0	9671	0	0
T18	0	1463	0	0
T21	485653	0	0	0
T22	70732	0	0	0
T23	12038	0	0	0
T29	0	1	0	0
T45	0	1451	0	0
T62	0	846	0	0
T70	0	120	0	0
T71	0	154	0	0
T72	0	61	0	0
T73	0	453	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	830	0	0
T8	108480	0	0	0
T9	165734	0	0	0
T10	354320	0	0	0
T11	605328	143	0	0
T18	343210	6	0	0
T19	136564	0	0	0
T24	39143	0	0	0
T26	47603	0	0	0
T31	32105	0	0	0
T45	0	15	0	0
T60	35818	0	0	0
T62	0	5	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	63	0	0
T14	139266	0	0	0
T41	0	1	0	0
T45	403675	3	0	0
T52	0	1	0	0
T68	307664	0	0	0
T71	74428	1	0	0
T72	5778	0	0	0
T73	78657	1	0	0
T74	57303	0	0	0
T75	70745	0	0	0
T77	0	2	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	3	0	0
T85	0	1	0	0
T86	354183	0	0	0
T87	632854	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1347	0	0
T15	19360	194	0	0
T16	0	390	0	0
T17	0	372	0	0
T32	0	204	0	0
T33	0	187	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	1137	0	0
T15	19360	164	0	0
T16	0	330	0	0
T17	0	312	0	0
T32	0	174	0	0
T33	0	157	0	0
T34	11582	0	0	0
T35	163335	0	0	0
T36	3673	0	0	0
T37	57657	0	0	0
T38	45384	0	0	0
T39	123898	0	0	0
T40	182913	0	0	0
T41	160730	0	0	0
T42	694516	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	698857116	698701957	0	0
T1	14491	14414	0	0
T2	536017	535989	0	0
T3	591114	591028	0	0
T4	963556	963458	0	0
T5	111372	111363	0	0
T6	7920	7830	0	0
T7	913163	913094	0	0
T21	485653	485587	0	0
T22	70732	70665	0	0
T23	12038	11953	0	0