Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63583627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30813246

1

T1

93851

T2

114337

T3

2266

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14237695	1			T1	36173		T2	44486		T3	1765
values[0x0]	39140725	1			T1	130344		T2	158816		T3	2180
values[0x1]	41018453	1			T1	129928		T2	159234		T3	2126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54377025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40019848

1

T1

118383

T2

144708

T3

2794

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	285849	1			T1	1118		T2	1458		T3	19
valid_sources[0x01]	288819	1			T1	1081		T2	1354		T3	24
valid_sources[0x02]	705090	1			T1	1101		T2	1452		T3	23
valid_sources[0x03]	282947	1			T1	1192		T2	1413		T3	28
valid_sources[0x04]	287383	1			T1	1150		T2	1384		T3	26
valid_sources[0x05]	274152	1			T1	1107		T2	1425		T3	19
valid_sources[0x06]	298310	1			T1	1187		T2	1474		T3	21
valid_sources[0x07]	286917	1			T1	1129		T2	1388		T3	27
valid_sources[0x08]	287363	1			T1	1167		T2	1389		T3	25
valid_sources[0x09]	280589	1			T1	1140		T2	1378		T3	25
valid_sources[0x0a]	289661	1			T1	1239		T2	1460		T3	21
valid_sources[0x0b]	288338	1			T1	1157		T2	1423		T3	22
valid_sources[0x0c]	283882	1			T1	1201		T2	1379		T3	20
valid_sources[0x0d]	283781	1			T1	1179		T2	1382		T3	22
valid_sources[0x0e]	282855	1			T1	1191		T2	1410		T3	14
valid_sources[0x0f]	566222	1			T1	1155		T2	1356		T3	18
valid_sources[0x10]	898556	1			T1	1216		T2	1407		T3	28
valid_sources[0x11]	279841	1			T1	1177		T2	1455		T3	24
valid_sources[0x12]	303989	1			T1	1197		T2	1398		T3	34
valid_sources[0x13]	294668	1			T1	1078		T2	1442		T3	26
valid_sources[0x14]	291649	1			T1	1140		T2	1443		T3	18
valid_sources[0x15]	287545	1			T1	1109		T2	1373		T3	30
valid_sources[0x16]	273384	1			T1	1186		T2	1452		T3	17
valid_sources[0x17]	300750	1			T1	1104		T2	1360		T3	23
valid_sources[0x18]	601180	1			T1	1141		T2	1405		T3	24
valid_sources[0x19]	655621	1			T1	1194		T2	1377		T3	26
valid_sources[0x1a]	292791	1			T1	1151		T2	1404		T3	29
valid_sources[0x1b]	311966	1			T1	1160		T2	1339		T3	18
valid_sources[0x1c]	278813	1			T1	1146		T2	1365		T3	22
valid_sources[0x1d]	286665	1			T1	1225		T2	1425		T3	35
valid_sources[0x1e]	301286	1			T1	1129		T2	1409		T3	28
valid_sources[0x1f]	292570	1			T1	1127		T2	1418		T3	19
valid_sources[0x20]	276999	1			T1	1244		T2	1433		T3	18
valid_sources[0x21]	294194	1			T1	1129		T2	1397		T3	20
valid_sources[0x22]	289698	1			T1	1163		T2	1427		T3	19
valid_sources[0x23]	284423	1			T1	1110		T2	1417		T3	15
valid_sources[0x24]	292735	1			T1	1182		T2	1453		T3	25
valid_sources[0x25]	288927	1			T1	1097		T2	1353		T3	29
valid_sources[0x26]	280898	1			T1	1132		T2	1430		T3	20
valid_sources[0x27]	296391	1			T1	1191		T2	1380		T3	25
valid_sources[0x28]	283538	1			T1	1204		T2	1348		T3	28
valid_sources[0x29]	285800	1			T1	1179		T2	1373		T3	18
valid_sources[0x2a]	284753	1			T1	1129		T2	1409		T3	21
valid_sources[0x2b]	509495	1			T1	1030		T2	1420		T3	20
valid_sources[0x2c]	282932	1			T1	1105		T2	1448		T3	39
valid_sources[0x2d]	300458	1			T1	1157		T2	1411		T3	27
valid_sources[0x2e]	285097	1			T1	1185		T2	1442		T3	23
valid_sources[0x2f]	277695	1			T1	1153		T2	1443		T3	20
valid_sources[0x30]	290393	1			T1	1196		T2	1358		T3	10
valid_sources[0x31]	298544	1			T1	1100		T2	1432		T3	25
valid_sources[0x32]	275067	1			T1	1131		T2	1455		T3	41
valid_sources[0x33]	287345	1			T1	1124		T2	1421		T3	22
valid_sources[0x34]	1218855	1			T1	1236		T2	1415		T3	28
valid_sources[0x35]	277756	1			T1	1117		T2	1386		T3	21
valid_sources[0x36]	283050	1			T1	1143		T2	1460		T3	24
valid_sources[0x37]	286830	1			T1	1236		T2	1395		T3	22
valid_sources[0x38]	308345	1			T1	1131		T2	1387		T3	30
valid_sources[0x39]	278888	1			T1	1159		T2	1447		T3	17
valid_sources[0x3a]	276202	1			T1	1206		T2	1380		T3	23
valid_sources[0x3b]	500414	1			T1	1127		T2	1411		T3	14
valid_sources[0x3c]	301780	1			T1	1087		T2	1462		T3	27
valid_sources[0x3d]	281984	1			T1	1214		T2	1395		T3	20
valid_sources[0x3e]	283549	1			T1	1064		T2	1383		T3	21
valid_sources[0x3f]	647848	1			T1	1172		T2	1446		T3	18
valid_sources[0x40]	291151	1			T1	1192		T2	1326		T3	19
valid_sources[0x41]	283071	1			T1	1219		T2	1414		T3	34
valid_sources[0x42]	291180	1			T1	1178		T2	1381		T3	32
valid_sources[0x43]	502260	1			T1	1105		T2	1493		T3	19
valid_sources[0x44]	322100	1			T1	1249		T2	1304		T3	33
valid_sources[0x45]	278621	1			T1	1103		T2	1453		T3	18
valid_sources[0x46]	302119	1			T1	1177		T2	1320		T3	20
valid_sources[0x47]	284673	1			T1	1181		T2	1411		T3	25
valid_sources[0x48]	899698	1			T1	1117		T2	1374		T3	27
valid_sources[0x49]	283964	1			T1	1158		T2	1420		T3	26
valid_sources[0x4a]	289646	1			T1	1186		T2	1424		T3	41
valid_sources[0x4b]	286701	1			T1	1225		T2	1424		T3	29
valid_sources[0x4c]	307415	1			T1	1148		T2	1502		T3	31
valid_sources[0x4d]	309453	1			T1	1251		T2	1412		T3	24
valid_sources[0x4e]	289310	1			T1	1163		T2	1417		T3	18
valid_sources[0x4f]	280362	1			T1	1106		T2	1439		T3	34
valid_sources[0x50]	283291	1			T1	1270		T2	1414		T3	32
valid_sources[0x51]	754763	1			T1	1163		T2	1405		T3	31
valid_sources[0x52]	540007	1			T1	1096		T2	1395		T3	25
valid_sources[0x53]	287358	1			T1	1188		T2	1436		T3	36
valid_sources[0x54]	286114	1			T1	1122		T2	1396		T3	17
valid_sources[0x55]	300925	1			T1	1167		T2	1395		T3	21
valid_sources[0x56]	275408	1			T1	1070		T2	1421		T3	22
valid_sources[0x57]	300413	1			T1	1174		T2	1469		T3	26
valid_sources[0x58]	287656	1			T1	1117		T2	1432		T3	13
valid_sources[0x59]	286650	1			T1	1180		T2	1407		T3	19
valid_sources[0x5a]	282945	1			T1	1160		T2	1455		T3	21
valid_sources[0x5b]	290511	1			T1	1186		T2	1367		T3	17
valid_sources[0x5c]	301270	1			T1	1127		T2	1465		T3	23
valid_sources[0x5d]	295031	1			T1	1138		T2	1489		T3	31
valid_sources[0x5e]	294386	1			T1	1156		T2	1333		T3	29
valid_sources[0x5f]	862832	1			T1	1194		T2	1358		T3	27
valid_sources[0x60]	279386	1			T1	1192		T2	1482		T3	27
valid_sources[0x61]	653678	1			T1	1165		T2	1485		T3	25
valid_sources[0x62]	293642	1			T1	1143		T2	1363		T3	22
valid_sources[0x63]	281452	1			T1	1124		T2	1436		T3	25
valid_sources[0x64]	277332	1			T1	1142		T2	1436		T3	15
valid_sources[0x65]	655399	1			T1	1158		T2	1485		T3	38
valid_sources[0x66]	295072	1			T1	1202		T2	1470		T3	28
valid_sources[0x67]	628683	1			T1	1149		T2	1421		T3	33
valid_sources[0x68]	288509	1			T1	1154		T2	1432		T3	22
valid_sources[0x69]	282058	1			T1	1096		T2	1439		T3	23
valid_sources[0x6a]	276613	1			T1	1176		T2	1453		T3	21
valid_sources[0x6b]	287415	1			T1	1131		T2	1449		T3	18
valid_sources[0x6c]	295680	1			T1	1177		T2	1355		T3	26
valid_sources[0x6d]	282852	1			T1	1130		T2	1443		T3	21
valid_sources[0x6e]	286127	1			T1	1140		T2	1384		T3	24
valid_sources[0x6f]	289526	1			T1	1187		T2	1442		T3	22
valid_sources[0x70]	283177	1			T1	1165		T2	1421		T3	23
valid_sources[0x71]	730254	1			T1	1148		T2	1436		T3	22
valid_sources[0x72]	290682	1			T1	1179		T2	1462		T3	32
valid_sources[0x73]	297125	1			T1	1135		T2	1444		T3	26
valid_sources[0x74]	288832	1			T1	1090		T2	1370		T3	21
valid_sources[0x75]	279553	1			T1	1068		T2	1407		T3	32
valid_sources[0x76]	287552	1			T1	1220		T2	1364		T3	28
valid_sources[0x77]	286789	1			T1	1161		T2	1398		T3	30
valid_sources[0x78]	693777	1			T1	1132		T2	1425		T3	26
valid_sources[0x79]	289496	1			T1	1171		T2	1399		T3	19
valid_sources[0x7a]	279726	1			T1	1124		T2	1412		T3	27
valid_sources[0x7b]	285983	1			T1	1180		T2	1391		T3	22
valid_sources[0x7c]	282292	1			T1	1092		T2	1392		T3	18
valid_sources[0x7d]	283602	1			T1	1178		T2	1399		T3	16
valid_sources[0x7e]	292941	1			T1	1253		T2	1427		T3	30
valid_sources[0x7f]	290559	1			T1	1150		T2	1429		T3	24
valid_sources[0x80]	286368	1			T1	1161		T2	1467		T3	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7107950

1

T1

17973

T2

22196

T3

874

values[0x0]

all_enables

biggest_size

14969396

1

T1

48248

T2

58886

T3

871

values[0x1]

all_enables

biggest_size

8735900

1

T1

27630

T2

33255

T3

521