Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T111,T195,T196
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13678	0	0
DisabledNoTrigBkwd_A	2147483647	833637	0	0
DisabledNoTrigFwd_A	2147483647	1480024085	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13678	0	0
T29	320872	0	0	0
T61	101732	0	0	0
T62	150603	0	0	0
T63	38333	0	0	0
T68	491008	0	0	0
T72	701114	0	0	0
T73	31504	0	0	0
T77	393536	0	0	0
T111	0	531	0	0
T195	2600	280	0	0
T196	840	156	0	0
T197	0	452	0	0
T198	0	285	0	0
T199	4231	808	0	0
T200	0	1195	0	0
T201	0	384	0	0
T202	0	991	0	0
T203	0	722	0	0
T204	0	724	0	0
T205	0	927	0	0
T206	0	917	0	0
T207	0	1144	0	0
T208	0	1158	0	0
T209	0	257	0	0
T210	0	652	0	0
T211	0	400	0	0
T212	0	902	0	0
T213	0	793	0	0
T214	52870	0	0	0
T215	67533	0	0	0
T216	229629	0	0	0
T217	574619	0	0	0
T218	23023	0	0	0
T219	243499	0	0	0
T220	991155	0	0	0
T221	4187	0	0	0
T222	155754	0	0	0
T223	24325	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	833637	0	0
T2	226574	3505	0	0
T3	63700	100	0	0
T4	577820	2060	0	0
T5	1230736	4698	0	0
T6	3090732	0	0	0
T7	254484	6	0	0
T12	404928	10477	0	0
T13	0	3931	0	0
T14	0	1292	0	0
T15	190972	27	0	0
T16	65900	6	0	0
T17	1699440	2048	0	0
T18	485776	68	0	0
T19	0	5007	0	0
T20	0	40	0	0
T23	0	244	0	0
T28	0	6316	0	0
T30	0	73	0	0
T37	0	2	0	0
T38	0	313	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1480024085	0	0
T1	1001120	527179	0	0
T2	453148	235702	0	0
T3	63700	34607	0	0
T4	577820	436791	0	0
T5	1230736	644313	0	0
T6	3090732	1846104	0	0
T15	190972	159647	0	0
T16	65900	49956	0	0
T17	1699440	870880	0	0
T18	485776	316911	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T195,T200,T212
1	1	Covered	T1,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675487858	2377	0	0
DisabledNoTrigBkwd_A	675487858	247517	0	0
DisabledNoTrigFwd_A	675487858	338078587	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	2377	0	0
T61	101732	0	0	0
T62	150603	0	0	0
T63	38333	0	0	0
T195	2600	280	0	0
T200	0	1195	0	0
T212	0	902	0	0
T214	52870	0	0	0
T215	67533	0	0	0
T216	229629	0	0	0
T217	574619	0	0	0
T218	23023	0	0	0
T219	243499	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	247517	0	0
T3	15925	12	0	0
T4	144455	0	0	0
T5	307684	1863	0	0
T6	772683	0	0	0
T7	127242	6	0	0
T12	101232	9173	0	0
T13	0	3878	0	0
T15	47743	27	0	0
T16	16475	6	0	0
T17	424860	1368	0	0
T18	121444	0	0	0
T23	0	17	0	0
T30	0	25	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	338078587	0	0
T1	250280	14440	0	0
T2	113287	113279	0	0
T3	15925	6458	0	0
T4	144455	144448	0	0
T5	307684	20631	0	0
T6	772683	772586	0	0
T15	47743	16688	0	0
T16	16475	690	0	0
T17	424860	10585	0	0
T18	121444	116005	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T198,T208
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675487858	1599	0	0
DisabledNoTrigBkwd_A	675487858	185303	0	0
DisabledNoTrigFwd_A	675487858	391458897	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1599	0	0
T29	320872	0	0	0
T68	491008	0	0	0
T72	701114	0	0	0
T73	31504	0	0	0
T77	393536	0	0	0
T196	840	156	0	0
T198	0	285	0	0
T208	0	1158	0	0
T220	991155	0	0	0
T221	4187	0	0	0
T222	155754	0	0	0
T223	24325	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	185303	0	0
T2	113287	2224	0	0
T3	15925	6	0	0
T4	144455	2060	0	0
T5	307684	4	0	0
T6	772683	0	0	0
T12	101232	3	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	680	0	0
T18	121444	0	0	0
T20	0	16	0	0
T23	0	167	0	0
T30	0	29	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	391458897	0	0
T1	250280	249867	0	0
T2	113287	6613	0	0
T3	15925	10229	0	0
T4	144455	3728	0	0
T5	307684	306514	0	0
T6	772683	717941	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	10609	0	0
T18	121444	121363	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T201,T202
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675487858	6153	0	0
DisabledNoTrigBkwd_A	675487858	188081	0	0
DisabledNoTrigFwd_A	675487858	389849581	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	6153	0	0
T76	159779	0	0	0
T199	4231	808	0	0
T200	4772	0	0	0
T201	0	384	0	0
T202	0	991	0	0
T204	0	724	0	0
T207	0	1144	0	0
T209	0	257	0	0
T210	0	652	0	0
T211	0	400	0	0
T213	0	793	0	0
T224	6738	0	0	0
T225	3834	0	0	0
T226	111223	0	0	0
T227	565489	0	0	0
T228	276227	0	0	0
T229	30222	0	0	0
T230	299060	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	188081	0	0
T2	113287	1281	0	0
T3	15925	72	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	53	0	0
T14	0	1291	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	33	0	0
T19	0	5007	0	0
T20	0	1	0	0
T23	0	29	0	0
T28	0	4874	0	0
T30	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	389849581	0	0
T1	250280	248663	0	0
T2	113287	2531	0	0
T3	15925	10870	0	0
T4	144455	144448	0	0
T5	307684	307234	0	0
T6	772683	55621	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	424843	0	0
T18	121444	28133	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T111,T197,T203
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	675487858	3549	0	0
DisabledNoTrigBkwd_A	675487858	212736	0	0
DisabledNoTrigFwd_A	675487858	360637020	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	3549	0	0
T26	142867	0	0	0
T39	143761	0	0	0
T57	240434	0	0	0
T65	61109	0	0	0
T78	11360	0	0	0
T107	264431	0	0	0
T111	1323	531	0	0
T112	31708	0	0	0
T113	162689	0	0	0
T114	98931	0	0	0
T197	0	452	0	0
T203	0	722	0	0
T205	0	927	0	0
T206	0	917	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	212736	0	0
T3	15925	10	0	0
T4	144455	0	0	0
T5	307684	2831	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	1301	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	35	0	0
T20	0	23	0	0
T23	0	31	0	0
T28	0	1442	0	0
T30	0	17	0	0
T37	0	2	0	0
T38	0	313	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	360637020	0	0
T1	250280	14209	0	0
T2	113287	113279	0	0
T3	15925	7050	0	0
T4	144455	144167	0	0
T5	307684	9934	0	0
T6	772683	299956	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	424843	0	0
T18	121444	51410	0	0