Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T15
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T3,T15,T18
1	1	1	Covered	T2,T3,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T18
0	1	Covered	T3,T18,T12
1	0	Covered	T18,T12,T20

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T12,T20

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T21,T22
1	1	Covered	T3,T18,T12

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T5,T18

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T17,T12,T23

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T4,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T16

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T2,T3,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T2,T3,T18
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T12,T24,T25
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T23,T26,T27
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T28,T21,T29
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T28,T24,T27
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T18,T12,T30
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T2,T12,T13
TimeoutSt->Phase0St	167	Covered	T3,T18,T12

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T12
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T24,T25
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T26,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T21,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T24,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T12,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	696	0	0
CheckAccumTrig0_A	2147483647	2208	0	0
CheckAccumTrig1_A	2147483647	114	0	0
CheckClr_A	2147483647	1017	0	0
CheckEn_A	2147483647	1181661523	0	0
CheckPhase0_A	2147483647	2507	0	0
CheckPhase1_A	2147483647	2459	0	0
CheckPhase2_A	2147483647	2423	0	0
CheckPhase3_A	2147483647	2380	0	0
CheckTimeout0_A	2147483647	6742	0	0
CheckTimeoutSt1_A	2147483647	583537	0	0
CheckTimeoutSt2_A	2147483647	6383	0	0
CheckTimeoutStTrig_A	2147483647	240	0	0
ErrorStAllEscAsserted_A	2147483647	3553	0	0
ErrorStIsTerminal_A	2147483647	2953	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	696	0	0
T9	90452	130	0	0
T10	0	177	0	0
T11	0	125	0	0
T14	1282964	0	0	0
T19	1615068	0	0	0
T20	50996	0	0	0
T23	1676656	0	0	0
T30	217360	0	0	0
T31	0	126	0	0
T32	0	138	0	0
T33	521852	0	0	0
T34	93972	0	0	0
T35	489340	0	0	0
T36	258232	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T2	226574	2	0	0
T3	63700	3	0	0
T4	577820	1	0	0
T5	1230736	3	0	0
T6	3090732	0	0	0
T7	254484	1	0	0
T12	404928	10	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	190972	1	0	0
T16	65900	1	0	0
T17	1699440	2	0	0
T18	485776	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T23	0	8	0	0
T24	0	2	0	0
T28	0	12	0	0
T30	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	114	0	0
T7	381726	0	0	0
T9	67839	0	0	0
T12	303696	1	0	0
T13	373977	0	0	0
T14	1282964	0	0	0
T18	242888	1	0	0
T19	1615068	0	0	0
T20	50996	1	0	0
T22	0	1	0	0
T23	1257492	0	0	0
T25	0	1	0	0
T27	0	4	0	0
T28	0	2	0	0
T30	163020	0	0	0
T33	260926	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0
T37	9662	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	45059	0	0	0
T55	50276	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1017	0	0
T7	381726	0	0	0
T9	67839	0	0	0
T12	303696	3	0	0
T13	373977	0	0	0
T14	1282964	0	0	0
T18	121444	1	0	0
T19	1615068	0	0	0
T20	50996	1	0	0
T21	0	5	0	0
T23	1676656	2	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	2	0	0
T27	0	5	0	0
T28	0	13	0	0
T30	163020	0	0	0
T33	391389	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T54	45059	0	0	0
T55	50276	0	0	0
T56	0	2	0	0
T57	0	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1181661523	0	0
T1	1001120	527178	0	0
T2	453148	229960	0	0
T3	63700	5802	0	0
T4	577820	435761	0	0
T5	1230736	336666	0	0
T6	3090732	1846102	0	0
T15	190972	151430	0	0
T16	65900	49953	0	0
T17	1699440	870878	0	0
T18	485776	273351	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2507	0	0
T2	226574	2	0	0
T3	63700	4	0	0
T4	577820	1	0	0
T5	1230736	3	0	0
T6	3090732	0	0	0
T7	254484	1	0	0
T12	404928	14	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	190972	1	0	0
T16	65900	1	0	0
T17	1699440	2	0	0
T18	485776	3	0	0
T19	0	1	0	0
T20	0	3	0	0
T23	0	11	0	0
T28	0	15	0	0
T30	0	5	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2459	0	0
T2	226574	2	0	0
T3	63700	4	0	0
T4	577820	1	0	0
T5	1230736	3	0	0
T6	3090732	0	0	0
T7	254484	1	0	0
T12	404928	14	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	190972	1	0	0
T16	65900	1	0	0
T17	1699440	2	0	0
T18	485776	3	0	0
T19	0	1	0	0
T20	0	3	0	0
T23	0	10	0	0
T28	0	15	0	0
T30	0	5	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T2	226574	2	0	0
T3	63700	4	0	0
T4	577820	1	0	0
T5	1230736	3	0	0
T6	3090732	0	0	0
T7	254484	1	0	0
T12	404928	14	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	190972	1	0	0
T16	65900	1	0	0
T17	1699440	2	0	0
T18	485776	3	0	0
T19	0	1	0	0
T20	0	3	0	0
T23	0	10	0	0
T28	0	15	0	0
T30	0	5	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2380	0	0
T2	226574	2	0	0
T3	63700	4	0	0
T4	577820	1	0	0
T5	1230736	3	0	0
T6	3090732	0	0	0
T7	254484	1	0	0
T12	404928	14	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	190972	1	0	0
T16	65900	1	0	0
T17	1699440	2	0	0
T18	485776	3	0	0
T19	0	1	0	0
T20	0	3	0	0
T23	0	10	0	0
T28	0	14	0	0
T30	0	5	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6742	0	0
T2	113287	4	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T7	381726	0	0	0
T9	67839	0	0	0
T12	404928	10	0	0
T13	373977	1	0	0
T14	962223	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	242888	3	0	0
T19	1211301	1	0	0
T20	38247	1	0	0
T21	0	1	0	0
T23	1257492	5	0	0
T27	0	13	0	0
T28	0	36	0	0
T30	163020	1	0	0
T33	260926	0	0	0
T37	0	1	0	0
T57	0	2	0	0
T58	0	10	0	0
T60	0	3	0	0
T64	0	6	0	0
T65	0	2	0	0
T66	0	17	0	0
T67	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	583537	0	0
T2	113287	244	0	0
T3	15925	268	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T7	381726	0	0	0
T9	67839	0	0	0
T12	404928	590	0	0
T13	373977	39	0	0
T14	962223	752	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	242888	100	0	0
T19	1211301	127	0	0
T20	38247	20	0	0
T21	0	206	0	0
T23	1257492	1469	0	0
T27	0	944	0	0
T28	0	5935	0	0
T30	163020	5	0	0
T33	260926	0	0	0
T37	0	852	0	0
T57	0	266	0	0
T58	0	2727	0	0
T60	0	1419	0	0
T64	0	1093	0	0
T65	0	483	0	0
T66	0	1244	0	0
T67	0	1347	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6383	0	0
T2	113287	4	0	0
T3	15925	0	0	0
T4	144455	0	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	202464	3	0	0
T13	124659	1	0	0
T14	320741	4	0	0
T19	807534	1	0	0
T20	12749	0	0	0
T21	0	1	0	0
T23	419164	1	0	0
T27	0	8	0	0
T28	0	24	0	0
T30	54340	0	0	0
T33	260926	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0
T37	9662	0	0	0
T38	329016	0	0	0
T41	0	6	0	0
T54	45059	0	0	0
T55	50276	0	0	0
T57	0	1	0	0
T58	0	5	0	0
T60	0	6	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T66	0	17	0	0
T67	0	12	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	47478	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	240	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T7	381726	0	0	0
T9	45226	0	0	0
T12	303696	3	0	0
T13	249318	0	0	0
T14	641482	0	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	1	0	0
T19	807534	0	0	0
T20	25498	0	0	0
T23	838328	2	0	0
T24	124497	0	0	0
T28	422960	1	0	0
T30	108680	0	0	0
T33	260926	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	877111	0	0	0
T58	0	5	0	0
T60	0	2	0	0
T61	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T72	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3553	0	0
T9	90452	695	0	0
T10	0	726	0	0
T11	0	703	0	0
T14	1282964	0	0	0
T19	1615068	0	0	0
T20	50996	0	0	0
T23	1676656	0	0	0
T30	217360	0	0	0
T31	0	715	0	0
T32	0	714	0	0
T33	521852	0	0	0
T34	93972	0	0	0
T35	489340	0	0	0
T36	258232	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2953	0	0
T9	90452	575	0	0
T10	0	606	0	0
T11	0	583	0	0
T14	1282964	0	0	0
T19	1615068	0	0	0
T20	50996	0	0	0
T23	1676656	0	0	0
T30	217360	0	0	0
T31	0	595	0	0
T32	0	594	0	0
T33	521852	0	0	0
T34	93972	0	0	0
T35	489340	0	0	0
T36	258232	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1001120	1001096	0	0
T2	453148	453116	0	0
T3	63700	63444	0	0
T4	577820	577792	0	0
T5	1230736	1230700	0	0
T6	3090732	3090344	0	0
T15	190972	190612	0	0
T16	65900	65688	0	0
T17	1699440	1699372	0	0
T18	485776	485452	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T15,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T15,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T18
1	0	1	Covered	T1,T12,T7
1	1	0	Covered	T15,T18,T12
1	1	1	Covered	T12,T23,T19

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T19
0	1	Covered	T12,T23,T37
1	0	Covered	T12,T28,T27

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T23,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T28,T27

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T19
1	0	Not Covered
1	1	Covered	T12,T23,T37

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T3,T5,T12

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T5
1	Covered	T12,T35,T54

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T12
1	Covered	T15,T16,T17

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T15,T5
1	Covered	T7,T13,T23

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T16,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T15,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T16,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T15,T5
Phase1St	193	Covered	T3,T15,T5
Phase2St	210	Covered	T3,T15,T5
Phase3St	228	Covered	T3,T15,T5
TerminalSt	244	Covered	T3,T15,T5
TimeoutSt	154	Covered	T12,T23,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T3,T15,T5
IdleSt->TimeoutSt	154	Covered	T12,T23,T19
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T12,T24,T25
Phase0St->Phase1St	193	Covered	T3,T15,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T41,T77
Phase1St->Phase2St	210	Covered	T3,T15,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T28,T29,T77
Phase2St->Phase3St	228	Covered	T3,T15,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T28,T24,T21
Phase3St->TerminalSt	244	Covered	T3,T15,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T12,T23,T37
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T19,T64,T28
TimeoutSt->Phase0St	167	Covered	T12,T23,T37

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T37
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T64,T28
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T24,T25
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T15,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T15,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T41,T77
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T15,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T15,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T29,T77
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T15,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T15,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T24,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T15,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T15,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T37,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T15,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675487858	192	0	0
CheckAccumTrig0_A	675487858	813	0	0
CheckAccumTrig1_A	675487858	46	0	0
CheckClr_A	675487858	399	0	0
CheckEn_A	675393729	263795250	0	0
CheckPhase0_A	675487858	891	0	0
CheckPhase1_A	675487858	870	0	0
CheckPhase2_A	675487858	855	0	0
CheckPhase3_A	675487858	837	0	0
CheckTimeout0_A	675487858	1552	0	0
CheckTimeoutSt1_A	675487858	115878	0	0
CheckTimeoutSt2_A	675487858	1446	0	0
CheckTimeoutStTrig_A	675487858	60	0	0
ErrorStAllEscAsserted_A	675487858	892	0	0
ErrorStIsTerminal_A	675487858	742	0	0
u_state_regs_A	675487858	675352961	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	192	0	0
T9	22613	41	0	0
T10	0	53	0	0
T11	0	16	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	35	0	0
T32	0	47	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	813	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	1	0	0
T12	101232	6	0	0
T13	0	1	0	0
T15	47743	1	0	0
T16	16475	1	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T23	0	1	0	0
T30	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	46	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	1	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T25	0	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	399	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	3	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T24	0	2	0	0
T26	0	2	0	0
T27	0	3	0	0
T28	0	5	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675393729	263795250	0	0
T1	250280	14440	0	0
T2	113287	113279	0	0
T3	15925	612	0	0
T4	144455	144448	0	0
T5	307684	17471	0	0
T6	772683	772585	0	0
T15	47743	8474	0	0
T16	16475	690	0	0
T17	424860	10584	0	0
T18	121444	116004	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	891	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	1	0	0
T12	101232	8	0	0
T13	0	1	0	0
T15	47743	1	0	0
T16	16475	1	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	870	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	1	0	0
T12	101232	8	0	0
T13	0	1	0	0
T15	47743	1	0	0
T16	16475	1	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	855	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	1	0	0
T12	101232	8	0	0
T13	0	1	0	0
T15	47743	1	0	0
T16	16475	1	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	837	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	1	0	0
T12	101232	8	0	0
T13	0	1	0	0
T15	47743	1	0	0
T16	16475	1	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1552	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	3	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	1	0	0
T20	12749	0	0	0
T23	419164	1	0	0
T27	0	7	0	0
T28	0	10	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T37	0	1	0	0
T58	0	2	0	0
T64	0	2	0	0
T66	0	7	0	0
T67	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	115878	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	184	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	127	0	0
T20	12749	0	0	0
T23	419164	750	0	0
T27	0	601	0	0
T28	0	1274	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T37	0	852	0	0
T58	0	655	0	0
T64	0	324	0	0
T66	0	501	0	0
T67	0	1347	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1446	0	0
T19	403767	1	0	0
T27	0	5	0	0
T28	0	9	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0
T37	9662	0	0	0
T38	329016	0	0	0
T41	0	6	0	0
T54	45059	0	0	0
T55	50276	0	0	0
T58	0	1	0	0
T60	0	2	0	0
T62	0	2	0	0
T64	0	2	0	0
T66	0	7	0	0
T67	0	6	0	0
T71	47478	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	60	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	2	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	1	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T37	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T63	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	892	0	0
T9	22613	163	0	0
T10	0	165	0	0
T11	0	182	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	197	0	0
T32	0	185	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	742	0	0
T9	22613	133	0	0
T10	0	135	0	0
T11	0	152	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	167	0	0
T32	0	155	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	675352961	0	0
T1	250280	250274	0	0
T2	113287	113279	0	0
T3	15925	15861	0	0
T4	144455	144448	0	0
T5	307684	307675	0	0
T6	772683	772586	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	424843	0	0
T18	121444	121363	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T17,T12
1	0	1	Covered	T12,T7,T33
1	1	0	Covered	T3,T18,T12
1	1	1	Covered	T12,T23,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T23,T20
0	1	Covered	T12,T23,T64
1	0	Covered	T20,T46,T47

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T23,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T46,T47

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T20
1	0	Not Covered
1	1	Covered	T12,T23,T64

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T23,T20,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T17,T78,T79

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T4,T12,T30

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T17,T12
1	Covered	T2,T3,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T17,T30

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T12,T23,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T12,T23,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T69,T50,T80
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T23,T44,T50
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T50,T81,T82
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T25,T69,T83
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T12,T23,T37
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T12,T28,T58
TimeoutSt->Phase0St	167	Covered	T12,T23,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T28,T58
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T50,T84
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T44,T50
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T50,T81,T82
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T69,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T37,T56,T58
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675487858	162	0	0
CheckAccumTrig0_A	675487858	432	0	0
CheckAccumTrig1_A	675487858	27	0	0
CheckClr_A	675487858	190	0	0
CheckEn_A	675393729	310661323	0	0
CheckPhase0_A	675487858	521	0	0
CheckPhase1_A	675487858	510	0	0
CheckPhase2_A	675487858	504	0	0
CheckPhase3_A	675487858	495	0	0
CheckTimeout0_A	675487858	2123	0	0
CheckTimeoutSt1_A	675487858	183416	0	0
CheckTimeoutSt2_A	675487858	2025	0	0
CheckTimeoutStTrig_A	675487858	69	0	0
ErrorStAllEscAsserted_A	675487858	865	0	0
ErrorStIsTerminal_A	675487858	715	0	0
u_state_regs_A	675487858	675352961	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	162	0	0
T9	22613	30	0	0
T10	0	41	0	0
T11	0	37	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	36	0	0
T32	0	18	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	432	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	1	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T12	101232	1	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T19	0	1	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	27	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	1	0	0
T22	0	1	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0
T37	9662	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	45059	0	0	0
T55	50276	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	190	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T21	0	2	0	0
T23	419164	1	0	0
T25	0	1	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0
T37	0	1	0	0
T54	45059	0	0	0
T55	50276	0	0	0
T56	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675393729	310661323	0	0
T1	250280	249866	0	0
T2	113287	871	0	0
T3	15925	3946	0	0
T4	144455	2698	0	0
T5	307684	2027	0	0
T6	772683	717940	0	0
T15	47743	47652	0	0
T16	16475	16421	0	0
T17	424860	10608	0	0
T18	121444	121362	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	521	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	1	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T12	101232	2	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T30	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	510	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	1	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T12	101232	2	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	504	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	1	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T12	101232	2	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	495	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	1	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T12	101232	2	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	1	0	0
T18	121444	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T30	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	2123	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	4	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	1	0	0
T21	0	1	0	0
T23	419164	1	0	0
T28	0	3	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T58	0	5	0	0
T60	0	3	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	10	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	183416	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	199	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	20	0	0
T21	0	206	0	0
T23	419164	273	0	0
T28	0	447	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T58	0	1069	0	0
T60	0	1419	0	0
T64	0	68	0	0
T65	0	274	0	0
T66	0	743	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	2025	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	3	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T21	0	1	0	0
T23	419164	0	0	0
T28	0	3	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T58	0	2	0	0
T60	0	2	0	0
T63	0	1	0	0
T66	0	10	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	69	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	1	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	1	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T41	0	1	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T69	0	1	0	0
T72	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	865	0	0
T9	22613	174	0	0
T10	0	177	0	0
T11	0	182	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	169	0	0
T32	0	163	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	715	0	0
T9	22613	144	0	0
T10	0	147	0	0
T11	0	152	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	139	0	0
T32	0	133	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	675352961	0	0
T1	250280	250274	0	0
T2	113287	113279	0	0
T3	15925	15861	0	0
T4	144455	144448	0	0
T5	307684	307675	0	0
T6	772683	772586	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	424843	0	0
T18	121444	121363	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T13,T30

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T18,T12,T13
1	1	1	Covered	T2,T3,T18

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T18
0	1	Covered	T3,T18,T28
1	0	Covered	T18,T23,T28

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T23,T28

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T21
1	1	Covered	T3,T18,T28

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T18,T28,T65

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T23,T19,T28

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T18,T13
1	Covered	T2,T18,T23

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T23
1	Covered	T3,T13,T30

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T18,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T3,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T18,T13,T30

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T18,T20,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T18
Phase1St	193	Covered	T2,T3,T18
Phase2St	210	Covered	T2,T3,T18
Phase3St	228	Covered	T2,T3,T18
TerminalSt	244	Covered	T2,T3,T18
TimeoutSt	154	Covered	T2,T3,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T2,T13,T30
IdleSt->TimeoutSt	154	Covered	T2,T3,T18
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T85,T86,T87
Phase0St->Phase1St	193	Covered	T2,T3,T18
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T27,T29,T88
Phase1St->Phase2St	210	Covered	T2,T3,T18
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T21,T89,T90
Phase2St->Phase3St	228	Covered	T2,T3,T18
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T27,T90,T91
Phase3St->TerminalSt	244	Covered	T2,T3,T18
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T18,T23,T20
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T2,T13,T23
TimeoutSt->Phase0St	167	Covered	T3,T18,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T30
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T13,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T85,T86,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T29,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T21,T89,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T90,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T23,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675487858	165	0	0
CheckAccumTrig0_A	675487858	452	0	0
CheckAccumTrig1_A	675487858	23	0	0
CheckClr_A	675487858	209	0	0
CheckEn_A	675393729	327782188	0	0
CheckPhase0_A	675487858	521	0	0
CheckPhase1_A	675487858	514	0	0
CheckPhase2_A	675487858	507	0	0
CheckPhase3_A	675487858	499	0	0
CheckTimeout0_A	675487858	1905	0	0
CheckTimeoutSt1_A	675487858	168384	0	0
CheckTimeoutSt2_A	675487858	1827	0	0
CheckTimeoutStTrig_A	675487858	53	0	0
ErrorStAllEscAsserted_A	675487858	893	0	0
ErrorStIsTerminal_A	675487858	743	0	0
u_state_regs_A	675487858	675352961	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	165	0	0
T9	22613	30	0	0
T10	0	38	0	0
T11	0	38	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	21	0	0
T32	0	38	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	452	0	0
T2	113287	1	0	0
T3	15925	0	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	0	10	0	0
T30	0	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	23	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	0	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T18	121444	1	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	54340	0	0	0
T69	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	209	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	0	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T18	121444	1	0	0
T19	403767	0	0	0
T20	12749	1	0	0
T21	0	3	0	0
T23	419164	1	0	0
T27	0	2	0	0
T28	0	8	0	0
T30	54340	0	0	0
T57	0	2	0	0
T60	0	1	0	0
T79	0	3	0	0
T98	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675393729	327782188	0	0
T1	250280	248663	0	0
T2	113287	2531	0	0
T3	15925	620	0	0
T4	144455	144448	0	0
T5	307684	307234	0	0
T6	772683	55621	0	0
T15	47743	47652	0	0
T16	16475	16421	0	0
T17	424860	424843	0	0
T18	121444	20247	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	521	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	2	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	12	0	0
T30	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	514	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	2	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	12	0	0
T30	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	507	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	2	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	12	0	0
T30	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	499	0	0
T2	113287	1	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	2	0	0
T19	0	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	12	0	0
T30	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1905	0	0
T2	113287	4	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	2	0	0
T23	0	2	0	0
T27	0	5	0	0
T28	0	14	0	0
T57	0	1	0	0
T58	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	168384	0	0
T2	113287	244	0	0
T3	15925	268	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	39	0	0
T14	0	752	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	94	0	0
T23	0	193	0	0
T27	0	295	0	0
T28	0	2589	0	0
T57	0	237	0	0
T58	0	774	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1827	0	0
T2	113287	4	0	0
T3	15925	0	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T12	101232	0	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	0	0	0
T23	0	1	0	0
T27	0	3	0	0
T28	0	12	0	0
T57	0	1	0	0
T58	0	2	0	0
T60	0	2	0	0
T67	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	53	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	0	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	0	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	1	0	0
T28	0	1	0	0
T45	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T72	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T99	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	893	0	0
T9	22613	176	0	0
T10	0	198	0	0
T11	0	169	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	182	0	0
T32	0	168	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	743	0	0
T9	22613	146	0	0
T10	0	168	0	0
T11	0	139	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	152	0	0
T32	0	138	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	675352961	0	0
T1	250280	250274	0	0
T2	113287	113279	0	0
T3	15925	15861	0	0
T4	144455	144448	0	0
T5	307684	307675	0	0
T6	772683	772586	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	424843	0	0
T18	121444	121363	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T18
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T18

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T12

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T18,T12
1	0	1	Covered	T1,T4,T12
1	1	0	Covered	T12,T23,T14
1	1	1	Covered	T18,T12,T30

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T12,T30
0	1	Covered	T28,T65,T27
1	0	Covered	T18,T12,T30

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T12,T30
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T12,T30

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T12,T30
1	0	Covered	T22
1	1	Covered	T28,T65,T27

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T30
1	Covered	T5,T18,T12

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T18
1	Covered	T12,T23,T20

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T18
1	Covered	T12,T30,T23

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T18,T12
1	Covered	T3,T30,T23

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T12,T30

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T5,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T3,T12,T30

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T12,T30,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T9,T10,T11
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T5,T18
Phase1St	193	Covered	T3,T5,T18
Phase2St	210	Covered	T3,T5,T18
Phase3St	228	Covered	T3,T5,T18
TerminalSt	244	Covered	T3,T5,T18
TimeoutSt	154	Covered	T18,T12,T30

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T9,T10,T11
IdleSt->Phase0St	147	Covered	T3,T5,T12
IdleSt->TimeoutSt	154	Covered	T18,T12,T30
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T88,T100,T50
Phase0St->Phase1St	193	Covered	T3,T5,T18
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T101,T102,T103
Phase1St->Phase2St	210	Covered	T3,T5,T18
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T26,T58,T44
Phase2St->Phase3St	228	Covered	T3,T5,T18
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T28,T77,T104
Phase3St->TerminalSt	244	Covered	T3,T5,T18
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T12,T30,T23
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T12,T23,T64
TimeoutSt->Phase0St	167	Covered	T18,T12,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T12,T30
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T12,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T12,T30
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T23,T64
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T50,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T101,T103,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T58,T44
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T77,T104
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T30,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	675487858	177	0	0
CheckAccumTrig0_A	675487858	511	0	0
CheckAccumTrig1_A	675487858	18	0	0
CheckClr_A	675487858	219	0	0
CheckEn_A	675393729	279422762	0	0
CheckPhase0_A	675487858	574	0	0
CheckPhase1_A	675487858	565	0	0
CheckPhase2_A	675487858	557	0	0
CheckPhase3_A	675487858	549	0	0
CheckTimeout0_A	675487858	1162	0	0
CheckTimeoutSt1_A	675487858	115859	0	0
CheckTimeoutSt2_A	675487858	1085	0	0
CheckTimeoutStTrig_A	675487858	58	0	0
ErrorStAllEscAsserted_A	675487858	903	0	0
ErrorStIsTerminal_A	675487858	753	0	0
u_state_regs_A	675487858	675352961	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	177	0	0
T9	22613	29	0	0
T10	0	45	0	0
T11	0	34	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	34	0	0
T32	0	35	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	511	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	3	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T24	0	1	0	0
T28	0	2	0	0
T30	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	18	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	1	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T18	121444	1	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T21	0	1	0	0
T23	419164	0	0	0
T30	54340	1	0	0
T47	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	219	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	1	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	2	0	0
T26	0	3	0	0
T28	0	1	0	0
T30	54340	1	0	0
T33	130463	0	0	0
T39	0	1	0	0
T58	0	1	0	0
T78	0	1	0	0
T98	0	1	0	0
T107	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675393729	279422762	0	0
T1	250280	14209	0	0
T2	113287	113279	0	0
T3	15925	624	0	0
T4	144455	144167	0	0
T5	307684	9934	0	0
T6	772683	299956	0	0
T15	47743	47652	0	0
T16	16475	16421	0	0
T17	424860	424843	0	0
T18	121444	15738	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	574	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	3	0	0
T30	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	565	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	3	0	0
T30	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	557	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	3	0	0
T30	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	549	0	0
T3	15925	1	0	0
T4	144455	0	0	0
T5	307684	1	0	0
T6	772683	0	0	0
T7	127242	0	0	0
T12	101232	4	0	0
T15	47743	0	0	0
T16	16475	0	0	0
T17	424860	0	0	0
T18	121444	1	0	0
T20	0	1	0	0
T23	0	3	0	0
T28	0	2	0	0
T30	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1162	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	3	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T18	121444	1	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	1	0	0
T27	0	1	0	0
T28	0	9	0	0
T30	54340	1	0	0
T57	0	1	0	0
T64	0	3	0	0
T65	0	1	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	115859	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	207	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T18	121444	6	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	253	0	0
T27	0	48	0	0
T28	0	1625	0	0
T30	54340	5	0	0
T57	0	29	0	0
T58	0	229	0	0
T64	0	701	0	0
T65	0	209	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	1085	0	0
T7	127242	0	0	0
T9	22613	0	0	0
T12	101232	2	0	0
T13	124659	0	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T21	0	2	0	0
T23	419164	1	0	0
T28	0	8	0	0
T30	54340	0	0	0
T33	130463	0	0	0
T41	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	0	1	0	0
T64	0	3	0	0
T66	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	58	0	0
T24	124497	0	0	0
T27	0	1	0	0
T28	422960	1	0	0
T39	143761	0	0	0
T41	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T56	877111	0	0	0
T58	0	1	0	0
T65	61109	1	0	0
T78	11360	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	1323	0	0	0
T112	31708	0	0	0
T113	162689	0	0	0
T114	98931	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	903	0	0
T9	22613	182	0	0
T10	0	186	0	0
T11	0	170	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	167	0	0
T32	0	198	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	753	0	0
T9	22613	152	0	0
T10	0	156	0	0
T11	0	140	0	0
T14	320741	0	0	0
T19	403767	0	0	0
T20	12749	0	0	0
T23	419164	0	0	0
T30	54340	0	0	0
T31	0	137	0	0
T32	0	168	0	0
T33	130463	0	0	0
T34	23493	0	0	0
T35	122335	0	0	0
T36	64558	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675487858	675352961	0	0
T1	250280	250274	0	0
T2	113287	113279	0	0
T3	15925	15861	0	0
T4	144455	144448	0	0
T5	307684	307675	0	0
T6	772683	772586	0	0
T15	47743	47653	0	0
T16	16475	16422	0	0
T17	424860	424843	0	0
T18	121444	121363	0	0