Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T79,T184
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13574	0	0
DisabledNoTrigBkwd_A	2147483647	810525	0	0
DisabledNoTrigFwd_A	2147483647	1378230642	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13574	0	0
T7	708954	0	0	0
T10	144342	0	0	0
T15	237784	0	0	0
T16	361143	0	0	0
T26	118729	0	0	0
T35	0	718	0	0
T40	4610	954	0	0
T42	525575	0	0	0
T43	19976	0	0	0
T55	178689	0	0	0
T56	111214	0	0	0
T57	478583	0	0	0
T59	110239	0	0	0
T60	9224	0	0	0
T61	60513	0	0	0
T69	167869	0	0	0
T79	3689	367	0	0
T80	47047	0	0	0
T184	4014	987	0	0
T189	432604	0	0	0
T190	0	691	0	0
T191	0	1322	0	0
T192	0	800	0	0
T193	0	315	0	0
T194	0	704	0	0
T195	0	432	0	0
T196	0	671	0	0
T197	0	1134	0	0
T198	0	451	0	0
T199	0	681	0	0
T200	0	351	0	0
T201	0	420	0	0
T202	0	581	0	0
T203	0	663	0	0
T204	0	736	0	0
T205	0	596	0	0
T206	13277	0	0	0
T207	22090	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	810525	0	0
T2	584076	531	0	0
T3	2080676	10210	0	0
T4	515640	15	0	0
T5	407504	4975	0	0
T7	0	2025	0	0
T8	0	23079	0	0
T14	0	3151	0	0
T16	0	631	0	0
T17	240608	3	0	0
T18	135924	15	0	0
T19	785612	579	0	0
T20	134928	88	0	0
T21	839320	174	0	0
T22	317796	94	0	0
T23	0	78	0	0
T25	0	65	0	0
T28	0	627	0	0
T40	0	20	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1378230642	0	0
T1	347540	316403	0	0
T2	584076	582139	0	0
T3	2080676	535465	0	0
T4	515640	336249	0	0
T5	407504	1118053	0	0
T17	240608	187662	0	0
T18	135924	126361	0	0
T19	785612	201130	0	0
T20	134928	101559	0	0
T21	839320	413910	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T79,T199,T204
1	1	Covered	T2,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	646783603	2380	0	0
DisabledNoTrigBkwd_A	646783603	225611	0	0
DisabledNoTrigFwd_A	646783603	298994037	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	2380	0	0
T10	144342	0	0	0
T42	525575	0	0	0
T43	19976	0	0	0
T56	111214	0	0	0
T57	478583	0	0	0
T59	110239	0	0	0
T60	9224	0	0	0
T61	60513	0	0	0
T79	3689	367	0	0
T80	47047	0	0	0
T199	0	681	0	0
T204	0	736	0	0
T205	0	596	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	225611	0	0
T2	146019	9	0	0
T3	520169	0	0	0
T4	128910	2	0	0
T5	101876	1339	0	0
T17	60152	3	0	0
T18	33981	15	0	0
T19	196403	145	0	0
T20	33732	88	0	0
T21	209830	95	0	0
T22	79449	2	0	0
T23	0	78	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	298994037	0	0
T1	86885	86831	0	0
T2	146019	145359	0	0
T3	520169	520161	0	0
T4	128910	3045	0	0
T5	101876	6545	0	0
T17	60152	7365	0	0
T18	33981	24607	0	0
T19	196403	1622	0	0
T20	33732	582	0	0
T21	209830	5418	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T190,T192
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	646783603	4682	0	0
DisabledNoTrigBkwd_A	646783603	200706	0	0
DisabledNoTrigFwd_A	646783603	340218696	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	4682	0	0
T7	708954	0	0	0
T15	237784	0	0	0
T16	361143	0	0	0
T26	118729	0	0	0
T40	4610	954	0	0
T55	178689	0	0	0
T69	167869	0	0	0
T189	432604	0	0	0
T190	0	691	0	0
T192	0	800	0	0
T195	0	432	0	0
T196	0	671	0	0
T197	0	1134	0	0
T206	13277	0	0	0
T207	22090	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	200706	0	0
T2	146019	503	0	0
T3	520169	2336	0	0
T4	128910	0	0	0
T5	101876	4	0	0
T8	0	21063	0	0
T14	0	1402	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	184	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	18	0	0
T28	0	1	0	0
T40	0	20	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	340218696	0	0
T1	86885	80090	0	0
T2	146019	146630	0	0
T3	520169	3060	0	0
T4	128910	128902	0	0
T5	101876	100586	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	594	0	0
T20	33732	33659	0	0
T21	209830	193148	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T35,T194
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	646783603	4875	0	0
DisabledNoTrigBkwd_A	646783603	200085	0	0
DisabledNoTrigFwd_A	646783603	348666344	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	4875	0	0
T35	0	718	0	0
T71	39352	0	0	0
T184	4014	987	0	0
T185	52077	0	0	0
T186	149073	0	0	0
T187	63287	0	0	0
T188	29320	0	0	0
T194	0	704	0	0
T198	0	451	0	0
T200	0	351	0	0
T201	0	420	0	0
T202	0	581	0	0
T203	0	663	0	0
T208	192478	0	0	0
T209	22296	0	0	0
T210	106033	0	0	0
T211	85682	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	200085	0	0
T2	146019	7	0	0
T3	520169	1835	0	0
T4	128910	13	0	0
T5	101876	52	0	0
T8	0	2016	0	0
T14	0	893	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	250	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	72	0	0
T25	0	26	0	0
T28	0	624	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	348666344	0	0
T1	86885	86831	0	0
T2	146019	145115	0	0
T3	520169	3071	0	0
T4	128910	91738	0	0
T5	101876	920426	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	2600	0	0
T20	33732	33659	0	0
T21	209830	209754	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T191,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	646783603	1637	0	0
DisabledNoTrigBkwd_A	646783603	184123	0	0
DisabledNoTrigFwd_A	646783603	390351565	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1637	0	0
T191	5553	1322	0	0
T192	4304	0	0	0
T193	0	315	0	0
T212	156434	0	0	0
T213	125400	0	0	0
T214	49212	0	0	0
T215	722469	0	0	0
T216	249237	0	0	0
T217	24373	0	0	0
T218	76927	0	0	0
T219	21371	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	184123	0	0
T2	146019	12	0	0
T3	520169	6039	0	0
T4	128910	0	0	0
T5	101876	3580	0	0
T7	0	2025	0	0
T14	0	856	0	0
T16	0	631	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	79	0	0
T22	79449	19	0	0
T25	0	21	0	0
T28	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	390351565	0	0
T1	86885	62651	0	0
T2	146019	145035	0	0
T3	520169	9173	0	0
T4	128910	112564	0	0
T5	101876	90496	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	196314	0	0
T20	33732	33659	0	0
T21	209830	5590	0	0