Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T19
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T5

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T5,T8
1	0	Covered	T3,T5,T18

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T18

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T24
1	1	Covered	T1,T5,T8

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T3,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T1,T3,T5
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T25,T26,T27
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T20,T23,T8
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T8,T28,T14
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T14,T15,T27
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T2,T3,T5
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T3,T5
TimeoutSt->Phase0St	167	Covered	T3,T5,T18

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T25,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T23,T8
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T28,T14
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	661	0	0
CheckAccumTrig0_A	2147483647	2411	0	0
CheckAccumTrig1_A	2147483647	113	0	0
CheckClr_A	2147483647	1150	0	0
CheckEn_A	2147483647	1039516248	0	0
CheckPhase0_A	2147483647	2760	0	0
CheckPhase1_A	2147483647	2690	0	0
CheckPhase2_A	2147483647	2621	0	0
CheckPhase3_A	2147483647	2576	0	0
CheckTimeout0_A	2147483647	5727	0	0
CheckTimeoutSt1_A	2147483647	524097	0	0
CheckTimeoutSt2_A	2147483647	5327	0	0
CheckTimeoutStTrig_A	2147483647	283	0	0
ErrorStAllEscAsserted_A	2147483647	3618	0	0
ErrorStIsTerminal_A	2147483647	3018	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	661	0	0
T11	82720	140	0	0
T12	0	129	0	0
T13	0	135	0	0
T29	0	127	0	0
T30	0	130	0	0
T31	419104	0	0	0
T32	1084552	0	0	0
T33	2324616	0	0	0
T34	48404	0	0	0
T35	12276	0	0	0
T36	10176	0	0	0
T37	67236	0	0	0
T38	207944	0	0	0
T39	158580	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2411	0	0
T2	584076	8	0	0
T3	2080676	3	0	0
T4	515640	2	0	0
T5	407504	5	0	0
T7	0	1	0	0
T8	0	7	0	0
T14	0	17	0	0
T16	0	1	0	0
T17	240608	1	0	0
T18	135924	2	0	0
T19	785612	3	0	0
T20	134928	5	0	0
T21	839320	2	0	0
T22	317796	5	0	0
T23	0	5	0	0
T25	0	5	0	0
T28	0	4	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	113	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	305628	1	0	0
T6	71940	0	0	0
T7	708954	0	0	0
T8	1021569	1	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T17	180456	0	0	0
T18	101943	1	0	0
T19	589209	0	0	0
T20	101196	1	0	0
T21	629490	0	0	0
T22	238347	0	0	0
T23	112608	0	0	0
T25	27045	1	0	0
T28	135810	0	0	0
T33	0	3	0	0
T40	4610	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	4	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	178689	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1150	0	0
T2	292038	4	0	0
T3	1040338	1	0	0
T4	257820	0	0	0
T5	305628	3	0	0
T6	47960	0	0	0
T7	0	1	0	0
T8	681046	8	0	0
T14	0	12	0	0
T15	0	8	0	0
T17	180456	0	0	0
T18	135924	2	0	0
T19	785612	0	0	0
T20	134928	5	0	0
T21	839320	0	0	0
T22	317796	3	0	0
T23	75072	4	0	0
T25	27045	7	0	0
T27	0	14	0	0
T28	135810	4	0	0
T41	0	3	0	0
T42	0	10	0	0
T44	0	4	0	0
T47	0	3	0	0
T56	0	8	0	0
T57	0	1	0	0
T58	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1039516248	0	0
T1	347540	266056	0	0
T2	584076	570178	0	0
T3	2080676	535464	0	0
T4	515640	336248	0	0
T5	407504	1945908	0	0
T17	240608	187659	0	0
T18	135924	102333	0	0
T19	785612	201129	0	0
T20	134928	101556	0	0
T21	839320	413908	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2760	0	0
T1	86885	1	0	0
T2	584076	8	0	0
T3	2080676	4	0	0
T4	515640	2	0	0
T5	407504	8	0	0
T7	0	1	0	0
T8	0	8	0	0
T14	0	18	0	0
T17	240608	1	0	0
T18	135924	3	0	0
T19	785612	3	0	0
T20	134928	6	0	0
T21	839320	2	0	0
T22	238347	5	0	0
T23	0	5	0	0
T25	0	5	0	0
T28	0	5	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2690	0	0
T1	86885	1	0	0
T2	584076	8	0	0
T3	2080676	4	0	0
T4	515640	2	0	0
T5	407504	8	0	0
T7	0	1	0	0
T8	0	7	0	0
T14	0	18	0	0
T17	240608	1	0	0
T18	135924	3	0	0
T19	785612	3	0	0
T20	134928	4	0	0
T21	839320	2	0	0
T22	238347	5	0	0
T23	0	4	0	0
T25	0	5	0	0
T28	0	5	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2621	0	0
T1	86885	1	0	0
T2	584076	8	0	0
T3	2080676	4	0	0
T4	515640	2	0	0
T5	407504	8	0	0
T7	0	1	0	0
T8	0	7	0	0
T14	0	18	0	0
T17	240608	1	0	0
T18	135924	3	0	0
T19	785612	3	0	0
T20	134928	4	0	0
T21	839320	2	0	0
T22	238347	5	0	0
T23	0	4	0	0
T25	0	5	0	0
T28	0	5	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2576	0	0
T1	86885	1	0	0
T2	584076	8	0	0
T3	2080676	4	0	0
T4	515640	2	0	0
T5	407504	7	0	0
T7	0	1	0	0
T8	0	7	0	0
T14	0	18	0	0
T17	240608	1	0	0
T18	135924	3	0	0
T19	785612	3	0	0
T20	134928	4	0	0
T21	839320	2	0	0
T22	238347	5	0	0
T23	0	4	0	0
T25	0	5	0	0
T28	0	5	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5727	0	0
T1	86885	5	0	0
T3	1040338	2	0	0
T4	257820	0	0	0
T5	305628	5	0	0
T6	47960	0	0	0
T7	708954	0	0	0
T8	681046	6	0	0
T9	104893	0	0	0
T14	321024	3	0	0
T15	237784	0	0	0
T17	180456	0	0	0
T18	101943	1	0	0
T19	589209	0	0	0
T20	101196	1	0	0
T21	629490	0	0	0
T22	158898	0	0	0
T23	75072	0	0	0
T25	27045	6	0	0
T26	0	1	0	0
T28	135810	4	0	0
T40	4610	0	0	0
T41	0	46	0	0
T42	0	32	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	0	1	0	0
T55	178689	0	0	0
T59	0	36	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	524097	0	0
T1	86885	715	0	0
T3	1040338	151	0	0
T4	257820	0	0	0
T5	305628	80	0	0
T6	47960	0	0	0
T7	708954	0	0	0
T8	681046	673	0	0
T9	104893	0	0	0
T14	321024	104	0	0
T15	237784	0	0	0
T17	180456	0	0	0
T18	101943	0	0	0
T19	589209	0	0	0
T20	101196	1	0	0
T21	629490	0	0	0
T22	158898	0	0	0
T23	75072	0	0	0
T25	27045	495	0	0
T26	0	183	0	0
T28	135810	268	0	0
T40	4610	0	0	0
T41	0	10022	0	0
T42	0	6120	0	0
T44	0	72	0	0
T45	0	1	0	0
T46	0	2	0	0
T55	178689	0	0	0
T58	0	414	0	0
T59	0	7661	0	0
T60	0	372	0	0
T61	0	547	0	0
T62	0	52	0	0
T63	0	39	0	0
T64	0	200	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5327	0	0
T1	0	4	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T7	1417908	0	0	0
T8	0	4	0	0
T9	209786	0	0	0
T14	642048	1	0	0
T15	475568	0	0	0
T16	722286	0	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T24	0	1	0	0
T25	54090	5	0	0
T26	237458	1	0	0
T28	135810	3	0	0
T40	9220	0	0	0
T41	0	42	0	0
T42	0	24	0	0
T44	0	3	0	0
T47	0	1	0	0
T55	357378	0	0	0
T59	0	36	0	0
T61	0	5	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	4	0	0
T69	167869	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	283	0	0
T1	0	1	0	0
T5	0	2	0	0
T6	23980	0	0	0
T7	1417908	0	0	0
T8	340523	1	0	0
T9	209786	0	0	0
T14	642048	1	0	0
T15	475568	0	0	0
T25	54090	0	0	0
T26	118729	0	0	0
T28	271620	1	0	0
T40	9220	0	0	0
T41	730214	3	0	0
T42	525575	5	0	0
T43	19976	0	0	0
T47	0	4	0	0
T49	0	12	0	0
T50	0	1	0	0
T55	357378	0	0	0
T56	111214	0	0	0
T57	478583	0	0	0
T59	110239	0	0	0
T60	9224	1	0	0
T66	0	3	0	0
T68	0	3	0	0
T70	0	3	0	0
T71	0	5	0	0
T72	0	4	0	0
T73	0	10	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	7	0	0
T77	0	1	0	0
T78	165851	0	0	0
T79	3689	0	0	0
T80	47047	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3618	0	0
T11	82720	699	0	0
T12	0	777	0	0
T13	0	711	0	0
T29	0	697	0	0
T30	0	734	0	0
T31	419104	0	0	0
T32	1084552	0	0	0
T33	2324616	0	0	0
T34	48404	0	0	0
T35	12276	0	0	0
T36	10176	0	0	0
T37	67236	0	0	0
T38	207944	0	0	0
T39	158580	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3018	0	0
T11	82720	579	0	0
T12	0	657	0	0
T13	0	591	0	0
T29	0	577	0	0
T30	0	614	0	0
T31	419104	0	0	0
T32	1084552	0	0	0
T33	2324616	0	0	0
T34	48404	0	0	0
T35	12276	0	0	0
T36	10176	0	0	0
T37	67236	0	0	0
T38	207944	0	0	0
T39	158580	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	347540	347324	0	0
T2	584076	583944	0	0
T3	2080676	2080644	0	0
T4	515640	515608	0	0
T5	407504	407404	0	0
T17	240608	240396	0	0
T18	135924	135672	0	0
T19	785612	785256	0	0
T20	134928	134636	0	0
T21	839320	839016	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T17,T18
1	0	1	Covered	T5,T19,T21
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T5,T18,T20

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T5,T20,T8
0	1	Covered	T8,T14,T41
1	0	Covered	T5,T18,T20

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T5,T20,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T18,T20

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T18,T20
1	0	Not Covered
1	1	Covered	T8,T14,T41

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T17
1	Covered	T4,T5,T21

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T5,T17

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T20,T23,T8

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T18,T8

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T5,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T4,T5
Phase1St	193	Covered	T2,T4,T5
Phase2St	210	Covered	T2,T4,T5
Phase3St	228	Covered	T2,T4,T5
TerminalSt	244	Covered	T2,T4,T5
TimeoutSt	154	Covered	T5,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T4,T5
IdleSt->TimeoutSt	154	Covered	T5,T18,T20
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T61,T47
Phase0St->Phase1St	193	Covered	T2,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T20,T23,T25
Phase1St->Phase2St	210	Covered	T2,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T8,T28,T14
Phase2St->Phase3St	228	Covered	T2,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T14,T15,T41
Phase3St->TerminalSt	244	Covered	T2,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T5,T18
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T28,T26,T41
TimeoutSt->Phase0St	167	Covered	T5,T18,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T20,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T28,T26,T41
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T61,T47
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T23,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T28,T14
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T14,T15,T41
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T20,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	646783603	141	0	0
CheckAccumTrig0_A	646783603	897	0	0
CheckAccumTrig1_A	646783603	44	0	0
CheckClr_A	646783603	456	0	0
CheckEn_A	646651613	224139543	0	0
CheckPhase0_A	646783603	1006	0	0
CheckPhase1_A	646783603	982	0	0
CheckPhase2_A	646783603	953	0	0
CheckPhase3_A	646783603	935	0	0
CheckTimeout0_A	646783603	1472	0	0
CheckTimeoutSt1_A	646783603	132797	0	0
CheckTimeoutSt2_A	646783603	1343	0	0
CheckTimeoutStTrig_A	646783603	84	0	0
ErrorStAllEscAsserted_A	646783603	904	0	0
ErrorStIsTerminal_A	646783603	754	0	0
u_state_regs_A	646783603	646645797	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	141	0	0
T11	20680	28	0	0
T12	0	23	0	0
T13	0	36	0	0
T29	0	19	0	0
T30	0	35	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	897	0	0
T2	146019	2	0	0
T3	520169	0	0	0
T4	128910	1	0	0
T5	101876	2	0	0
T17	60152	1	0	0
T18	33981	2	0	0
T19	196403	1	0	0
T20	33732	5	0	0
T21	209830	1	0	0
T22	79449	1	0	0
T23	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	44	0	0
T5	101876	1	0	0
T6	23980	0	0	0
T8	340523	0	0	0
T17	60152	0	0	0
T18	33981	1	0	0
T19	196403	0	0	0
T20	33732	1	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T33	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T52	0	4	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	456	0	0
T6	23980	0	0	0
T7	0	1	0	0
T8	340523	2	0	0
T14	0	8	0	0
T15	0	5	0	0
T18	33981	2	0	0
T19	196403	0	0	0
T20	33732	5	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T23	37536	4	0	0
T25	27045	4	0	0
T28	135810	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646651613	224139543	0	0
T1	86885	86830	0	0
T2	146019	133402	0	0
T3	520169	520160	0	0
T4	128910	3045	0	0
T5	101876	5599	0	0
T17	60152	7365	0	0
T18	33981	582	0	0
T19	196403	1622	0	0
T20	33732	582	0	0
T21	209830	5418	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1006	0	0
T2	146019	2	0	0
T3	520169	0	0	0
T4	128910	1	0	0
T5	101876	3	0	0
T17	60152	1	0	0
T18	33981	3	0	0
T19	196403	1	0	0
T20	33732	6	0	0
T21	209830	1	0	0
T22	79449	1	0	0
T23	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	982	0	0
T2	146019	2	0	0
T3	520169	0	0	0
T4	128910	1	0	0
T5	101876	3	0	0
T17	60152	1	0	0
T18	33981	3	0	0
T19	196403	1	0	0
T20	33732	4	0	0
T21	209830	1	0	0
T22	79449	1	0	0
T23	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	953	0	0
T2	146019	2	0	0
T3	520169	0	0	0
T4	128910	1	0	0
T5	101876	3	0	0
T17	60152	1	0	0
T18	33981	3	0	0
T19	196403	1	0	0
T20	33732	4	0	0
T21	209830	1	0	0
T22	79449	1	0	0
T23	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	935	0	0
T2	146019	2	0	0
T3	520169	0	0	0
T4	128910	1	0	0
T5	101876	3	0	0
T17	60152	1	0	0
T18	33981	3	0	0
T19	196403	1	0	0
T20	33732	4	0	0
T21	209830	1	0	0
T22	79449	1	0	0
T23	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1472	0	0
T5	101876	1	0	0
T6	23980	0	0	0
T8	340523	1	0	0
T14	0	1	0	0
T17	60152	0	0	0
T18	33981	1	0	0
T19	196403	0	0	0
T20	33732	1	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T41	0	3	0	0
T42	0	6	0	0
T59	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	132797	0	0
T5	101876	1	0	0
T6	23980	0	0	0
T8	340523	18	0	0
T14	0	26	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	1	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T26	0	183	0	0
T28	0	110	0	0
T41	0	382	0	0
T42	0	993	0	0
T59	0	1916	0	0
T61	0	463	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1343	0	0
T7	708954	0	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T16	361143	0	0	0
T25	27045	0	0	0
T26	118729	1	0	0
T28	135810	1	0	0
T40	4610	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T44	0	1	0	0
T47	0	1	0	0
T55	178689	0	0	0
T59	0	9	0	0
T61	0	4	0	0
T65	0	2	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	84	0	0
T6	23980	0	0	0
T7	708954	0	0	0
T8	340523	1	0	0
T9	104893	0	0	0
T14	321024	1	0	0
T15	237784	0	0	0
T25	27045	0	0	0
T28	135810	0	0	0
T40	4610	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T55	178689	0	0	0
T66	0	3	0	0
T68	0	2	0	0
T70	0	1	0	0
T73	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	904	0	0
T11	20680	168	0	0
T12	0	187	0	0
T13	0	189	0	0
T29	0	168	0	0
T30	0	192	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	754	0	0
T11	20680	138	0	0
T12	0	157	0	0
T13	0	159	0	0
T29	0	138	0	0
T30	0	162	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	646645797	0	0
T1	86885	86831	0	0
T2	146019	145986	0	0
T3	520169	520161	0	0
T4	128910	128902	0	0
T5	101876	101851	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	196314	0	0
T20	33732	33659	0	0
T21	209830	209754	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T5
1	0	1	Covered	T4,T5,T19
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T3,T5,T8

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T8
0	1	Covered	T28,T60,T42
1	0	Covered	T3,T44,T47

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T44,T47

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Not Covered
1	1	Covered	T28,T60,T42

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T19
1	Covered	T2,T3,T5

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T22,T28

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T4,T19,T22

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T28,T14,T15

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T4
Phase1St	193	Covered	T2,T3,T4
Phase2St	210	Covered	T2,T3,T4
Phase3St	228	Covered	T2,T3,T4
TerminalSt	244	Covered	T2,T3,T4
TimeoutSt	154	Covered	T3,T5,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T3,T4
IdleSt->TimeoutSt	154	Covered	T3,T5,T8
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T25,T27,T81
Phase0St->Phase1St	193	Covered	T2,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T47,T49,T82
Phase1St->Phase2St	210	Covered	T2,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T41,T83,T73
Phase2St->Phase3St	228	Covered	T2,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T27,T84,T85
Phase3St->TerminalSt	244	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T3,T22
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T5,T8
TimeoutSt->Phase0St	167	Covered	T3,T28,T60

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T28,T60
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T27,T81
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T47,T49,T82
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T41,T83,T73
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T84,T85
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	646783603	169	0	0
CheckAccumTrig0_A	646783603	494	0	0
CheckAccumTrig1_A	646783603	16	0	0
CheckClr_A	646783603	215	0	0
CheckEn_A	646651613	257984250	0	0
CheckPhase0_A	646783603	566	0	0
CheckPhase1_A	646783603	556	0	0
CheckPhase2_A	646783603	544	0	0
CheckPhase3_A	646783603	536	0	0
CheckTimeout0_A	646783603	1553	0	0
CheckTimeoutSt1_A	646783603	151909	0	0
CheckTimeoutSt2_A	646783603	1466	0	0
CheckTimeoutStTrig_A	646783603	70	0	0
ErrorStAllEscAsserted_A	646783603	909	0	0
ErrorStIsTerminal_A	646783603	759	0	0
u_state_regs_A	646783603	646645797	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	169	0	0
T11	20680	53	0	0
T12	0	39	0	0
T13	0	31	0	0
T29	0	26	0	0
T30	0	20	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	494	0	0
T2	146019	3	0	0
T3	520169	1	0	0
T4	128910	1	0	0
T5	101876	1	0	0
T8	0	1	0	0
T14	0	6	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	2	0	0
T25	0	2	0	0
T28	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	16	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	0	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0
T91	0	4	0	0
T92	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	215	0	0
T2	146019	3	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	0	0	0
T14	0	2	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	1	0	0
T27	0	3	0	0
T28	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T56	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646651613	257984250	0	0
T1	86885	86830	0	0
T2	146019	145115	0	0
T3	520169	3071	0	0
T4	128910	91738	0	0
T5	101876	920424	0	0
T17	60152	60098	0	0
T18	33981	33917	0	0
T19	196403	2600	0	0
T20	33732	33658	0	0
T21	209830	209753	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	566	0	0
T2	146019	3	0	0
T3	520169	2	0	0
T4	128910	1	0	0
T5	101876	1	0	0
T8	0	1	0	0
T14	0	6	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	2	0	0
T25	0	1	0	0
T28	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	556	0	0
T2	146019	3	0	0
T3	520169	2	0	0
T4	128910	1	0	0
T5	101876	1	0	0
T8	0	1	0	0
T14	0	6	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	2	0	0
T25	0	1	0	0
T28	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	544	0	0
T2	146019	3	0	0
T3	520169	2	0	0
T4	128910	1	0	0
T5	101876	1	0	0
T8	0	1	0	0
T14	0	6	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	2	0	0
T25	0	1	0	0
T28	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	536	0	0
T2	146019	3	0	0
T3	520169	2	0	0
T4	128910	1	0	0
T5	101876	1	0	0
T8	0	1	0	0
T14	0	6	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	2	0	0
T25	0	1	0	0
T28	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1553	0	0
T3	520169	2	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	4	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T25	0	1	0	0
T28	0	3	0	0
T41	0	14	0	0
T42	0	10	0	0
T44	0	2	0	0
T59	0	6	0	0
T60	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	151909	0	0
T3	520169	151	0	0
T4	128910	0	0	0
T5	101876	37	0	0
T8	0	651	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T25	0	55	0	0
T28	0	158	0	0
T41	0	3257	0	0
T42	0	2107	0	0
T44	0	35	0	0
T59	0	1243	0	0
T60	0	372	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1466	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	4	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T25	0	1	0	0
T28	0	2	0	0
T41	0	14	0	0
T42	0	9	0	0
T44	0	1	0	0
T59	0	6	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	70	0	0
T7	708954	0	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T16	361143	0	0	0
T25	27045	0	0	0
T26	118729	0	0	0
T28	135810	1	0	0
T40	4610	0	0	0
T42	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T55	178689	0	0	0
T60	0	1	0	0
T70	0	1	0	0
T73	0	4	0	0
T75	0	2	0	0
T76	0	6	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	909	0	0
T11	20680	187	0	0
T12	0	195	0	0
T13	0	159	0	0
T29	0	175	0	0
T30	0	193	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	759	0	0
T11	20680	157	0	0
T12	0	165	0	0
T13	0	129	0	0
T29	0	145	0	0
T30	0	163	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	646645797	0	0
T1	86885	86831	0	0
T2	146019	145986	0	0
T3	520169	520161	0	0
T4	128910	128902	0	0
T5	101876	101851	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	196314	0	0
T20	33732	33659	0	0
T21	209830	209754	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T21
1	1	0	Covered	T1,T2,T8
1	1	1	Covered	T1,T5,T25

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T25
0	1	Covered	T1,T5,T42
1	0	Covered	T5,T14,T42

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T14,T42

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T25
1	0	Not Covered
1	1	Covered	T1,T5,T42

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T28,T25

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T2,T22,T14

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T3,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T14,T16

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T2,T3
Phase1St	193	Covered	T1,T2,T3
Phase2St	210	Covered	T1,T2,T3
Phase3St	228	Covered	T1,T2,T3
TerminalSt	244	Covered	T1,T2,T3
TimeoutSt	154	Covered	T1,T5,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T5,T25
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T5,T70,T93
Phase0St->Phase1St	193	Covered	T1,T2,T3
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T42,T94,T81
Phase1St->Phase2St	210	Covered	T1,T2,T3
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T70,T94,T95
Phase2St->Phase3St	228	Covered	T1,T2,T3
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T5,T42,T47
Phase3St->TerminalSt	244	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T5,T28
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T25,T14
TimeoutSt->Phase0St	167	Covered	T1,T5,T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T25,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T70,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T42,T94,T81
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T70,T94,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T42,T47
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T14,T42
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	646783603	169	0	0
CheckAccumTrig0_A	646783603	473	0	0
CheckAccumTrig1_A	646783603	28	0	0
CheckClr_A	646783603	203	0	0
CheckEn_A	646651613	295803653	0	0
CheckPhase0_A	646783603	558	0	0
CheckPhase1_A	646783603	547	0	0
CheckPhase2_A	646783603	540	0	0
CheckPhase3_A	646783603	532	0	0
CheckTimeout0_A	646783603	1258	0	0
CheckTimeoutSt1_A	646783603	104771	0	0
CheckTimeoutSt2_A	646783603	1166	0	0
CheckTimeoutStTrig_A	646783603	64	0	0
ErrorStAllEscAsserted_A	646783603	903	0	0
ErrorStIsTerminal_A	646783603	753	0	0
u_state_regs_A	646783603	646645797	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	169	0	0
T11	20680	21	0	0
T12	0	33	0	0
T13	0	37	0	0
T29	0	44	0	0
T30	0	34	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	473	0	0
T2	146019	1	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T7	0	1	0	0
T14	0	6	0	0
T16	0	1	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	1	0	0
T22	79449	1	0	0
T25	0	1	0	0
T28	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	28	0	0
T5	101876	2	0	0
T6	23980	0	0	0
T8	340523	0	0	0
T14	0	1	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T33	0	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T70	0	1	0	0
T77	0	1	0	0
T94	0	1	0	0
T96	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	203	0	0
T5	101876	3	0	0
T6	23980	0	0	0
T8	340523	0	0	0
T14	0	1	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	0	0	0
T23	37536	0	0	0
T42	0	9	0	0
T44	0	4	0	0
T47	0	3	0	0
T57	0	1	0	0
T58	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T70	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646651613	295803653	0	0
T1	86885	12307	0	0
T2	146019	145034	0	0
T3	520169	9173	0	0
T4	128910	112564	0	0
T5	101876	90494	0	0
T17	60152	60098	0	0
T18	33981	33917	0	0
T19	196403	196313	0	0
T20	33732	33658	0	0
T21	209830	5590	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	558	0	0
T1	86885	1	0	0
T2	146019	1	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	3	0	0
T7	0	1	0	0
T14	0	7	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	547	0	0
T1	86885	1	0	0
T2	146019	1	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	3	0	0
T7	0	1	0	0
T14	0	7	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	540	0	0
T1	86885	1	0	0
T2	146019	1	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	3	0	0
T7	0	1	0	0
T14	0	7	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	532	0	0
T1	86885	1	0	0
T2	146019	1	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	2	0	0
T7	0	1	0	0
T14	0	7	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	1	0	0
T22	0	1	0	0
T25	0	1	0	0
T28	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1258	0	0
T1	86885	5	0	0
T2	146019	0	0	0
T3	520169	0	0	0
T4	128910	0	0	0
T5	101876	3	0	0
T14	0	2	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T25	0	1	0	0
T41	0	23	0	0
T42	0	16	0	0
T44	0	1	0	0
T58	0	2	0	0
T59	0	9	0	0
T62	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	104771	0	0
T1	86885	715	0	0
T2	146019	0	0	0
T3	520169	0	0	0
T4	128910	0	0	0
T5	101876	42	0	0
T14	0	78	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T25	0	56	0	0
T41	0	5462	0	0
T42	0	3020	0	0
T47	0	53	0	0
T58	0	414	0	0
T59	0	1883	0	0
T62	0	52	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1166	0	0
T1	86885	4	0	0
T2	146019	0	0	0
T3	520169	0	0	0
T4	128910	0	0	0
T5	101876	0	0	0
T14	0	1	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T25	0	1	0	0
T41	0	23	0	0
T42	0	12	0	0
T58	0	2	0	0
T59	0	9	0	0
T62	0	1	0	0
T68	0	2	0	0
T70	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	64	0	0
T1	86885	1	0	0
T2	146019	0	0	0
T3	520169	0	0	0
T4	128910	0	0	0
T5	101876	2	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T33	0	2	0	0
T42	0	3	0	0
T47	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T76	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	903	0	0
T11	20680	171	0	0
T12	0	186	0	0
T13	0	186	0	0
T29	0	182	0	0
T30	0	178	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	753	0	0
T11	20680	141	0	0
T12	0	156	0	0
T13	0	156	0	0
T29	0	152	0	0
T30	0	148	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	646645797	0	0
T1	86885	86831	0	0
T2	146019	145986	0	0
T3	520169	520161	0	0
T4	128910	128902	0	0
T5	101876	101851	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	196314	0	0
T20	33732	33659	0	0
T21	209830	209754	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T19,T21,T14
1	1	0	Covered	T1,T5,T22
1	1	1	Covered	T8,T25,T41

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T41
0	1	Covered	T41,T47,T70
1	0	Covered	T8,T25,T41

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T8,T25,T41
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T25,T41

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T25,T41
1	0	Covered	T24
1	1	Covered	T41,T47,T70

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T8,T14,T40

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T5,T19
1	Covered	T3,T22,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T22
1	Covered	T2,T5,T19

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T2,T28,T25

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T19,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T14,T40,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T5
Phase1St	193	Covered	T2,T3,T5
Phase2St	210	Covered	T2,T3,T5
Phase3St	228	Covered	T2,T3,T5
TerminalSt	244	Covered	T2,T3,T5
TimeoutSt	154	Covered	T8,T25,T41

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T2,T3,T5
IdleSt->TimeoutSt	154	Covered	T8,T25,T41
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T56,T97,T82
Phase0St->Phase1St	193	Covered	T2,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T8,T27,T61
Phase1St->Phase2St	210	Covered	T2,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T56,T63,T72
Phase2St->Phase3St	228	Covered	T2,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T15,T63,T33
Phase3St->TerminalSt	244	Covered	T2,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T22,T8
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T25,T41,T59
TimeoutSt->Phase0St	167	Covered	T8,T25,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T41
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T8,T25,T41
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T25,T41,T59
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T56,T97,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T27,T61
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T56,T63,T72
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T63,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T22,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	646783603	182	0	0
CheckAccumTrig0_A	646783603	547	0	0
CheckAccumTrig1_A	646783603	25	0	0
CheckClr_A	646783603	276	0	0
CheckEn_A	646651613	261588802	0	0
CheckPhase0_A	646783603	630	0	0
CheckPhase1_A	646783603	605	0	0
CheckPhase2_A	646783603	584	0	0
CheckPhase3_A	646783603	573	0	0
CheckTimeout0_A	646783603	1444	0	0
CheckTimeoutSt1_A	646783603	134620	0	0
CheckTimeoutSt2_A	646783603	1352	0	0
CheckTimeoutStTrig_A	646783603	65	0	0
ErrorStAllEscAsserted_A	646783603	902	0	0
ErrorStIsTerminal_A	646783603	752	0	0
u_state_regs_A	646783603	646645797	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	182	0	0
T11	20680	38	0	0
T12	0	34	0	0
T13	0	31	0	0
T29	0	38	0	0
T30	0	41	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	547	0	0
T2	146019	2	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	6	0	0
T14	0	5	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	2	0	0
T28	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	25	0	0
T6	23980	0	0	0
T7	708954	0	0	0
T8	340523	1	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T25	27045	1	0	0
T28	135810	0	0	0
T40	4610	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	178689	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	276	0	0
T2	146019	1	0	0
T3	520169	0	0	0
T4	128910	0	0	0
T5	101876	0	0	0
T8	0	6	0	0
T14	0	1	0	0
T15	0	3	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	0	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	2	0	0
T27	0	11	0	0
T28	0	1	0	0
T41	0	1	0	0
T56	0	7	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646651613	261588802	0	0
T1	86885	80089	0	0
T2	146019	146627	0	0
T3	520169	3060	0	0
T4	128910	128901	0	0
T5	101876	929391	0	0
T17	60152	60098	0	0
T18	33981	33917	0	0
T19	196403	594	0	0
T20	33732	33658	0	0
T21	209830	193147	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	630	0	0
T2	146019	2	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	7	0	0
T14	0	5	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	3	0	0
T28	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	605	0	0
T2	146019	2	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	6	0	0
T14	0	5	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	3	0	0
T28	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	584	0	0
T2	146019	2	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	6	0	0
T14	0	5	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	3	0	0
T28	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	573	0	0
T2	146019	2	0	0
T3	520169	1	0	0
T4	128910	0	0	0
T5	101876	1	0	0
T8	0	6	0	0
T14	0	5	0	0
T17	60152	0	0	0
T18	33981	0	0	0
T19	196403	1	0	0
T20	33732	0	0	0
T21	209830	0	0	0
T22	79449	1	0	0
T25	0	3	0	0
T28	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1444	0	0
T6	23980	0	0	0
T7	708954	0	0	0
T8	340523	1	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T25	27045	4	0	0
T28	135810	0	0	0
T40	4610	0	0	0
T41	0	6	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T55	178689	0	0	0
T59	0	12	0	0
T61	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	134620	0	0
T6	23980	0	0	0
T7	708954	0	0	0
T8	340523	4	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T25	27045	384	0	0
T28	135810	0	0	0
T40	4610	0	0	0
T41	0	921	0	0
T44	0	37	0	0
T45	0	1	0	0
T46	0	2	0	0
T55	178689	0	0	0
T59	0	2619	0	0
T61	0	84	0	0
T63	0	39	0	0
T64	0	200	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	1352	0	0
T7	708954	0	0	0
T9	104893	0	0	0
T14	321024	0	0	0
T15	237784	0	0	0
T16	361143	0	0	0
T24	0	1	0	0
T25	27045	3	0	0
T26	118729	0	0	0
T40	4610	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T55	178689	0	0	0
T59	0	12	0	0
T61	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	167869	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	65	0	0
T41	730214	1	0	0
T42	525575	0	0	0
T43	19976	0	0	0
T47	0	1	0	0
T49	0	5	0	0
T56	111214	0	0	0
T57	478583	0	0	0
T59	110239	0	0	0
T60	9224	0	0	0
T68	0	1	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	4	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T78	165851	0	0	0
T79	3689	0	0	0
T80	47047	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	902	0	0
T11	20680	173	0	0
T12	0	209	0	0
T13	0	177	0	0
T29	0	172	0	0
T30	0	171	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	752	0	0
T11	20680	143	0	0
T12	0	179	0	0
T13	0	147	0	0
T29	0	142	0	0
T30	0	141	0	0
T31	104776	0	0	0
T32	271138	0	0	0
T33	581154	0	0	0
T34	12101	0	0	0
T35	3069	0	0	0
T36	2544	0	0	0
T37	16809	0	0	0
T38	51986	0	0	0
T39	39645	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	646783603	646645797	0	0
T1	86885	86831	0	0
T2	146019	145986	0	0
T3	520169	520161	0	0
T4	128910	128902	0	0
T5	101876	101851	0	0
T17	60152	60099	0	0
T18	33981	33918	0	0
T19	196403	196314	0	0
T20	33732	33659	0	0
T21	209830	209754	0	0