Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T209,T210,T77
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14562	0	0
DisabledNoTrigBkwd_A	2147483647	759934	0	0
DisabledNoTrigFwd_A	2147483647	1602991888	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14562	0	0
T11	15529	0	0	0
T30	107454	0	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T77	4407	902	0	0
T78	97319	0	0	0
T81	67489	0	0	0
T82	39111	0	0	0
T88	14303	0	0	0
T209	3607	490	0	0
T210	3347	894	0	0
T211	0	583	0	0
T212	0	666	0	0
T213	0	1067	0	0
T214	4943	1330	0	0
T215	0	113	0	0
T216	0	548	0	0
T217	0	340	0	0
T218	0	427	0	0
T219	0	990	0	0
T220	0	854	0	0
T221	0	888	0	0
T222	0	406	0	0
T223	0	768	0	0
T224	0	1036	0	0
T225	0	575	0	0
T226	0	605	0	0
T227	0	1080	0	0
T228	74922	0	0	0
T229	9536	0	0	0
T230	212143	0	0	0
T231	168802	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	759934	0	0
T1	136996	54	0	0
T2	3523256	0	0	0
T3	437296	62	0	0
T4	3724928	4	0	0
T5	545028	28	0	0
T6	2080812	3	0	0
T7	46764	0	0	0
T8	40712	3	0	0
T9	2748320	4	0	0
T10	239404	0	0	0
T17	0	504	0	0
T20	0	5971	0	0
T21	0	15	0	0
T22	0	4949	0	0
T23	0	384	0	0
T25	0	13	0	0
T26	0	14	0	0
T44	0	7268	0	0
T45	0	1	0	0
T46	0	7063	0	0
T47	0	72	0	0
T48	0	234	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1602991888	0	0
T1	136996	26130	0	0
T2	3523256	3522976	0	0
T3	437296	231894	0	0
T4	3724928	3722126	0	0
T5	545028	582362	0	0
T6	2080812	1318395	0	0
T7	46764	23885	0	0
T8	40712	31146	0	0
T9	2748320	1403534	0	0
T10	239404	229947	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T209,T210,T212
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	685210656	2904	0	0
DisabledNoTrigBkwd_A	685210656	232781	0	0
DisabledNoTrigFwd_A	685210656	368825656	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	2904	0	0
T30	107454	0	0	0
T81	67489	0	0	0
T82	39111	0	0	0
T88	14303	0	0	0
T209	3607	490	0	0
T210	3347	894	0	0
T212	0	666	0	0
T220	0	854	0	0
T228	74922	0	0	0
T229	9536	0	0	0
T230	212143	0	0	0
T231	168802	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	232781	0	0
T1	34249	10	0	0
T2	880814	0	0	0
T3	109324	23	0	0
T4	931232	0	0	0
T5	136257	2	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	3	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	9	0	0
T20	0	1408	0	0
T21	0	15	0	0
T22	0	2918	0	0
T23	0	146	0	0
T44	0	2789	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	368825656	0	0
T1	34249	12714	0	0
T2	880814	880744	0	0
T3	109324	10220	0	0
T4	931232	931159	0	0
T5	136257	582	0	0
T6	520203	275499	0	0
T7	11691	5979	0	0
T8	10178	774	0	0
T9	687080	432544	0	0
T10	59851	50586	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T211,T213
1	1	Covered	T1,T4,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	685210656	5694	0	0
DisabledNoTrigBkwd_A	685210656	178341	0	0
DisabledNoTrigFwd_A	685210656	393030659	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	5694	0	0
T11	15529	0	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T77	4407	902	0	0
T78	97319	0	0	0
T211	0	583	0	0
T213	0	1067	0	0
T221	0	888	0	0
T222	0	406	0	0
T223	0	768	0	0
T227	0	1080	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	178341	0	0
T1	34249	14	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	4	0	0
T10	59851	0	0	0
T17	0	4	0	0
T20	0	1063	0	0
T25	0	13	0	0
T26	0	12	0	0
T44	0	2585	0	0
T46	0	2355	0	0
T48	0	234	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	393030659	0	0
T1	34249	9176	0	0
T2	880814	880744	0	0
T3	109324	109240	0	0
T4	931232	929775	0	0
T5	136257	208248	0	0
T6	520203	520117	0	0
T7	11691	3147	0	0
T8	10178	10124	0	0
T9	687080	51565	0	0
T10	59851	59787	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T214,T216,T217
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	685210656	3250	0	0
DisabledNoTrigBkwd_A	685210656	156919	0	0
DisabledNoTrigFwd_A	685210656	427289060	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	3250	0	0
T55	106226	0	0	0
T214	4943	1330	0	0
T216	0	548	0	0
T217	0	340	0	0
T218	0	427	0	0
T226	0	605	0	0
T232	148602	0	0	0
T233	282606	0	0	0
T234	21204	0	0	0
T235	36981	0	0	0
T236	81939	0	0	0
T237	233519	0	0	0
T238	73167	0	0	0
T239	378401	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	156919	0	0
T1	34249	12	0	0
T2	880814	0	0	0
T3	109324	2	0	0
T4	931232	0	0	0
T5	136257	26	0	0
T6	520203	3	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	50	0	0
T20	0	1006	0	0
T22	0	2029	0	0
T26	0	2	0	0
T46	0	2942	0	0
T47	0	72	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	427289060	0	0
T1	34249	2111	0	0
T2	880814	880744	0	0
T3	109324	102137	0	0
T4	931232	931159	0	0
T5	136257	237282	0	0
T6	520203	2662	0	0
T7	11691	3166	0	0
T8	10178	10124	0	0
T9	687080	232403	0	0
T10	59851	59787	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T219,T224
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	685210656	2714	0	0
DisabledNoTrigBkwd_A	685210656	191893	0	0
DisabledNoTrigFwd_A	685210656	413846513	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	2714	0	0
T61	305521	0	0	0
T114	12313	0	0	0
T215	787	113	0	0
T219	0	990	0	0
T224	0	1036	0	0
T225	0	575	0	0
T240	88249	0	0	0
T241	39633	0	0	0
T242	880851	0	0	0
T243	61547	0	0	0
T244	322747	0	0	0
T245	407961	0	0	0
T246	11182	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	191893	0	0
T1	34249	18	0	0
T2	880814	0	0	0
T3	109324	37	0	0
T4	931232	3	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	441	0	0
T20	0	2494	0	0
T22	0	2	0	0
T23	0	238	0	0
T44	0	1894	0	0
T45	0	1	0	0
T46	0	1766	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	413846513	0	0
T1	34249	2129	0	0
T2	880814	880744	0	0
T3	109324	10297	0	0
T4	931232	930033	0	0
T5	136257	136250	0	0
T6	520203	520117	0	0
T7	11691	11593	0	0
T8	10178	10124	0	0
T9	687080	687022	0	0
T10	59851	59787	0	0