Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T5,T6,T9
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T1,T3,T7

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T17,T15

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T8
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T17,T15

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T15,T18,T19
1	1	Covered	T14,T15,T16

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T20,T17,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T22,T23

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T4
IdleSt->TimeoutSt	154	Covered	T1,T3,T7
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T1,T24,T25
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T26,T27,T28
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T29,T30,T31
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T22,T32,T31
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T4,T22,T20
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T3,T7,T8
TimeoutSt->Phase0St	167	Covered	T1,T17,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T24,T25
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T32,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T32,T31
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T22,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	963	0	0
CheckAccumTrig0_A	2147483647	2169	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1030	0	0
CheckEn_A	2147483647	1259094451	0	0
CheckPhase0_A	2147483647	2495	0	0
CheckPhase1_A	2147483647	2464	0	0
CheckPhase2_A	2147483647	2420	0	0
CheckPhase3_A	2147483647	2379	0	0
CheckTimeout0_A	2147483647	3126	0	0
CheckTimeoutSt1_A	2147483647	350263	0	0
CheckTimeoutSt2_A	2147483647	2743	0	0
CheckTimeoutStTrig_A	2147483647	253	0	0
ErrorStAllEscAsserted_A	2147483647	5113	0	0
ErrorStIsTerminal_A	2147483647	4273	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	963	0	0
T11	62116	130	0	0
T12	0	146	0	0
T13	0	133	0	0
T33	0	285	0	0
T34	0	269	0	0
T35	3767772	0	0	0
T36	2346828	0	0	0
T37	15108	0	0	0
T38	463368	0	0	0
T39	271008	0	0	0
T40	2739104	0	0	0
T41	217324	0	0	0
T42	300736	0	0	0
T43	1262768	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2169	0	0
T1	136996	6	0	0
T2	3523256	0	0	0
T3	437296	3	0	0
T4	3724928	2	0	0
T5	545028	2	0	0
T6	2080812	1	0	0
T7	46764	0	0	0
T8	40712	1	0	0
T9	2748320	1	0	0
T10	239404	0	0	0
T17	0	4	0	0
T20	0	23	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	2	0	0
T25	0	6	0	0
T26	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T1	34249	1	0	0
T11	15529	0	0	0
T15	380335	2	0	0
T17	0	1	0	0
T31	0	1	0	0
T32	625662	0	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T49	17647	1	0	0
T50	405346	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	4	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	123992	0	0	0
T67	389784	0	0	0
T68	61919	0	0	0
T69	70378	0	0	0
T70	47475	0	0	0
T71	11589	0	0	0
T72	369338	0	0	0
T73	3966	0	0	0
T74	164660	0	0	0
T75	410421	0	0	0
T76	39956	0	0	0
T77	4407	0	0	0
T78	97319	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1030	0	0
T1	102747	2	0	0
T2	2642442	0	0	0
T3	327972	0	0	0
T4	2793696	1	0	0
T5	408771	0	0	0
T6	1560609	0	0	0
T7	35073	0	0	0
T8	30534	0	0	0
T9	2061240	0	0	0
T10	179553	0	0	0
T15	0	5	0	0
T16	0	3	0	0
T17	38566	1	0	0
T20	361323	10	0	0
T21	17966	0	0	0
T22	502227	3	0	0
T23	506846	0	0	0
T24	7126	2	0	0
T25	0	4	0	0
T26	0	2	0	0
T29	0	1	0	0
T31	0	8	0	0
T32	0	5	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	1	0	0
T49	0	6	0	0
T50	0	7	0	0
T72	0	2	0	0
T79	0	1	0	0
T80	0	7	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	103430	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1259094451	0	0
T1	136996	8417	0	0
T2	3523256	3522972	0	0
T3	437296	132924	0	0
T4	3724928	3722122	0	0
T5	545028	345670	0	0
T6	2080812	1318393	0	0
T7	46764	23883	0	0
T8	40712	31143	0	0
T9	2748320	1403532	0	0
T10	239404	229943	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2495	0	0
T1	136996	4	0	0
T2	3523256	0	0	0
T3	437296	3	0	0
T4	3724928	2	0	0
T5	545028	2	0	0
T6	2080812	1	0	0
T7	46764	0	0	0
T8	40712	1	0	0
T9	2748320	1	0	0
T10	239404	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T20	0	27	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	2	0	0
T25	0	2	0	0
T26	0	4	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2464	0	0
T1	136996	4	0	0
T2	3523256	0	0	0
T3	437296	3	0	0
T4	3724928	2	0	0
T5	545028	2	0	0
T6	2080812	1	0	0
T7	46764	0	0	0
T8	40712	1	0	0
T9	2748320	1	0	0
T10	239404	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T20	0	27	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2420	0	0
T1	136996	4	0	0
T2	3523256	0	0	0
T3	437296	3	0	0
T4	3724928	2	0	0
T5	545028	2	0	0
T6	2080812	1	0	0
T7	46764	0	0	0
T8	40712	1	0	0
T9	2748320	1	0	0
T10	239404	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T20	0	27	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2379	0	0
T1	136996	4	0	0
T2	3523256	0	0	0
T3	437296	3	0	0
T4	3724928	2	0	0
T5	545028	2	0	0
T6	2080812	1	0	0
T7	46764	0	0	0
T8	40712	1	0	0
T9	2748320	1	0	0
T10	239404	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T20	0	27	0	0
T21	0	1	0	0
T22	0	5	0	0
T23	0	2	0	0
T25	0	2	0	0
T26	0	3	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	4	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3126	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	218648	2	0	0
T4	1862464	0	0	0
T5	272514	0	0	0
T6	1040406	0	0	0
T7	35073	2	0	0
T8	30534	1	0	0
T9	2061240	0	0	0
T10	179553	2	0	0
T14	0	11	0	0
T15	0	21	0	0
T16	0	1	0	0
T17	77132	3	0	0
T20	722646	14	0	0
T21	17966	0	0	0
T22	1004454	0	0	0
T23	506846	0	0	0
T24	7126	0	0	0
T25	0	5	0	0
T30	0	2	0	0
T31	0	16	0	0
T32	0	1	0	0
T44	676680	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T49	0	5	0	0
T66	0	3	0	0
T69	0	17	0	0
T80	0	7	0	0
T83	206860	0	0	0
T84	0	1	0	0
T85	0	3	0	0
T86	0	4	0	0
T87	22645	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	350263	0	0
T3	109324	207	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	23382	282	0	0
T8	20356	105	0	0
T9	1374160	0	0	0
T10	119702	188	0	0
T14	0	620	0	0
T15	0	4815	0	0
T16	0	3	0	0
T17	77132	389	0	0
T20	361323	655	0	0
T21	17966	0	0	0
T22	1004454	0	0	0
T23	506846	0	0	0
T24	7126	0	0	0
T25	0	219	0	0
T26	114552	0	0	0
T30	0	182	0	0
T31	0	1400	0	0
T32	0	2	0	0
T35	0	134	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T49	0	379	0	0
T66	0	240	0	0
T69	0	3061	0	0
T80	0	485	0	0
T83	206860	0	0	0
T84	7460	139	0	0
T85	0	511	0	0
T86	0	484	0	0
T87	22645	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2743	0	0
T3	109324	2	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	23382	2	0	0
T8	20356	1	0	0
T9	1374160	0	0	0
T10	119702	2	0	0
T14	27699	10	0	0
T15	0	6	0	0
T17	38566	1	0	0
T20	361323	10	0	0
T22	1004454	0	0	0
T23	506846	0	0	0
T25	108951	0	0	0
T26	114552	0	0	0
T30	0	2	0	0
T31	0	20	0	0
T35	0	1	0	0
T44	338340	0	0	0
T47	164225	0	0	0
T48	318204	0	0	0
T49	0	4	0	0
T66	0	2	0	0
T69	0	17	0	0
T80	0	5	0	0
T83	206860	0	0	0
T84	7460	1	0	0
T85	0	3	0	0
T86	0	2	0	0
T88	0	4	0	0
T89	0	128	0	0
T90	0	11	0	0
T91	572120	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253	0	0
T14	27699	1	0	0
T15	1141005	9	0	0
T16	0	1	0	0
T17	38566	0	0	0
T20	361323	0	0	0
T21	17966	0	0	0
T29	263716	0	0	0
T31	0	5	0	0
T32	1251324	0	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T48	318204	0	0	0
T49	35294	0	0	0
T50	0	2	0	0
T57	0	1	0	0
T66	371976	0	0	0
T67	1169352	0	0	0
T68	185757	0	0	0
T69	140756	0	0	0
T70	94950	0	0	0
T71	23178	0	0	0
T72	738676	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T85	210106	0	0	0
T86	0	1	0	0
T88	0	1	0	0
T89	0	3	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	3	0	0
T102	311598	0	0	0
T103	220831	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5113	0	0
T11	62116	771	0	0
T12	0	741	0	0
T13	0	696	0	0
T33	0	1477	0	0
T34	0	1428	0	0
T35	3767772	0	0	0
T36	2346828	0	0	0
T37	15108	0	0	0
T38	463368	0	0	0
T39	271008	0	0	0
T40	2739104	0	0	0
T41	217324	0	0	0
T42	300736	0	0	0
T43	1262768	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4273	0	0
T11	62116	651	0	0
T12	0	621	0	0
T13	0	576	0	0
T33	0	1237	0	0
T34	0	1188	0	0
T35	3767772	0	0	0
T36	2346828	0	0	0
T37	15108	0	0	0
T38	463368	0	0	0
T39	271008	0	0	0
T40	2739104	0	0	0
T41	217324	0	0	0
T42	300736	0	0	0
T43	1262768	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	136996	136612	0	0
T2	3523256	3522976	0	0
T3	437296	436960	0	0
T4	3724928	3724636	0	0
T5	545028	545000	0	0
T6	2080812	2080468	0	0
T7	46764	46372	0	0
T8	40712	40496	0	0
T9	2748320	2748088	0	0
T10	239404	239148	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T9

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T20
1	0	1	Covered	T9,T23,T20
1	1	0	Covered	T3,T4,T17
1	1	1	Covered	T7,T20,T14

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T20,T14
0	1	Covered	T14,T15,T16
1	0	Covered	T50,T52,T104

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T20,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T50,T52,T104

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T20,T14
1	0	Not Covered
1	1	Covered	T14,T15,T16

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T9,T20,T17
1	Covered	T1,T4,T44

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T20,T17,T26

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T9
1	Covered	T17,T46,T25

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T20
1	Covered	T9,T20,T25

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T9,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T9,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T4,T9
Phase1St	193	Covered	T1,T4,T9
Phase2St	210	Covered	T1,T4,T9
Phase3St	228	Covered	T1,T4,T9
TerminalSt	244	Covered	T1,T4,T9
TimeoutSt	154	Covered	T7,T20,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T4,T9
IdleSt->TimeoutSt	154	Covered	T7,T20,T14
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T1,T63,T105
Phase0St->Phase1St	193	Covered	T1,T4,T9
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T26,T27,T28
Phase1St->Phase2St	210	Covered	T1,T4,T9
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T29,T27,T61
Phase2St->Phase3St	228	Covered	T1,T4,T9
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T61,T106,T107
Phase3St->TerminalSt	244	Covered	T1,T4,T9
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T20,T17
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T7,T20,T14
TimeoutSt->Phase0St	167	Covered	T14,T15,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T20,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T20,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T7,T20,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T63,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T27,T61
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T61,T106,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T20,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	685210656	199	0	0
CheckAccumTrig0_A	685210656	482	0	0
CheckAccumTrig1_A	685210656	29	0	0
CheckClr_A	685210656	238	0	0
CheckEn_A	685076009	322611192	0	0
CheckPhase0_A	685210656	568	0	0
CheckPhase1_A	685210656	557	0	0
CheckPhase2_A	685210656	545	0	0
CheckPhase3_A	685210656	541	0	0
CheckTimeout0_A	685210656	880	0	0
CheckTimeoutSt1_A	685210656	94125	0	0
CheckTimeoutSt2_A	685210656	781	0	0
CheckTimeoutStTrig_A	685210656	68	0	0
ErrorStAllEscAsserted_A	685210656	1295	0	0
ErrorStIsTerminal_A	685210656	1085	0	0
u_state_regs_A	685210656	685050575	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	199	0	0
T11	15529	22	0	0
T12	0	41	0	0
T13	0	29	0	0
T33	0	44	0	0
T34	0	63	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	482	0	0
T1	34249	2	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	1	0	0
T10	59851	0	0	0
T17	0	2	0	0
T20	0	8	0	0
T25	0	2	0	0
T26	0	2	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	29	0	0
T11	15529	0	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T50	405346	2	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T61	0	4	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T73	3966	0	0	0
T74	164660	0	0	0
T75	410421	0	0	0
T76	39956	0	0	0
T77	4407	0	0	0
T78	97319	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	238	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T16	0	3	0	0
T17	0	1	0	0
T20	0	5	0	0
T25	0	1	0	0
T26	0	1	0	0
T29	0	1	0	0
T46	0	1	0	0
T49	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685076009	322611192	0	0
T1	34249	2095	0	0
T2	880814	880743	0	0
T3	109324	109239	0	0
T4	931232	929774	0	0
T5	136257	208248	0	0
T6	520203	520116	0	0
T7	11691	3147	0	0
T8	10178	10123	0	0
T9	687080	51565	0	0
T10	59851	59786	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	568	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	1	0	0
T10	59851	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T20	0	8	0	0
T25	0	2	0	0
T26	0	2	0	0
T44	0	1	0	0
T46	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	557	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	1	0	0
T10	59851	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T20	0	8	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	545	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	1	0	0
T10	59851	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T20	0	8	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	541	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	1	0	0
T10	59851	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T20	0	8	0	0
T25	0	2	0	0
T26	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	880	0	0
T7	11691	1	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T14	0	2	0	0
T15	0	4	0	0
T16	0	1	0	0
T17	38566	0	0	0
T20	361323	3	0	0
T22	502227	0	0	0
T23	506846	0	0	0
T44	338340	0	0	0
T49	0	1	0	0
T66	0	1	0	0
T80	0	1	0	0
T83	103430	0	0	0
T85	0	3	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	94125	0	0
T7	11691	146	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T14	0	75	0	0
T15	0	1150	0	0
T16	0	3	0	0
T17	38566	0	0	0
T20	361323	72	0	0
T22	502227	0	0	0
T23	506846	0	0	0
T44	338340	0	0	0
T49	0	87	0	0
T66	0	117	0	0
T80	0	313	0	0
T83	103430	0	0	0
T85	0	511	0	0
T86	0	182	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	781	0	0
T7	11691	1	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	38566	0	0	0
T20	361323	3	0	0
T22	502227	0	0	0
T23	506846	0	0	0
T30	0	1	0	0
T44	338340	0	0	0
T49	0	1	0	0
T66	0	1	0	0
T83	103430	0	0	0
T85	0	3	0	0
T86	0	1	0	0
T88	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	68	0	0
T14	27699	1	0	0
T15	380335	3	0	0
T16	0	1	0	0
T29	263716	0	0	0
T31	0	2	0	0
T48	318204	0	0	0
T57	0	1	0	0
T66	123992	0	0	0
T67	389784	0	0	0
T68	61919	0	0	0
T80	0	1	0	0
T85	210106	0	0	0
T92	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T99	0	1	0	0
T102	311598	0	0	0
T103	220831	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1295	0	0
T11	15529	206	0	0
T12	0	205	0	0
T13	0	143	0	0
T33	0	376	0	0
T34	0	365	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1085	0	0
T11	15529	176	0	0
T12	0	175	0	0
T13	0	113	0	0
T33	0	316	0	0
T34	0	305	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	685050575	0	0
T1	34249	34153	0	0
T2	880814	880744	0	0
T3	109324	109240	0	0
T4	931232	931159	0	0
T5	136257	136250	0	0
T6	520203	520117	0	0
T7	11691	11593	0	0
T8	10178	10124	0	0
T9	687080	687022	0	0
T10	59851	59787	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T5,T6,T22
1	1	0	Covered	T4,T20,T17
1	1	1	Covered	T1,T17,T84

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T84,T14
0	1	Covered	T15,T93,T89
1	0	Covered	T1,T17,T15

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T84,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T17,T15

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T84
1	0	Not Covered
1	1	Covered	T15,T93,T89

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T22,T20
1	Covered	T1,T3,T5

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T20,T47,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T6,T22,T26

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T17,T46,T103

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T6,T20

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T1,T17,T84

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T17,T84
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T1,T25,T108
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T109,T105,T110
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T30,T65,T111
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T22,T32,T107
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T20,T26,T25
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T84,T14,T15
TimeoutSt->Phase0St	167	Covered	T1,T17,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T84
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T84,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T84,T14,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T25,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T109,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T65,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T32,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T26,T25,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	685210656	253	0	0
CheckAccumTrig0_A	685210656	428	0	0
CheckAccumTrig1_A	685210656	27	0	0
CheckClr_A	685210656	180	0	0
CheckEn_A	685076009	345705159	0	0
CheckPhase0_A	685210656	498	0	0
CheckPhase1_A	685210656	495	0	0
CheckPhase2_A	685210656	490	0	0
CheckPhase3_A	685210656	483	0	0
CheckTimeout0_A	685210656	821	0	0
CheckTimeoutSt1_A	685210656	106889	0	0
CheckTimeoutSt2_A	685210656	740	0	0
CheckTimeoutStTrig_A	685210656	54	0	0
ErrorStAllEscAsserted_A	685210656	1236	0	0
ErrorStIsTerminal_A	685210656	1026	0	0
u_state_regs_A	685210656	685050575	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	253	0	0
T11	15529	32	0	0
T12	0	41	0	0
T13	0	27	0	0
T33	0	90	0	0
T34	0	63	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	428	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	1	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T20	0	4	0	0
T22	0	2	0	0
T25	0	4	0	0
T26	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	27	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T32	0	1	0	0
T55	0	1	0	0
T96	0	1	0	0
T101	0	1	0	0
T104	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	180	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T15	0	2	0	0
T22	0	1	0	0
T25	0	3	0	0
T26	0	1	0	0
T32	0	3	0	0
T72	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685076009	345705159	0	0
T1	34249	2111	0	0
T2	880814	880743	0	0
T3	109324	3168	0	0
T4	931232	931158	0	0
T5	136257	590	0	0
T6	520203	2662	0	0
T7	11691	3166	0	0
T8	10178	10123	0	0
T9	687080	232403	0	0
T10	59851	59786	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	498	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	1	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	4	0	0
T22	0	2	0	0
T26	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	495	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	1	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	4	0	0
T22	0	2	0	0
T26	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	490	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	1	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	4	0	0
T22	0	2	0	0
T26	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	483	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	1	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	4	0	0
T22	0	1	0	0
T26	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	821	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T14	0	7	0	0
T15	0	7	0	0
T17	0	1	0	0
T31	0	16	0	0
T32	0	1	0	0
T66	0	1	0	0
T69	0	11	0	0
T84	0	1	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	106889	0	0
T14	0	413	0	0
T15	0	2020	0	0
T17	38566	1	0	0
T21	17966	0	0	0
T24	7126	0	0	0
T26	114552	0	0	0
T31	0	1400	0	0
T32	0	2	0	0
T35	0	134	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T47	164225	0	0	0
T66	0	95	0	0
T69	0	1976	0	0
T84	7460	139	0	0
T86	0	156	0	0
T87	22645	0	0	0
T91	572120	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	740	0	0
T14	27699	7	0	0
T15	0	2	0	0
T25	108951	0	0	0
T26	114552	0	0	0
T29	263716	0	0	0
T31	0	16	0	0
T35	0	1	0	0
T47	164225	0	0	0
T48	318204	0	0	0
T66	0	1	0	0
T69	0	11	0	0
T84	7460	1	0	0
T86	0	1	0	0
T89	0	128	0	0
T90	0	11	0	0
T91	572120	0	0	0
T102	311598	0	0	0
T103	220831	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	54	0	0
T15	380335	4	0	0
T32	625662	0	0	0
T49	17647	0	0	0
T66	123992	0	0	0
T67	389784	0	0	0
T68	61919	0	0	0
T69	70378	0	0	0
T70	47475	0	0	0
T71	11589	0	0	0
T72	369338	0	0	0
T89	0	3	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T100	0	1	0	0
T101	0	3	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1236	0	0
T11	15529	166	0	0
T12	0	184	0	0
T13	0	169	0	0
T33	0	375	0	0
T34	0	342	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1026	0	0
T11	15529	136	0	0
T12	0	154	0	0
T13	0	139	0	0
T33	0	315	0	0
T34	0	282	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	685050575	0	0
T1	34249	34153	0	0
T2	880814	880744	0	0
T3	109324	109240	0	0
T4	931232	931159	0	0
T5	136257	136250	0	0
T6	520203	520117	0	0
T7	11691	11593	0	0
T8	10178	10124	0	0
T9	687080	687022	0	0
T10	59851	59787	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T7
1	0	1	Covered	T5,T6,T9
1	1	0	Covered	T3,T4,T7
1	1	1	Covered	T3,T7,T8

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T15,T86,T81
1	0	Covered	T15,T49,T31

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T7,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T49,T31

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T19
1	1	Covered	T15,T86,T81

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T22,T67,T70

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T20,T17,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T23,T20,T24

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T22,T23,T20
1	Covered	T1,T3,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T8,T20,T44

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T5,T8,T44

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T3,T7,T8
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T15,T118
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T105,T119,T120
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T31,T121,T122
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T31,T50,T89
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T22,T20,T24
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T3,T7,T8
TimeoutSt->Phase0St	167	Covered	T15,T49,T86

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T49,T86
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T15,T63
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T105,T119,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T121,T122
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T50,T89
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T22,T20,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	685210656	221	0	0
CheckAccumTrig0_A	685210656	818	0	0
CheckAccumTrig1_A	685210656	45	0	0
CheckClr_A	685210656	415	0	0
CheckEn_A	685076009	275600842	0	0
CheckPhase0_A	685210656	911	0	0
CheckPhase1_A	685210656	898	0	0
CheckPhase2_A	685210656	877	0	0
CheckPhase3_A	685210656	858	0	0
CheckTimeout0_A	685210656	644	0	0
CheckTimeoutSt1_A	685210656	67349	0	0
CheckTimeoutSt2_A	685210656	529	0	0
CheckTimeoutStTrig_A	685210656	70	0	0
ErrorStAllEscAsserted_A	685210656	1267	0	0
ErrorStIsTerminal_A	685210656	1057	0	0
u_state_regs_A	685210656	685050575	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	221	0	0
T11	15529	28	0	0
T12	0	31	0	0
T13	0	34	0	0
T33	0	69	0	0
T34	0	59	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	818	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	8	0	0
T21	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	45	0	0
T15	380335	1	0	0
T31	0	1	0	0
T32	625662	0	0	0
T49	17647	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T64	0	2	0	0
T66	123992	0	0	0
T67	389784	0	0	0
T68	61919	0	0	0
T69	70378	0	0	0
T70	47475	0	0	0
T71	11589	0	0	0
T72	369338	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	415	0	0
T15	0	3	0	0
T17	38566	0	0	0
T20	361323	5	0	0
T21	17966	0	0	0
T22	502227	2	0	0
T23	506846	0	0	0
T24	7126	2	0	0
T31	0	8	0	0
T32	0	2	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T49	0	3	0	0
T50	0	7	0	0
T80	0	6	0	0
T82	0	1	0	0
T83	103430	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685076009	275600842	0	0
T1	34249	2082	0	0
T2	880814	880743	0	0
T3	109324	10220	0	0
T4	931232	931158	0	0
T5	136257	582	0	0
T6	520203	275499	0	0
T7	11691	5978	0	0
T8	10178	774	0	0
T9	687080	432543	0	0
T10	59851	50585	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	911	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	8	0	0
T21	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	898	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	8	0	0
T21	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	877	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	8	0	0
T21	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	858	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	0	0	0
T5	136257	1	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	8	0	0
T21	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	644	0	0
T3	109324	2	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	1	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	2	0	0
T14	0	1	0	0
T15	0	5	0	0
T20	0	2	0	0
T22	502227	0	0	0
T49	0	4	0	0
T80	0	4	0	0
T83	103430	0	0	0
T86	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	67349	0	0
T3	109324	207	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	136	0	0
T8	10178	105	0	0
T9	687080	0	0	0
T10	59851	188	0	0
T14	0	67	0	0
T15	0	1050	0	0
T20	0	183	0	0
T22	502227	0	0	0
T49	0	292	0	0
T80	0	60	0	0
T83	103430	0	0	0
T86	0	99	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	529	0	0
T3	109324	2	0	0
T4	931232	0	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	1	0	0
T8	10178	1	0	0
T9	687080	0	0	0
T10	59851	2	0	0
T14	0	1	0	0
T15	0	2	0	0
T20	0	2	0	0
T22	502227	0	0	0
T49	0	3	0	0
T80	0	4	0	0
T83	103430	0	0	0
T88	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	70	0	0
T15	380335	2	0	0
T31	0	3	0	0
T32	625662	0	0	0
T49	17647	0	0	0
T50	0	2	0	0
T66	123992	0	0	0
T67	389784	0	0	0
T68	61919	0	0	0
T69	70378	0	0	0
T70	47475	0	0	0
T71	11589	0	0	0
T72	369338	0	0	0
T81	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T94	0	1	0	0
T98	0	2	0	0
T99	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1267	0	0
T11	15529	203	0	0
T12	0	150	0	0
T13	0	200	0	0
T33	0	366	0	0
T34	0	348	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1057	0	0
T11	15529	173	0	0
T12	0	120	0	0
T13	0	170	0	0
T33	0	306	0	0
T34	0	288	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	685050575	0	0
T1	34249	34153	0	0
T2	880814	880744	0	0
T3	109324	109240	0	0
T4	931232	931159	0	0
T5	136257	136250	0	0
T6	520203	520117	0	0
T7	11691	11593	0	0
T8	10178	10124	0	0
T9	687080	687022	0	0
T10	59851	59787	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T22,T83,T23
1	1	0	Covered	T4,T7,T20
1	1	1	Covered	T20,T17,T25

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T17,T25
0	1	Covered	T20,T17,T15
1	0	Covered	T25,T66,T80

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T17,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T66,T80

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T17,T25
1	0	Covered	T15,T18
1	1	Covered	T20,T17,T15

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T23,T20,T44

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T17,T25,T49

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T3,T25,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T23,T20
1	Covered	T1,T4,T22

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T23,T20,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T22,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T4
Phase1St	193	Covered	T1,T3,T4
Phase2St	210	Covered	T1,T3,T4
Phase3St	228	Covered	T1,T3,T4
TerminalSt	244	Covered	T1,T3,T4
TimeoutSt	154	Covered	T20,T17,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T4
IdleSt->TimeoutSt	154	Covered	T20,T17,T25
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T1,T123,T124
Phase0St->Phase1St	193	Covered	T1,T3,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T15,T32,T125
Phase1St->Phase2St	210	Covered	T1,T3,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T15,T30,T126
Phase2St->Phase3St	228	Covered	T1,T3,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T65,T127,T123
Phase3St->TerminalSt	244	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T22,T20
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T20,T17,T25
TimeoutSt->Phase0St	167	Covered	T20,T17,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T17,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T17,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T17,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T17,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T123,T124
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T125,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T15,T30,T126
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T65,T127,T123
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T22,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	685210656	290	0	0
CheckAccumTrig0_A	685210656	441	0	0
CheckAccumTrig1_A	685210656	24	0	0
CheckClr_A	685210656	197	0	0
CheckEn_A	685076009	315177258	0	0
CheckPhase0_A	685210656	518	0	0
CheckPhase1_A	685210656	514	0	0
CheckPhase2_A	685210656	508	0	0
CheckPhase3_A	685210656	497	0	0
CheckTimeout0_A	685210656	781	0	0
CheckTimeoutSt1_A	685210656	81900	0	0
CheckTimeoutSt2_A	685210656	693	0	0
CheckTimeoutStTrig_A	685210656	61	0	0
ErrorStAllEscAsserted_A	685210656	1315	0	0
ErrorStIsTerminal_A	685210656	1105	0	0
u_state_regs_A	685210656	685050575	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	290	0	0
T11	15529	48	0	0
T12	0	33	0	0
T13	0	43	0	0
T33	0	82	0	0
T34	0	84	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	441	0	0
T1	34249	2	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	1	0	0
T20	0	3	0	0
T22	0	1	0	0
T23	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	24	0	0
T14	27699	0	0	0
T15	380335	0	0	0
T25	108951	1	0	0
T29	263716	0	0	0
T30	0	1	0	0
T48	318204	0	0	0
T50	0	2	0	0
T61	0	1	0	0
T66	123992	1	0	0
T67	389784	0	0	0
T80	0	1	0	0
T85	210106	0	0	0
T95	0	1	0	0
T102	311598	0	0	0
T103	220831	0	0	0
T128	0	2	0	0
T129	0	2	0	0
T130	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	197	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	0	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T15	0	4	0	0
T17	0	1	0	0
T20	0	4	0	0
T22	0	1	0	0
T25	0	2	0	0
T32	0	2	0	0
T45	0	1	0	0
T49	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685076009	315177258	0	0
T1	34249	2129	0	0
T2	880814	880743	0	0
T3	109324	10297	0	0
T4	931232	930032	0	0
T5	136257	136250	0	0
T6	520203	520116	0	0
T7	11691	11592	0	0
T8	10178	10123	0	0
T9	687080	687021	0	0
T10	59851	59786	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	518	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	2	0	0
T20	0	7	0	0
T22	0	1	0	0
T23	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	514	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	2	0	0
T20	0	7	0	0
T22	0	1	0	0
T23	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	508	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	2	0	0
T20	0	7	0	0
T22	0	1	0	0
T23	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	497	0	0
T1	34249	1	0	0
T2	880814	0	0	0
T3	109324	1	0	0
T4	931232	1	0	0
T5	136257	0	0	0
T6	520203	0	0	0
T7	11691	0	0	0
T8	10178	0	0	0
T9	687080	0	0	0
T10	59851	0	0	0
T17	0	2	0	0
T20	0	7	0	0
T22	0	1	0	0
T23	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	781	0	0
T14	0	1	0	0
T15	0	5	0	0
T17	38566	2	0	0
T20	361323	9	0	0
T21	17966	0	0	0
T24	7126	0	0	0
T25	0	5	0	0
T26	114552	0	0	0
T30	0	2	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T66	0	1	0	0
T69	0	6	0	0
T80	0	2	0	0
T84	7460	0	0	0
T86	0	1	0	0
T87	22645	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	81900	0	0
T14	0	65	0	0
T15	0	595	0	0
T17	38566	388	0	0
T20	361323	400	0	0
T21	17966	0	0	0
T24	7126	0	0	0
T25	0	219	0	0
T26	114552	0	0	0
T30	0	182	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T66	0	28	0	0
T69	0	1085	0	0
T80	0	112	0	0
T84	7460	0	0	0
T86	0	47	0	0
T87	22645	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	693	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	38566	1	0	0
T20	361323	5	0	0
T21	17966	0	0	0
T24	7126	0	0	0
T25	0	4	0	0
T26	114552	0	0	0
T30	0	1	0	0
T31	0	4	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T50	0	4	0	0
T69	0	6	0	0
T80	0	1	0	0
T84	7460	0	0	0
T87	22645	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	61	0	0
T15	0	4	0	0
T17	38566	1	0	0
T20	361323	4	0	0
T21	17966	0	0	0
T24	7126	0	0	0
T26	114552	0	0	0
T31	0	2	0	0
T42	0	1	0	0
T44	338340	0	0	0
T45	20782	0	0	0
T46	439490	0	0	0
T84	7460	0	0	0
T86	0	1	0	0
T87	22645	0	0	0
T89	0	2	0	0
T92	0	1	0	0
T118	0	1	0	0
T131	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1315	0	0
T11	15529	196	0	0
T12	0	202	0	0
T13	0	184	0	0
T33	0	360	0	0
T34	0	373	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	1105	0	0
T11	15529	166	0	0
T12	0	172	0	0
T13	0	154	0	0
T33	0	300	0	0
T34	0	313	0	0
T35	941943	0	0	0
T36	586707	0	0	0
T37	3777	0	0	0
T38	115842	0	0	0
T39	67752	0	0	0
T40	684776	0	0	0
T41	54331	0	0	0
T42	75184	0	0	0
T43	315692	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	685210656	685050575	0	0
T1	34249	34153	0	0
T2	880814	880744	0	0
T3	109324	109240	0	0
T4	931232	931159	0	0
T5	136257	136250	0	0
T6	520203	520117	0	0
T7	11691	11593	0	0
T8	10178	10124	0	0
T9	687080	687022	0	0
T10	59851	59787	0	0