Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61727444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29898257

1

T1

127415

T2

122

T3

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14129426	1			T1	51262		T2	73		T3	21
values[0x0]	37877457	1			T1	175256		T2	191		T3	161
values[0x1]	39618818	1			T1	175686		T2	189		T3	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52795133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38830568

1

T1

161364

T2

167

T3

123

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	289200	1			T5	129		T4	974		T20	19
valid_sources[0x01]	301493	1			T5	171		T4	1158		T20	18
valid_sources[0x02]	294110	1			T5	127		T4	1255		T20	14
valid_sources[0x03]	288763	1			T5	201		T4	1217		T20	16
valid_sources[0x04]	293559	1			T5	222		T4	1151		T20	13
valid_sources[0x05]	289596	1			T5	212		T4	1223		T20	19
valid_sources[0x06]	295909	1			T2	155		T5	148		T4	1340
valid_sources[0x07]	677922	1			T5	163		T4	1094		T20	14
valid_sources[0x08]	284836	1			T2	12		T5	176		T4	1112
valid_sources[0x09]	303627	1			T5	144		T4	1228		T20	17
valid_sources[0x0a]	291004	1			T5	167		T4	998		T20	18
valid_sources[0x0b]	287420	1			T5	184		T4	1073		T20	30
valid_sources[0x0c]	289901	1			T5	234		T4	1196		T20	16
valid_sources[0x0d]	289284	1			T5	262		T4	1153		T20	15
valid_sources[0x0e]	334605	1			T5	150		T4	1078		T20	22
valid_sources[0x0f]	283377	1			T5	266		T4	1183		T20	21
valid_sources[0x10]	286018	1			T5	172		T4	1203		T20	15
valid_sources[0x11]	529369	1			T5	111		T4	1018		T20	16
valid_sources[0x12]	290851	1			T5	125		T4	1184		T20	12
valid_sources[0x13]	285910	1			T5	222		T4	1183		T20	15
valid_sources[0x14]	287126	1			T5	113		T4	1126		T20	15
valid_sources[0x15]	312701	1			T5	210		T4	1174		T20	12
valid_sources[0x16]	283088	1			T5	221		T4	1136		T20	19
valid_sources[0x17]	288658	1			T5	158		T4	1176		T20	19
valid_sources[0x18]	287478	1			T5	149		T4	1221		T20	23
valid_sources[0x19]	292408	1			T5	144		T4	1211		T20	14
valid_sources[0x1a]	289894	1			T5	191		T4	1208		T20	10
valid_sources[0x1b]	286744	1			T5	181		T4	1151		T20	8
valid_sources[0x1c]	289273	1			T5	175		T4	1019		T20	25
valid_sources[0x1d]	288203	1			T5	80		T4	1099		T20	18
valid_sources[0x1e]	287268	1			T5	159		T4	1079		T20	14
valid_sources[0x1f]	501120	1			T5	140		T4	1104		T20	15
valid_sources[0x20]	289057	1			T5	150		T4	1172		T20	18
valid_sources[0x21]	298096	1			T5	142		T4	1194		T20	20
valid_sources[0x22]	324572	1			T5	229		T4	1084		T20	24
valid_sources[0x23]	288002	1			T5	152		T4	1132		T20	15
valid_sources[0x24]	283547	1			T5	170		T4	1177		T20	17
valid_sources[0x25]	548257	1			T5	135		T4	1188		T20	18
valid_sources[0x26]	298368	1			T5	147		T4	1147		T20	15
valid_sources[0x27]	294050	1			T5	146		T4	1142		T20	12
valid_sources[0x28]	287638	1			T5	151		T4	882		T20	15
valid_sources[0x29]	666562	1			T3	338		T5	187		T4	1211
valid_sources[0x2a]	287796	1			T5	131		T4	1103		T20	13
valid_sources[0x2b]	327945	1			T5	162		T4	961		T20	19
valid_sources[0x2c]	888325	1			T5	141		T4	999		T20	18
valid_sources[0x2d]	289797	1			T5	197		T4	1120		T20	18
valid_sources[0x2e]	293396	1			T5	136		T4	1273		T20	23
valid_sources[0x2f]	747938	1			T5	129		T4	1071		T20	22
valid_sources[0x30]	692494	1			T5	216		T4	1073		T20	17
valid_sources[0x31]	288847	1			T5	75		T4	1111		T20	14
valid_sources[0x32]	991482	1			T5	140		T4	1145		T20	9
valid_sources[0x33]	295812	1			T5	225		T4	1119		T20	19
valid_sources[0x34]	1159320	1			T5	113		T4	1105		T20	14
valid_sources[0x35]	597993	1			T5	193		T4	1168		T20	14
valid_sources[0x36]	287674	1			T5	246		T4	1075		T20	18
valid_sources[0x37]	689339	1			T1	402204		T5	155		T4	1133
valid_sources[0x38]	294339	1			T5	161		T4	1111		T20	15
valid_sources[0x39]	282919	1			T5	164		T4	1174		T20	22
valid_sources[0x3a]	283012	1			T5	115		T4	1208		T20	15
valid_sources[0x3b]	562495	1			T5	117		T4	913		T20	16
valid_sources[0x3c]	293162	1			T5	176		T4	1147		T20	21
valid_sources[0x3d]	291028	1			T5	135		T4	1132		T20	25
valid_sources[0x3e]	290267	1			T5	164		T4	1202		T20	17
valid_sources[0x3f]	567384	1			T5	173		T4	1204		T20	17
valid_sources[0x40]	286982	1			T5	128		T4	1216		T20	12
valid_sources[0x41]	299310	1			T5	142		T4	1160		T20	15
valid_sources[0x42]	288347	1			T5	197		T4	1099		T20	15
valid_sources[0x43]	298472	1			T5	222		T4	1210		T20	18
valid_sources[0x44]	535655	1			T5	121		T4	1149		T20	26
valid_sources[0x45]	614825	1			T5	181		T4	1061		T20	7
valid_sources[0x46]	289102	1			T5	119		T4	1027		T20	21
valid_sources[0x47]	296893	1			T5	193		T4	1120		T20	20
valid_sources[0x48]	298498	1			T5	232		T4	1079		T20	21
valid_sources[0x49]	292039	1			T5	241		T4	1039		T20	16
valid_sources[0x4a]	285013	1			T5	196		T4	1156		T20	9
valid_sources[0x4b]	561417	1			T2	79		T5	149		T4	1181
valid_sources[0x4c]	290340	1			T5	147		T4	1121		T20	16
valid_sources[0x4d]	292431	1			T5	185		T4	1131		T20	20
valid_sources[0x4e]	285127	1			T5	140		T4	1191		T20	9
valid_sources[0x4f]	283493	1			T5	171		T4	1038		T20	8
valid_sources[0x50]	284154	1			T5	196		T4	1205		T20	15
valid_sources[0x51]	301614	1			T5	201		T4	1073		T20	17
valid_sources[0x52]	309588	1			T5	196		T4	1246		T20	27
valid_sources[0x53]	306542	1			T5	188		T4	1103		T20	19
valid_sources[0x54]	294229	1			T5	217		T4	1152		T20	18
valid_sources[0x55]	288512	1			T5	185		T4	1159		T20	19
valid_sources[0x56]	321546	1			T5	124		T4	1034		T20	17
valid_sources[0x57]	289961	1			T5	259		T4	1151		T20	17
valid_sources[0x58]	286185	1			T5	175		T4	1149		T20	17
valid_sources[0x59]	289716	1			T5	196		T4	1281		T20	12
valid_sources[0x5a]	286482	1			T5	172		T4	1035		T20	21
valid_sources[0x5b]	289471	1			T5	121		T4	1041		T20	12
valid_sources[0x5c]	291199	1			T5	169		T4	1071		T20	16
valid_sources[0x5d]	285057	1			T5	142		T4	1388		T20	15
valid_sources[0x5e]	630299	1			T5	149		T4	1177		T20	16
valid_sources[0x5f]	287920	1			T5	143		T4	1166		T20	15
valid_sources[0x60]	298347	1			T5	105		T4	1191		T20	12
valid_sources[0x61]	293028	1			T5	180		T4	1247		T20	19
valid_sources[0x62]	292546	1			T5	163		T4	1153		T20	13
valid_sources[0x63]	782633	1			T2	193		T5	195		T4	1203
valid_sources[0x64]	292674	1			T5	177		T4	1045		T20	15
valid_sources[0x65]	820473	1			T5	176		T4	1292		T20	19
valid_sources[0x66]	294994	1			T5	124		T4	980		T20	13
valid_sources[0x67]	743545	1			T5	106		T4	1161		T20	28
valid_sources[0x68]	298778	1			T5	202		T4	1105		T20	17
valid_sources[0x69]	297136	1			T5	152		T4	1157		T20	13
valid_sources[0x6a]	288980	1			T5	196		T4	1185		T20	17
valid_sources[0x6b]	295215	1			T5	183		T4	1150		T20	24
valid_sources[0x6c]	287692	1			T5	177		T4	1007		T20	22
valid_sources[0x6d]	289298	1			T5	128		T4	1205		T20	14
valid_sources[0x6e]	288528	1			T5	152		T4	1038		T20	20
valid_sources[0x6f]	287743	1			T5	169		T4	981		T20	11
valid_sources[0x70]	283600	1			T5	136		T4	1128		T20	25
valid_sources[0x71]	289188	1			T5	77		T4	1126		T20	18
valid_sources[0x72]	288921	1			T5	176		T4	1249		T20	12
valid_sources[0x73]	290372	1			T5	212		T4	1210		T20	21
valid_sources[0x74]	289153	1			T5	191		T4	1028		T20	18
valid_sources[0x75]	288678	1			T5	119		T4	994		T20	15
valid_sources[0x76]	289129	1			T5	163		T4	1020		T20	18
valid_sources[0x77]	287410	1			T5	146		T4	1122		T20	16
valid_sources[0x78]	291764	1			T5	186		T4	966		T20	20
valid_sources[0x79]	510633	1			T5	131		T4	1179		T20	13
valid_sources[0x7a]	293033	1			T5	173		T4	1149		T20	29
valid_sources[0x7b]	289572	1			T5	186		T4	1203		T20	19
valid_sources[0x7c]	288645	1			T5	165		T4	1133		T20	19
valid_sources[0x7d]	295542	1			T5	177		T4	1042		T20	19
valid_sources[0x7e]	293449	1			T5	188		T4	1051		T20	18
valid_sources[0x7f]	291919	1			T5	131		T4	1088		T20	13
valid_sources[0x80]	290830	1			T5	192		T4	1133		T20	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6989926

1

T1

25522

T2

34

T3

9

values[0x0]

all_enables

biggest_size

14474145

1

T1

65344

T2

60

T3

55

values[0x1]

all_enables

biggest_size

8434186

1

T1

36549

T2

28

T3

22