Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T102,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13998	0	0
DisabledNoTrigBkwd_A	2147483647	838371	0	0
DisabledNoTrigFwd_A	2147483647	1491112629	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13998	0	0
T3	1008	230	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T8	123295	0	0	0
T9	882677	0	0	0
T14	103623	0	0	0
T15	577151	0	0	0
T19	264727	0	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T23	528166	0	0	0
T29	604853	0	0	0
T32	475484	0	0	0
T62	8376	0	0	0
T63	68631	0	0	0
T64	569186	0	0	0
T65	9568	0	0	0
T102	1398	528	0	0
T103	309530	0	0	0
T180	0	647	0	0
T199	0	973	0	0
T200	0	484	0	0
T201	0	1007	0	0
T202	3128	828	0	0
T203	0	680	0	0
T204	0	655	0	0
T205	0	1823	0	0
T206	0	696	0	0
T207	0	159	0	0
T208	0	338	0	0
T209	0	590	0	0
T210	0	623	0	0
T211	0	1177	0	0
T212	0	527	0	0
T213	0	312	0	0
T214	0	607	0	0
T215	0	1114	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	838371	0	0
T1	1457204	7655	0	0
T2	92624	0	0	0
T3	4032	6	0	0
T4	471172	812	0	0
T5	1547136	258	0	0
T6	1300136	4728	0	0
T7	0	1	0	0
T14	414492	12	0	0
T15	0	2783	0	0
T16	0	2190	0	0
T17	0	1105	0	0
T18	0	1490	0	0
T19	1058908	628	0	0
T20	147096	5	0	0
T21	591796	966	0	0
T29	0	3310	0	0
T31	0	3	0	0
T41	0	4	0	0
T42	0	9	0	0
T43	0	2	0	0
T44	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1491112629	0	0
T1	1457204	2363678	0	0
T2	92624	10257	0	0
T3	4032	2416	0	0
T4	471172	257731	0	0
T5	1547136	740655	0	0
T6	1300136	657366	0	0
T14	414492	413634	0	0
T19	1058908	863557	0	0
T20	147096	106260	0	0
T21	591796	1240031	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T102,T199,T206
1	1	Covered	T1,T5,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687220843	2724	0	0
DisabledNoTrigBkwd_A	687220843	256786	0	0
DisabledNoTrigFwd_A	687220843	329383753	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	2724	0	0
T8	123295	0	0	0
T9	882677	0	0	0
T23	528166	0	0	0
T32	475484	0	0	0
T62	8376	0	0	0
T63	68631	0	0	0
T64	569186	0	0	0
T65	9568	0	0	0
T102	1398	528	0	0
T103	309530	0	0	0
T199	0	973	0	0
T206	0	696	0	0
T212	0	527	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	256786	0	0
T1	364301	1091	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	266	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	48	0	0
T17	0	1099	0	0
T19	264727	105	0	0
T20	36774	5	0	0
T21	147949	681	0	0
T29	0	3310	0	0
T31	0	2	0	0
T42	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	329383753	0	0
T1	364301	118254	0	0
T2	23156	2549	0	0
T3	1008	598	0	0
T4	117793	8905	0	0
T5	386784	369937	0	0
T6	325034	325028	0	0
T14	103623	103413	0	0
T19	264727	211094	0	0
T20	36774	33250	0	0
T21	147949	231068	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T180,T200
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687220843	6467	0	0
DisabledNoTrigBkwd_A	687220843	152247	0	0
DisabledNoTrigFwd_A	687220843	418349132	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	6467	0	0
T3	1008	230	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	577151	0	0	0
T19	264727	0	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T29	604853	0	0	0
T180	0	647	0	0
T200	0	484	0	0
T203	0	680	0	0
T205	0	1823	0	0
T211	0	1177	0	0
T213	0	312	0	0
T215	0	1114	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	152247	0	0
T1	364301	3698	0	0
T2	23156	0	0	0
T3	1008	6	0	0
T4	117793	543	0	0
T5	386784	3	0	0
T6	325034	2026	0	0
T14	103623	11	0	0
T15	0	2723	0	0
T19	264727	225	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T31	0	1	0	0
T43	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	418349132	0	0
T1	364301	643720	0	0
T2	23156	2559	0	0
T3	1008	602	0	0
T4	117793	15138	0	0
T5	386784	349829	0	0
T6	325034	2365	0	0
T14	103623	103203	0	0
T19	264727	223970	0	0
T20	36774	31964	0	0
T21	147949	147821	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T204
1	1	Covered	T1,T5,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687220843	1483	0	0
DisabledNoTrigBkwd_A	687220843	250865	0	0
DisabledNoTrigFwd_A	687220843	361245045	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1483	0	0
T59	18076	0	0	0
T60	814414	0	0	0
T85	30581	0	0	0
T202	3128	828	0	0
T203	1473	0	0	0
T204	0	655	0	0
T216	123191	0	0	0
T217	510845	0	0	0
T218	163347	0	0	0
T219	780042	0	0	0
T220	33771	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	250865	0	0
T1	364301	1583	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	3	0	0
T5	386784	145	0	0
T6	325034	2701	0	0
T14	103623	0	0	0
T15	0	12	0	0
T16	0	1146	0	0
T17	0	6	0	0
T18	0	1490	0	0
T19	264727	127	0	0
T20	36774	0	0	0
T21	147949	258	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	361245045	0	0
T1	364301	719915	0	0
T2	23156	2567	0	0
T3	1008	606	0	0
T4	117793	116664	0	0
T5	386784	5507	0	0
T6	325034	6063	0	0
T14	103623	103509	0	0
T19	264727	218421	0	0
T20	36774	31970	0	0
T21	147949	725272	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T207,T208
1	1	Covered	T1,T5,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687220843	3324	0	0
DisabledNoTrigBkwd_A	687220843	178473	0	0
DisabledNoTrigFwd_A	687220843	382134699	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	3324	0	0
T56	87413	0	0	0
T57	113773	0	0	0
T82	22880	0	0	0
T201	1816	1007	0	0
T207	0	159	0	0
T208	0	338	0	0
T209	0	590	0	0
T210	0	623	0	0
T214	0	607	0	0
T221	25815	0	0	0
T222	33751	0	0	0
T223	14894	0	0	0
T224	163307	0	0	0
T225	15815	0	0	0
T226	261466	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	178473	0	0
T1	364301	1283	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	110	0	0
T6	325034	1	0	0
T7	0	1	0	0
T14	103623	1	0	0
T16	0	1044	0	0
T19	264727	171	0	0
T20	36774	0	0	0
T21	147949	27	0	0
T41	0	4	0	0
T44	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	382134699	0	0
T1	364301	881789	0	0
T2	23156	2582	0	0
T3	1008	610	0	0
T4	117793	117024	0	0
T5	386784	15382	0	0
T6	325034	323910	0	0
T14	103623	103509	0	0
T19	264727	210072	0	0
T20	36774	9076	0	0
T21	147949	135870	0	0