Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T20
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T19,T21
1	1	1	Covered	T1,T19,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T1,T19,T21
1	0	Covered	T22,T23,T24

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T21
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T23,T24

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Covered	T25
1	1	Covered	T1,T19,T21

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T3,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T5,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T5,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T4,T19

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T19,T21
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T26,T27,T28
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T1,T22,T27
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T29,T27,T30
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T31,T8,T32
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T4,T19
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T19,T21
TimeoutSt->Phase0St	167	Covered	T1,T19,T21

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T22,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T27,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T8,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1229	0	0
CheckAccumTrig0_A	2147483647	2373	0	0
CheckAccumTrig1_A	2147483647	113	0	0
CheckClr_A	2147483647	1088	0	0
CheckEn_A	2147483647	1179642239	0	0
CheckPhase0_A	2147483647	2686	0	0
CheckPhase1_A	2147483647	2628	0	0
CheckPhase2_A	2147483647	2585	0	0
CheckPhase3_A	2147483647	2535	0	0
CheckTimeout0_A	2147483647	2649	0	0
CheckTimeoutSt1_A	2147483647	386643	0	0
CheckTimeoutSt2_A	2147483647	2268	0	0
CheckTimeoutStTrig_A	2147483647	260	0	0
ErrorStAllEscAsserted_A	2147483647	6553	0	0
ErrorStIsTerminal_A	2147483647	5473	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1229	0	0
T11	188448	274	0	0
T12	0	256	0	0
T13	0	114	0	0
T24	105144	0	0	0
T27	464696	0	0	0
T30	395220	0	0	0
T33	0	296	0	0
T34	0	289	0	0
T35	74664	0	0	0
T36	111524	0	0	0
T37	57484	0	0	0
T38	710672	0	0	0
T39	193532	0	0	0
T40	155448	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2373	0	0
T1	1457204	25	0	0
T2	92624	0	0	0
T3	4032	1	0	0
T4	471172	4	0	0
T5	1547136	3	0	0
T6	1300136	5	0	0
T7	0	1	0	0
T14	414492	2	0	0
T15	0	6	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	1058908	7	0	0
T20	147096	1	0	0
T21	591796	4	0	0
T29	0	5	0	0
T31	0	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	113	0	0
T9	882677	0	0	0
T11	47112	0	0	0
T22	639671	1	0	0
T23	528166	1	0	0
T24	26286	1	0	0
T27	116174	0	0	0
T28	177539	2	0	0
T32	475484	0	0	0
T45	0	2	0	0
T46	427416	2	0	0
T47	446050	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	8376	0	0	0
T63	68631	0	0	0
T64	569186	0	0	0
T65	9568	0	0	0
T66	111147	0	0	0
T67	364118	0	0	0
T68	22470	0	0	0
T69	289017	0	0	0
T70	152793	0	0	0
T71	16420	0	0	0
T72	121586	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1088	0	0
T1	1092903	4	0	0
T2	69468	0	0	0
T3	3024	0	0	0
T4	353379	1	0	0
T5	1160352	0	0	0
T6	1300136	2	0	0
T14	414492	0	0	0
T15	577151	2	0	0
T16	185115	0	0	0
T17	242779	1	0	0
T19	794181	2	0	0
T20	110322	0	0	0
T21	591796	1	0	0
T22	0	4	0	0
T23	0	3	0	0
T26	0	5	0	0
T27	0	2	0	0
T29	604853	3	0	0
T31	6025	3	0	0
T32	0	2	0	0
T41	10851	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	4	0	0
T77	522366	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1179642239	0	0
T1	1457204	2977678	0	0
T2	92624	10253	0	0
T3	4032	2416	0	0
T4	471172	129822	0	0
T5	1547136	428851	0	0
T6	1300136	657366	0	0
T14	414492	208101	0	0
T19	1058908	860912	0	0
T20	147096	75038	0	0
T21	591796	1173798	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2686	0	0
T1	1457204	28	0	0
T2	92624	0	0	0
T3	4032	1	0	0
T4	471172	4	0	0
T5	1547136	3	0	0
T6	1300136	5	0	0
T14	414492	2	0	0
T15	0	6	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	1058908	9	0	0
T20	147096	1	0	0
T21	591796	6	0	0
T29	0	5	0	0
T31	0	3	0	0
T41	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2628	0	0
T1	1457204	26	0	0
T2	92624	0	0	0
T3	4032	1	0	0
T4	471172	4	0	0
T5	1547136	3	0	0
T6	1300136	5	0	0
T14	414492	2	0	0
T15	0	6	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	1058908	9	0	0
T20	147096	1	0	0
T21	591796	6	0	0
T29	0	5	0	0
T31	0	3	0	0
T41	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2585	0	0
T1	1457204	26	0	0
T2	92624	0	0	0
T3	4032	1	0	0
T4	471172	4	0	0
T5	1547136	3	0	0
T6	1300136	5	0	0
T14	414492	2	0	0
T15	0	6	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	1058908	9	0	0
T20	147096	1	0	0
T21	591796	6	0	0
T29	0	4	0	0
T31	0	3	0	0
T41	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2535	0	0
T1	1457204	26	0	0
T2	92624	0	0	0
T3	4032	1	0	0
T4	471172	4	0	0
T5	1547136	3	0	0
T6	1300136	5	0	0
T14	414492	2	0	0
T15	0	6	0	0
T16	0	2	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	1058908	9	0	0
T20	147096	1	0	0
T21	591796	6	0	0
T29	0	4	0	0
T31	0	2	0	0
T41	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2649	0	0
T1	1457204	84	0	0
T2	92624	0	0	0
T3	4032	0	0	0
T4	471172	0	0	0
T5	1547136	0	0	0
T6	1300136	0	0	0
T14	414492	0	0	0
T16	0	2	0	0
T19	1058908	18	0	0
T20	147096	0	0	0
T21	591796	8	0	0
T22	0	75	0	0
T23	0	18	0	0
T24	0	4	0	0
T26	0	40	0	0
T30	0	1	0	0
T32	0	7	0	0
T41	0	3	0	0
T44	0	1	0	0
T74	0	5	0	0
T75	0	5	0	0
T76	0	9	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	386643	0	0
T1	1457204	8856	0	0
T2	92624	0	0	0
T3	4032	0	0	0
T4	471172	0	0	0
T5	1547136	0	0	0
T6	1300136	0	0	0
T14	414492	0	0	0
T16	0	236	0	0
T19	1058908	2416	0	0
T20	147096	0	0	0
T21	591796	1896	0	0
T22	0	4444	0	0
T23	0	3232	0	0
T24	0	44	0	0
T26	0	6503	0	0
T30	0	30	0	0
T32	0	2521	0	0
T41	0	799	0	0
T44	0	167	0	0
T74	0	1913	0	0
T75	0	423	0	0
T76	0	1638	0	0
T77	0	307	0	0
T78	0	40	0	0
T79	0	152	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2268	0	0
T1	1457204	81	0	0
T2	92624	0	0	0
T3	4032	0	0	0
T4	471172	0	0	0
T5	1547136	0	0	0
T6	1300136	0	0	0
T14	414492	0	0	0
T16	0	2	0	0
T19	1058908	16	0	0
T20	147096	0	0	0
T21	591796	5	0	0
T22	0	74	0	0
T23	0	14	0	0
T24	0	4	0	0
T26	0	34	0	0
T28	0	2	0	0
T30	0	1	0	0
T32	0	5	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	7	0	0
T46	0	20	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	7	0	0
T77	0	1	0	0
T79	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	260	0	0
T1	364301	2	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	207246	0	0	0
T15	577151	0	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	295898	2	0	0
T22	639671	0	0	0
T23	0	3	0	0
T26	110815	4	0	0
T32	0	1	0	0
T41	0	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T54	0	2	0	0
T58	0	3	0	0
T74	26387	1	0	0
T75	44471	4	0	0
T76	261405	1	0	0
T78	0	1	0	0
T79	276429	0	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	17425	0	0	0
T87	16507	0	0	0
T88	98462	0	0	0
T89	210461	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6553	0	0
T11	188448	1438	0	0
T12	0	1479	0	0
T13	0	719	0	0
T24	105144	0	0	0
T27	464696	0	0	0
T30	395220	0	0	0
T33	0	1439	0	0
T34	0	1478	0	0
T35	74664	0	0	0
T36	111524	0	0	0
T37	57484	0	0	0
T38	710672	0	0	0
T39	193532	0	0	0
T40	155448	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5473	0	0
T11	188448	1198	0	0
T12	0	1239	0	0
T13	0	599	0	0
T24	105144	0	0	0
T27	464696	0	0	0
T30	395220	0	0	0
T33	0	1199	0	0
T34	0	1238	0	0
T35	74664	0	0	0
T36	111524	0	0	0
T37	57484	0	0	0
T38	710672	0	0	0
T39	193532	0	0	0
T40	155448	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1457204	1456860	0	0
T2	92624	92012	0	0
T3	4032	3648	0	0
T4	471172	471132	0	0
T5	1547136	1546832	0	0
T6	1300136	1300112	0	0
T14	414492	414460	0	0
T19	1058908	1058620	0	0
T20	147096	146880	0	0
T21	591796	591748	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T20
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T19,T21
1	1	1	Covered	T1,T19,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T74,T75,T23
1	0	Covered	T28,T47,T50

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T47,T50

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Not Covered
1	1	Covered	T74,T75,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T3,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T5,T43,T74

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T4,T7

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T6,T14

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T19,T21
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T27,T28,T90
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T91,T57,T90
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T92,T93,T94
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T47,T91,T93
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T19,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T21
TimeoutSt->Phase0St	167	Covered	T74,T75,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T74,T75,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T74
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T28,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T91,T57,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T92,T93,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T47,T91,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T6,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687220843	270	0	0
CheckAccumTrig0_A	687220843	522	0	0
CheckAccumTrig1_A	687220843	25	0	0
CheckClr_A	687220843	241	0	0
CheckEn_A	687040496	320133668	0	0
CheckPhase0_A	687220843	608	0	0
CheckPhase1_A	687220843	598	0	0
CheckPhase2_A	687220843	590	0	0
CheckPhase3_A	687220843	577	0	0
CheckTimeout0_A	687220843	600	0	0
CheckTimeoutSt1_A	687220843	85014	0	0
CheckTimeoutSt2_A	687220843	502	0	0
CheckTimeoutStTrig_A	687220843	70	0	0
ErrorStAllEscAsserted_A	687220843	1636	0	0
ErrorStIsTerminal_A	687220843	1366	0	0
u_state_regs_A	687220843	687035610	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	270	0	0
T11	47112	44	0	0
T12	0	59	0	0
T13	0	18	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	81	0	0
T34	0	68	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	522	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	1	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	1	0	0
T15	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T31	0	1	0	0
T43	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	25	0	0
T28	177539	1	0	0
T46	427416	0	0	0
T47	446050	1	0	0
T50	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T66	111147	0	0	0
T67	364118	0	0	0
T68	22470	0	0	0
T69	289017	0	0	0
T70	152793	0	0	0
T71	16420	0	0	0
T72	121586	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	241	0	0
T1	364301	1	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	1	0	0
T14	103623	0	0	0
T19	264727	0	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T27	0	1	0	0
T31	0	1	0	0
T43	0	1	0	0
T74	0	1	0	0
T75	0	3	0	0
T76	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687040496	320133668	0	0
T1	364301	577556	0	0
T2	23156	2558	0	0
T3	1008	602	0	0
T4	117793	1945	0	0
T5	386784	38026	0	0
T6	325034	2365	0	0
T14	103623	586	0	0
T19	264727	223970	0	0
T20	36774	31963	0	0
T21	147949	147821	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	608	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	1	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	1	0	0
T15	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T31	0	1	0	0
T43	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	598	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	1	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	1	0	0
T15	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T31	0	1	0	0
T43	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	590	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	1	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	1	0	0
T15	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T31	0	1	0	0
T43	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	577	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	1	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	1	0	0
T15	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T31	0	1	0	0
T43	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	600	0	0
T1	364301	23	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T22	0	6	0	0
T23	0	4	0	0
T24	0	4	0	0
T26	0	20	0	0
T74	0	5	0	0
T75	0	5	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	85014	0	0
T1	364301	2168	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	129	0	0
T20	36774	0	0	0
T21	147949	170	0	0
T22	0	345	0	0
T23	0	862	0	0
T24	0	44	0	0
T26	0	3525	0	0
T74	0	1913	0	0
T75	0	423	0	0
T76	0	11	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	502	0	0
T1	364301	23	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T22	0	6	0	0
T23	0	3	0	0
T24	0	4	0	0
T26	0	20	0	0
T45	0	4	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	70	0	0
T22	639671	0	0	0
T23	0	1	0	0
T26	110815	0	0	0
T46	0	1	0	0
T54	0	2	0	0
T58	0	3	0	0
T74	26387	1	0	0
T75	44471	4	0	0
T76	261405	0	0	0
T79	276429	0	0	0
T80	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T86	17425	0	0	0
T87	16507	0	0	0
T88	98462	0	0	0
T89	210461	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1636	0	0
T11	47112	353	0	0
T12	0	370	0	0
T13	0	198	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	368	0	0
T34	0	347	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1366	0	0
T11	47112	293	0	0
T12	0	310	0	0
T13	0	168	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	308	0	0
T34	0	287	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	687035610	0	0
T1	364301	364215	0	0
T2	23156	23003	0	0
T3	1008	912	0	0
T4	117793	117783	0	0
T5	386784	386708	0	0
T6	325034	325028	0	0
T14	103623	103615	0	0
T19	264727	264655	0	0
T20	36774	36720	0	0
T21	147949	147937	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T20
1	0	1	Covered	T1,T5,T19
1	1	0	Covered	T1,T19,T21
1	1	1	Covered	T1,T19,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T21,T26,T23
1	0	Covered	T22,T24,T46

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T24,T46

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Not Covered
1	1	Covered	T21,T26,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T17,T18

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T1,T19,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T5,T21,T15

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T4,T21,T22

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T5,T4
Phase1St	193	Covered	T1,T5,T4
Phase2St	210	Covered	T1,T5,T4
Phase3St	228	Covered	T1,T5,T4
TerminalSt	244	Covered	T1,T5,T4
TimeoutSt	154	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T5,T4
IdleSt->TimeoutSt	154	Covered	T1,T19,T21
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T69,T95
Phase0St->Phase1St	193	Covered	T1,T5,T4
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T22,T27,T69
Phase1St->Phase2St	210	Covered	T1,T5,T4
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T28,T46,T61
Phase2St->Phase3St	228	Covered	T1,T5,T4
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T45,T96,T97
Phase3St->TerminalSt	244	Covered	T1,T5,T4
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T19,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T21
TimeoutSt->Phase0St	167	Covered	T21,T22,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T69,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T27,T69
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T46,T61
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T45,T96,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T21,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687220843	284	0	0
CheckAccumTrig0_A	687220843	497	0	0
CheckAccumTrig1_A	687220843	23	0	0
CheckClr_A	687220843	223	0	0
CheckEn_A	687040496	294926420	0	0
CheckPhase0_A	687220843	578	0	0
CheckPhase1_A	687220843	563	0	0
CheckPhase2_A	687220843	553	0	0
CheckPhase3_A	687220843	546	0	0
CheckTimeout0_A	687220843	674	0	0
CheckTimeoutSt1_A	687220843	98768	0	0
CheckTimeoutSt2_A	687220843	577	0	0
CheckTimeoutStTrig_A	687220843	71	0	0
ErrorStAllEscAsserted_A	687220843	1628	0	0
ErrorStIsTerminal_A	687220843	1358	0	0
u_state_regs_A	687220843	687035610	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	284	0	0
T11	47112	63	0	0
T12	0	74	0	0
T13	0	14	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	54	0	0
T34	0	79	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	497	0	0
T1	364301	4	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	23	0	0
T22	639671	1	0	0
T24	0	1	0	0
T26	110815	0	0	0
T46	0	1	0	0
T50	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T76	261405	0	0	0
T79	276429	0	0	0
T87	16507	0	0	0
T88	98462	0	0	0
T89	210461	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	174025	0	0	0
T102	1398	0	0	0
T103	309530	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	223	0	0
T6	325034	1	0	0
T14	103623	0	0	0
T15	577151	1	0	0
T16	185115	0	0	0
T17	242779	0	0	0
T21	147949	1	0	0
T22	0	3	0	0
T26	0	5	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	604853	0	0	0
T31	6025	0	0	0
T32	0	2	0	0
T41	10851	0	0	0
T45	0	6	0	0
T76	0	2	0	0
T77	522366	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687040496	294926420	0	0
T1	364301	644164	0	0
T2	23156	2566	0	0
T3	1008	606	0	0
T4	117793	1949	0	0
T5	386784	5507	0	0
T6	325034	6063	0	0
T14	103623	103508	0	0
T19	264727	218421	0	0
T20	36774	31969	0	0
T21	147949	663473	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	578	0	0
T1	364301	4	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	563	0	0
T1	364301	4	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	553	0	0
T1	364301	4	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	546	0	0
T1	364301	4	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	1	0	0
T5	386784	1	0	0
T6	325034	2	0	0
T14	103623	0	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	674	0	0
T1	364301	29	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	5	0	0
T20	36774	0	0	0
T21	147949	3	0	0
T22	0	66	0	0
T23	0	2	0	0
T26	0	3	0	0
T32	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T79	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	98768	0	0
T1	364301	3347	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	676	0	0
T20	36774	0	0	0
T21	147949	827	0	0
T22	0	3883	0	0
T23	0	336	0	0
T26	0	141	0	0
T32	0	967	0	0
T76	0	138	0	0
T77	0	217	0	0
T79	0	152	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	577	0	0
T1	364301	29	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	5	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T22	0	65	0	0
T28	0	2	0	0
T32	0	1	0	0
T46	0	7	0	0
T76	0	2	0	0
T77	0	1	0	0
T79	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	71	0	0
T14	103623	0	0	0
T15	577151	0	0	0
T16	185115	0	0	0
T17	242779	0	0	0
T21	147949	2	0	0
T23	0	2	0	0
T26	0	3	0	0
T29	604853	0	0	0
T31	6025	0	0	0
T32	0	1	0	0
T41	10851	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0
T77	522366	0	0	0
T78	21966	0	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1628	0	0
T11	47112	369	0	0
T12	0	353	0	0
T13	0	181	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	342	0	0
T34	0	383	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1358	0	0
T11	47112	309	0	0
T12	0	293	0	0
T13	0	151	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	282	0	0
T34	0	323	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	687035610	0	0
T1	364301	364215	0	0
T2	23156	23003	0	0
T3	1008	912	0	0
T4	117793	117783	0	0
T5	386784	386708	0	0
T6	325034	325028	0	0
T14	103623	103615	0	0
T19	264727	264655	0	0
T20	36774	36720	0	0
T21	147949	147937	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T19

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T19

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T20
1	0	1	Covered	T1,T5,T4
1	1	0	Covered	T1,T19,T21
1	1	1	Covered	T1,T19,T21

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T21
0	1	Covered	T77,T76,T26
1	0	Covered	T1,T19,T26

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T19,T26

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T21
1	0	Not Covered
1	1	Covered	T77,T76,T26

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T7,T76

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T6
1	Covered	T1,T5,T19

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T19,T21

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T6,T14

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T5,T19
Phase1St	193	Covered	T1,T5,T19
Phase2St	210	Covered	T1,T5,T19
Phase3St	228	Covered	T1,T5,T19
TerminalSt	244	Covered	T1,T5,T19
TimeoutSt	154	Covered	T1,T19,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T5,T19
IdleSt->TimeoutSt	154	Covered	T1,T19,T21
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T99,T104,T105
Phase0St->Phase1St	193	Covered	T1,T5,T19
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T1,T23,T57
Phase1St->Phase2St	210	Covered	T1,T5,T19
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T106,T50,T107
Phase2St->Phase3St	228	Covered	T1,T5,T19
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T106,T108,T100
Phase3St->TerminalSt	244	Covered	T1,T5,T19
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T19,T6
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T21
TimeoutSt->Phase0St	167	Covered	T1,T19,T77

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T77
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T99,T104,T109
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T23,T57
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T106,T50,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T106,T108,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T6,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687220843	328	0	0
CheckAccumTrig0_A	687220843	511	0	0
CheckAccumTrig1_A	687220843	21	0	0
CheckClr_A	687220843	224	0	0
CheckEn_A	687040496	313559609	0	0
CheckPhase0_A	687220843	575	0	0
CheckPhase1_A	687220843	566	0	0
CheckPhase2_A	687220843	561	0	0
CheckPhase3_A	687220843	554	0	0
CheckTimeout0_A	687220843	746	0	0
CheckTimeoutSt1_A	687220843	116437	0	0
CheckTimeoutSt2_A	687220843	672	0	0
CheckTimeoutStTrig_A	687220843	51	0	0
ErrorStAllEscAsserted_A	687220843	1597	0	0
ErrorStIsTerminal_A	687220843	1327	0	0
u_state_regs_A	687220843	687035610	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	328	0	0
T11	47112	76	0	0
T12	0	55	0	0
T13	0	40	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	87	0	0
T34	0	70	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	511	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	1	0	0
T6	325034	1	0	0
T7	0	1	0	0
T14	103623	1	0	0
T16	0	1	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T41	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	21	0	0
T1	364301	1	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T26	0	1	0	0
T46	0	1	0	0
T50	0	1	0	0
T59	0	1	0	0
T99	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	224	0	0
T1	364301	5	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	1	0	0
T14	103623	0	0	0
T19	264727	0	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T23	0	2	0	0
T26	0	1	0	0
T28	0	3	0	0
T32	0	1	0	0
T44	0	1	0	0
T46	0	4	0	0
T76	0	2	0	0
T110	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687040496	313559609	0	0
T1	364301	877677	0	0
T2	23156	2581	0	0
T3	1008	610	0	0
T4	117793	117023	0	0
T5	386784	15382	0	0
T6	325034	323910	0	0
T14	103623	594	0	0
T19	264727	208618	0	0
T20	36774	9076	0	0
T21	147949	131439	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	575	0	0
T1	364301	8	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	1	0	0
T6	325034	1	0	0
T14	103623	1	0	0
T16	0	1	0	0
T19	264727	2	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	566	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	1	0	0
T6	325034	1	0	0
T14	103623	1	0	0
T16	0	1	0	0
T19	264727	2	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	561	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	1	0	0
T6	325034	1	0	0
T14	103623	1	0	0
T16	0	1	0	0
T19	264727	2	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	554	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	1	0	0
T6	325034	1	0	0
T14	103623	1	0	0
T16	0	1	0	0
T19	264727	2	0	0
T20	36774	0	0	0
T21	147949	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	746	0	0
T1	364301	5	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T16	0	2	0	0
T19	264727	10	0	0
T20	36774	0	0	0
T21	147949	4	0	0
T23	0	10	0	0
T26	0	3	0	0
T32	0	4	0	0
T44	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	116437	0	0
T1	364301	534	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T16	0	236	0	0
T19	264727	1137	0	0
T20	36774	0	0	0
T21	147949	899	0	0
T23	0	1815	0	0
T26	0	231	0	0
T32	0	1387	0	0
T44	0	167	0	0
T76	0	82	0	0
T77	0	90	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	672	0	0
T1	364301	4	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T16	0	2	0	0
T19	264727	9	0	0
T20	36774	0	0	0
T21	147949	4	0	0
T23	0	10	0	0
T26	0	1	0	0
T32	0	3	0	0
T44	0	1	0	0
T45	0	3	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	51	0	0
T16	185115	0	0	0
T17	242779	0	0	0
T18	297262	0	0	0
T26	0	1	0	0
T31	6025	0	0	0
T32	0	1	0	0
T42	80374	0	0	0
T43	116377	0	0	0
T46	0	1	0	0
T54	0	1	0	0
T73	17097	0	0	0
T76	0	1	0	0
T77	522366	1	0	0
T78	21966	0	0	0
T80	0	1	0	0
T83	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	158964	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1597	0	0
T11	47112	344	0	0
T12	0	340	0	0
T13	0	158	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	362	0	0
T34	0	393	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1327	0	0
T11	47112	284	0	0
T12	0	280	0	0
T13	0	128	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	302	0	0
T34	0	333	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	687035610	0	0
T1	364301	364215	0	0
T2	23156	23003	0	0
T3	1008	912	0	0
T4	117793	117783	0	0
T5	386784	386708	0	0
T6	325034	325028	0	0
T14	103623	103615	0	0
T19	264727	264655	0	0
T20	36774	36720	0	0
T21	147949	147937	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T19

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T21
1	0	1	Covered	T1,T5,T4
1	1	0	Covered	T1,T19,T21
1	1	1	Covered	T1,T19,T41

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T41
0	1	Covered	T1,T19,T41
1	0	Covered	T23,T45,T28

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T41
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T45,T28

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T41
1	0	Covered	T25
1	1	Covered	T1,T19,T41

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T29,T42

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T19,T20

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T4,T19

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T4,T19

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T11,T12,T13
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T4,T19
Phase1St	193	Covered	T1,T4,T19
Phase2St	210	Covered	T1,T4,T19
Phase3St	228	Covered	T1,T4,T19
TerminalSt	244	Covered	T1,T4,T19
TimeoutSt	154	Covered	T1,T19,T41

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T11,T12,T13
IdleSt->Phase0St	147	Covered	T1,T4,T19
IdleSt->TimeoutSt	154	Covered	T1,T19,T41
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T47,T52,T116
Phase0St->Phase1St	193	Covered	T1,T4,T19
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T1,T22,T27
Phase1St->Phase2St	210	Covered	T1,T4,T19
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T29,T27,T30
Phase2St->Phase3St	228	Covered	T1,T4,T19
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T31,T8,T32
Phase3St->TerminalSt	244	Covered	T1,T4,T19
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T4,T19
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T19,T41
TimeoutSt->Phase0St	167	Covered	T1,T19,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T41
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T41
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T41
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T47,T52,T116
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T22,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T27,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T8,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687220843	347	0	0
CheckAccumTrig0_A	687220843	843	0	0
CheckAccumTrig1_A	687220843	44	0	0
CheckClr_A	687220843	400	0	0
CheckEn_A	687040496	251022542	0	0
CheckPhase0_A	687220843	925	0	0
CheckPhase1_A	687220843	901	0	0
CheckPhase2_A	687220843	881	0	0
CheckPhase3_A	687220843	858	0	0
CheckTimeout0_A	687220843	629	0	0
CheckTimeoutSt1_A	687220843	86424	0	0
CheckTimeoutSt2_A	687220843	517	0	0
CheckTimeoutStTrig_A	687220843	68	0	0
ErrorStAllEscAsserted_A	687220843	1692	0	0
ErrorStIsTerminal_A	687220843	1422	0	0
u_state_regs_A	687220843	687035610	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	347	0	0
T11	47112	91	0	0
T12	0	68	0	0
T13	0	42	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	74	0	0
T34	0	72	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	843	0	0
T1	364301	7	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	2	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	3	0	0
T17	0	2	0	0
T19	264727	4	0	0
T20	36774	1	0	0
T21	147949	2	0	0
T29	0	5	0	0
T31	0	2	0	0
T42	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	44	0	0
T9	882677	0	0	0
T11	47112	0	0	0
T23	528166	1	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T28	0	1	0	0
T32	475484	0	0	0
T45	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T62	8376	0	0	0
T63	68631	0	0	0
T64	569186	0	0	0
T65	9568	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	400	0	0
T1	364301	3	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	1	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	264727	2	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T29	0	3	0	0
T31	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687040496	251022542	0	0
T1	364301	878281	0	0
T2	23156	2548	0	0
T3	1008	598	0	0
T4	117793	8905	0	0
T5	386784	369936	0	0
T6	325034	325028	0	0
T14	103623	103413	0	0
T19	264727	209903	0	0
T20	36774	2030	0	0
T21	147949	231065	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	925	0	0
T1	364301	9	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	2	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	3	0	0
T17	0	2	0	0
T19	264727	5	0	0
T20	36774	1	0	0
T21	147949	2	0	0
T29	0	5	0	0
T31	0	2	0	0
T41	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	901	0	0
T1	364301	8	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	2	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	3	0	0
T17	0	2	0	0
T19	264727	5	0	0
T20	36774	1	0	0
T21	147949	2	0	0
T29	0	5	0	0
T31	0	2	0	0
T41	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	881	0	0
T1	364301	8	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	2	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	3	0	0
T17	0	2	0	0
T19	264727	5	0	0
T20	36774	1	0	0
T21	147949	2	0	0
T29	0	4	0	0
T31	0	2	0	0
T41	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	858	0	0
T1	364301	8	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	2	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T15	0	3	0	0
T17	0	2	0	0
T19	264727	5	0	0
T20	36774	1	0	0
T21	147949	2	0	0
T29	0	4	0	0
T31	0	1	0	0
T41	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	629	0	0
T1	364301	27	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	2	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T22	0	3	0	0
T23	0	2	0	0
T26	0	14	0	0
T30	0	1	0	0
T32	0	1	0	0
T41	0	3	0	0
T76	0	3	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	86424	0	0
T1	364301	2807	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	474	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T22	0	216	0	0
T23	0	219	0	0
T26	0	2606	0	0
T30	0	30	0	0
T32	0	167	0	0
T41	0	799	0	0
T76	0	1407	0	0
T78	0	40	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	517	0	0
T1	364301	25	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T22	0	3	0	0
T23	0	1	0	0
T26	0	13	0	0
T30	0	1	0	0
T32	0	1	0	0
T41	0	1	0	0
T46	0	13	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	68	0	0
T1	364301	2	0	0
T2	23156	0	0	0
T3	1008	0	0	0
T4	117793	0	0	0
T5	386784	0	0	0
T6	325034	0	0	0
T14	103623	0	0	0
T19	264727	1	0	0
T20	36774	0	0	0
T21	147949	0	0	0
T26	0	1	0	0
T41	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T76	0	1	0	0
T78	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1692	0	0
T11	47112	372	0	0
T12	0	416	0	0
T13	0	182	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	367	0	0
T34	0	355	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	1422	0	0
T11	47112	312	0	0
T12	0	356	0	0
T13	0	152	0	0
T24	26286	0	0	0
T27	116174	0	0	0
T30	98805	0	0	0
T33	0	307	0	0
T34	0	295	0	0
T35	18666	0	0	0
T36	27881	0	0	0
T37	14371	0	0	0
T38	177668	0	0	0
T39	48383	0	0	0
T40	38862	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687220843	687035610	0	0
T1	364301	364215	0	0
T2	23156	23003	0	0
T3	1008	912	0	0
T4	117793	117783	0	0
T5	386784	386708	0	0
T6	325034	325028	0	0
T14	103623	103615	0	0
T19	264727	264655	0	0
T20	36774	36720	0	0
T21	147949	147937	0	0