Module : prim_buf
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_buf_0/prim_buf.sv
Module self-instances :
Module Instance : tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| u_prim_reg_we_check |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_buf_input
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 83.33 | 100.00 | 50.00 | 100.00 | u_prim_double_lfsr |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_buf_output
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 83.33 | 100.00 | 50.00 | 100.00 | u_prim_double_lfsr |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_buf_input
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 83.33 | 100.00 | 50.00 | 100.00 | u_prim_double_lfsr |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_buf_output
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 83.33 | 100.00 | 50.00 | 100.00 | u_prim_double_lfsr |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_ping_timer.u_prim_buf_spurious_alert_ping
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 91.02 | 91.94 | 89.19 | 83.33 | 90.62 | 100.00 | u_ping_timer |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_ping_timer.u_prim_buf_spurious_esc_ping
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 91.02 | 91.94 | 89.19 | 83.33 | 90.62 | 100.00 | u_ping_timer |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[0].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[1].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[2].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[3].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[4].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[5].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[6].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[7].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[8].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[9].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[10].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[11].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[12].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[13].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[14].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[15].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[16].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[17].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[18].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[19].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[20].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[21].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[22].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_cg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_lpgs[23].u_prim_mubi4_sync_rst_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[0].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[0].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[0].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[0].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[1].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[1].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[1].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[1].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[2].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[2].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[2].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[2].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[3].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[3].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[3].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[3].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[4].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[4].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[4].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[4].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[5].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[5].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[5].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[5].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[6].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[6].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[6].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[6].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[7].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[7].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[7].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[7].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[8].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[8].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[8].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[8].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[9].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[9].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[9].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[9].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[10].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[10].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[10].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[10].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[11].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[11].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[11].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[11].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[12].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[12].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[12].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[12].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[13].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[13].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[13].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[13].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[14].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[14].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[14].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[14].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[15].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[15].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[15].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[15].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[16].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[16].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[16].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[16].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[17].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[17].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[17].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[17].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[18].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[18].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[18].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[18].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[19].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[19].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[19].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[19].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[20].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[20].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[20].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[20].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[21].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[21].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[21].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[21].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[22].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[22].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[22].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[22].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[23].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[23].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[23].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[23].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[24].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[24].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[24].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[24].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[25].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[25].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[25].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[25].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[26].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[26].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[26].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[26].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[27].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[27].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[27].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[27].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[28].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[28].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[28].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[28].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[29].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[29].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[29].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[29].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[30].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[30].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[30].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[30].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[31].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[31].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[31].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[31].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[32].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[32].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[32].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[32].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[33].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[33].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[33].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[33].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[34].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[34].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[34].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[34].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[35].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[35].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[35].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[35].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[36].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[36].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[36].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[36].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[37].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[37].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[37].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[37].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[38].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[38].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[38].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[38].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[39].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[39].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[39].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[39].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[40].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[40].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[40].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[40].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[41].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[41].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[41].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[41].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[42].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[42].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[42].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[42].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[43].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[43].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[43].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[43].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[44].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[44].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[44].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[44].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[45].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[45].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[45].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[45].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[46].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[46].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[46].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[46].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[47].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[47].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[47].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[47].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[48].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[48].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[48].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[48].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[49].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[49].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[49].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[49].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[50].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[50].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[50].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[50].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[51].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[51].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[51].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[51].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[52].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[52].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[52].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[52].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[53].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[53].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[53].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[53].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[54].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[54].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[54].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[54].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[55].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[55].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[55].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[55].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[56].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[56].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[56].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[56].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[57].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[57].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[57].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[57].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[58].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[58].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[58].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[58].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[59].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[59].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[59].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[59].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[60].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[60].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[60].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[60].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[61].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[61].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[61].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[61].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[62].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[62].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[62].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[62].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[63].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[63].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[63].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[63].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[0].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[64].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[1].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[64].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[2].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[64].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |
Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en.gen_buffs[0].gen_bits[3].u_prim_buf
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | gen_alert_map[64].u_prim_mubi4_sync_lpg_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 |