Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T54,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14227	0	0
DisabledNoTrigBkwd_A	2147483647	841859	0	0
DisabledNoTrigFwd_A	2147483647	1534340917	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14227	0	0
T12	76611	0	0	0
T13	229681	0	0	0
T22	142034	0	0	0
T33	310482	0	0	0
T34	612075	0	0	0
T44	6395	0	0	0
T46	657614	0	0	0
T52	0	390	0	0
T54	2871	499	0	0
T75	46695	0	0	0
T79	92266	0	0	0
T87	11499	0	0	0
T119	738129	0	0	0
T193	0	349	0	0
T194	2678	477	0	0
T195	3359	413	0	0
T196	0	1290	0	0
T197	0	845	0	0
T198	1078	307	0	0
T199	0	381	0	0
T200	0	1406	0	0
T201	0	774	0	0
T202	0	459	0	0
T203	0	335	0	0
T204	0	601	0	0
T205	0	1228	0	0
T206	0	700	0	0
T207	0	1550	0	0
T208	0	1213	0	0
T209	0	844	0	0
T210	0	166	0	0
T211	187898	0	0	0
T212	857363	0	0	0
T213	37707	0	0	0
T214	186136	0	0	0
T215	9279	0	0	0
T216	249718	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	841859	0	0
T1	107764	429	0	0
T2	417384	0	0	0
T3	2171560	1980	0	0
T4	1253152	8827	0	0
T5	2566320	11	0	0
T9	735760	1053	0	0
T10	70112	40	0	0
T14	324036	46	0	0
T15	0	2376	0	0
T16	0	28	0	0
T18	0	5	0	0
T24	0	10536	0	0
T27	35208	0	0	0
T33	0	2	0	0
T37	1073940	427	0	0
T38	0	1162	0	0
T43	0	645	0	0
T50	0	5	0	0
T51	0	147	0	0
T52	0	18	0	0
T53	0	497	0	0
T54	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1534340917	0	0
T1	107764	71174	0	0
T2	417384	2720	0	0
T3	2171560	1221541	0	0
T4	1253152	1977663	0	0
T5	2566320	1038292	0	0
T9	735760	1604814	0	0
T10	70112	52878	0	0
T14	324036	96693	0	0
T27	35208	15528	0	0
T37	1073940	301790	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T195,T203
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704783609	1225	0	0
DisabledNoTrigBkwd_A	704783609	251587	0	0
DisabledNoTrigFwd_A	704783609	341380742	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1225	0	0
T22	142034	0	0	0
T46	657614	0	0	0
T87	11499	0	0	0
T119	738129	0	0	0
T194	2678	477	0	0
T195	3359	413	0	0
T203	0	335	0	0
T213	37707	0	0	0
T214	186136	0	0	0
T215	9279	0	0	0
T216	249718	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	251587	0	0
T1	26941	4	0	0
T2	104346	0	0	0
T3	542890	234	0	0
T4	313288	3104	0	0
T5	641580	0	0	0
T9	183940	298	0	0
T10	17528	40	0	0
T14	81009	1	0	0
T24	0	10536	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	0	748	0	0
T50	0	5	0	0
T51	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	341380742	0	0
T1	26941	19668	0	0
T2	104346	674	0	0
T3	542890	277306	0	0
T4	313288	106657	0	0
T5	641580	83482	0	0
T9	183940	105588	0	0
T10	17528	1618	0	0
T14	81009	2970	0	0
T27	8802	4121	0	0
T37	268485	11522	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T196,T197
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704783609	7272	0	0
DisabledNoTrigBkwd_A	704783609	186018	0	0
DisabledNoTrigFwd_A	704783609	410272155	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	7272	0	0
T12	76611	0	0	0
T13	229681	0	0	0
T33	310482	0	0	0
T34	612075	0	0	0
T44	6395	0	0	0
T54	2871	499	0	0
T75	46695	0	0	0
T79	92266	0	0	0
T196	0	1290	0	0
T197	0	845	0	0
T199	0	381	0	0
T200	0	1406	0	0
T204	0	601	0	0
T206	0	700	0	0
T207	0	1550	0	0
T211	187898	0	0	0
T212	857363	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	186018	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	1108	0	0
T4	313288	1890	0	0
T5	641580	7	0	0
T9	183940	232	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T33	0	2	0	0
T37	268485	1	0	0
T43	0	645	0	0
T51	0	55	0	0
T54	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	410272155	0	0
T1	26941	25146	0	0
T2	104346	678	0	0
T3	542890	231170	0	0
T4	313288	966219	0	0
T5	641580	239142	0	0
T9	183940	718652	0	0
T10	17528	17432	0	0
T14	81009	2977	0	0
T27	8802	5376	0	0
T37	268485	267103	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T201,T205
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704783609	3688	0	0
DisabledNoTrigBkwd_A	704783609	220944	0	0
DisabledNoTrigFwd_A	704783609	389920228	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	3688	0	0
T104	353732	0	0	0
T198	1078	307	0	0
T201	0	774	0	0
T205	0	1228	0	0
T208	0	1213	0	0
T210	0	166	0	0
T217	966232	0	0	0
T218	9908	0	0	0
T219	16021	0	0	0
T220	120326	0	0	0
T221	83967	0	0	0
T222	885231	0	0	0
T223	86747	0	0	0
T224	204443	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	220944	0	0
T1	26941	398	0	0
T2	104346	0	0	0
T3	542890	549	0	0
T4	313288	2845	0	0
T5	641580	0	0	0
T9	183940	330	0	0
T10	17528	0	0	0
T14	81009	45	0	0
T15	0	2376	0	0
T16	0	28	0	0
T27	8802	0	0	0
T37	268485	216	0	0
T51	0	44	0	0
T53	0	497	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	389920228	0	0
T1	26941	22778	0	0
T2	104346	682	0	0
T3	542890	318051	0	0
T4	313288	753325	0	0
T5	641580	600396	0	0
T9	183940	664028	0	0
T10	17528	16396	0	0
T14	81009	9789	0	0
T27	8802	4311	0	0
T37	268485	11572	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T193,T202
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	704783609	2042	0	0
DisabledNoTrigBkwd_A	704783609	183310	0	0
DisabledNoTrigFwd_A	704783609	392767792	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	2042	0	0
T11	88836	0	0	0
T16	128255	0	0	0
T18	48867	0	0	0
T24	652502	0	0	0
T25	106296	0	0	0
T33	310482	0	0	0
T43	162974	0	0	0
T52	1198	390	0	0
T53	257211	0	0	0
T54	2871	0	0	0
T193	0	349	0	0
T202	0	459	0	0
T209	0	844	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	183310	0	0
T1	26941	26	0	0
T2	104346	0	0	0
T3	542890	89	0	0
T4	313288	988	0	0
T5	641580	4	0	0
T9	183940	193	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T18	0	5	0	0
T27	8802	0	0	0
T37	268485	210	0	0
T38	0	414	0	0
T51	0	38	0	0
T52	0	18	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	392767792	0	0
T1	26941	3582	0	0
T2	104346	686	0	0
T3	542890	395014	0	0
T4	313288	151462	0	0
T5	641580	115272	0	0
T9	183940	116546	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	1720	0	0
T37	268485	11593	0	0