Unified Coverage Report :: Module :: alert_handler_ping_timer

Module : alert_handler_ping_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.35	91.94	89.19		50.00	90.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer	91.02	91.94	89.19		83.33	90.62	100.00

---

Module Instance : tb.dut.u_ping_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.02	91.94	89.19		83.33	90.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.46	94.12	87.18	98.97	83.33	91.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_buf_spurious_alert_ping	100.00	100.00
u_prim_buf_spurious_esc_ping	100.00	100.00
u_prim_count_cnt	98.08			98.08
u_prim_count_esc_cnt	88.89			88.89
u_prim_double_lfsr	87.50	100.00	50.00	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	57	91.94
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
ALWAYS	85	3	3	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	141	4	4	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
ALWAYS	331	37	32	86.49
ALWAYS	426	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
81	1	1
82	1	1
85	1	1
86	1	1
88	1	1
99	1	1
134	1	1
141	1	1
142	1	1
144	1	1
145	1	1
			MISSING_ELSE
152	1	1
156	1	1
196	1	1
233	1	1
234	1	1
264	1	1
265	1	1
268	1	1
278	1	1
279	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
339	1	1
341	1	1
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
			MISSING_ELSE
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
			MISSING_ELSE
			MISSING_ELSE
399	0	1
400	0	1
412	1	1
413	0	1
414	0	1
415	0	1
			MISSING_ELSE
426	3	3

---

Cond Coverage for Module : alert_handler_ping_timer

	Total	Covered	Percent
Conditions	37	33	89.19
Logical	37	33	89.19
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       81
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       134
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION ((esc_cnt >= 2'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ---------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       233
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       268
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       365
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Covered	T3,T37,T38
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T5,T37,T53

 LINE       385
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T5,T16,T33

 LINE       412
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

FSM Coverage for Module : alert_handler_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	5	83.33	(Not included in score)
Transitions	10	5	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt	347	Covered	T2,T3,T4
EscPingSt	376	Covered	T2,T3,T4
EscWaitSt	366	Covered	T2,T3,T4
FsmErrorSt	413	Not Covered
InitSt	345	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertPingSt->EscWaitSt	366	Covered	T2,T3,T4
AlertPingSt->FsmErrorSt	413	Not Covered
AlertWaitSt->AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt->FsmErrorSt	413	Not Covered
EscPingSt->AlertWaitSt	386	Covered	T2,T3,T4
EscPingSt->FsmErrorSt	413	Not Covered
EscWaitSt->EscPingSt	376	Covered	T2,T3,T4
EscWaitSt->FsmErrorSt	413	Not Covered
InitSt->AlertWaitSt	347	Covered	T2,T3,T4
InitSt->FsmErrorSt	413	Not Covered

---

Branch Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	29	90.62
TERNARY	78	3	3	100.00
TERNARY	99	2	2	100.00
TERNARY	134	2	2	100.00
TERNARY	268	2	2	100.00
IF	85	2	2	100.00
IF	141	3	3	100.00
CASE	341	14	12	85.71
IF	412	2	1	50.00
IF	426	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	((reseed_timer_q > '0)) ? 
-2-:	78	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	134	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	144	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	case (state_q)
-2-:	346	if (en_i)
-3-:	353	if (timer_expired)
-4-:	365	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	368	if (timer_expired)
-6-:	375	if (timer_expired)
-7-:	385	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	389	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T2,T3,T4
AlertWaitSt	-	0	-	-	-	-	-	Covered	T2,T3,T4
AlertPingSt	-	-	1	1	-	-	-	Covered	T5,T37,T53
AlertPingSt	-	-	1	0	-	-	-	Covered	T2,T3,T4
AlertPingSt	-	-	0	-	-	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	1	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	0	-	-	Covered	T2,T3,T4
EscPingSt	-	-	-	-	-	1	1	Covered	T5,T16,T33
EscPingSt	-	-	-	-	-	1	0	Covered	T2,T3,T4
EscPingSt	-	-	-	-	-	0	-	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	412	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	704783609	187767	0	0
EscPingOH_A	704783609	131277	0	0
MaxIdDw_A	622	622	0	0
PingOH0_A	704783609	704712947	0	0
WaitCycMaskIsRightAlignedMask_A	704783609	704712947	0	0
WaitCycMaskMin_A	704783609	704712947	0	0
u_state_regs_A	704783609	704712947	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	187767	0	0
T2	104346	3778	0	0
T3	542890	5	0	0
T4	313288	137	0	0
T5	641580	3696	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T15	0	169	0	0
T27	8802	0	0	0
T35	0	3418	0	0
T36	0	3209	0	0
T37	268485	234	0	0
T38	159887	26	0	0
T53	0	464	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	131277	0	0
T2	104346	3730	0	0
T3	542890	10	0	0
T4	313288	85	0	0
T5	641580	1878	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T15	0	120	0	0
T27	8802	0	0	0
T35	0	3400	0	0
T36	0	3195	0	0
T37	268485	200	0	0
T38	159887	110	0	0
T53	0	200	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622	622	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T27	1	1	0	0
T37	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

Line Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	57	91.94
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
ALWAYS	85	3	3	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	141	4	4	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
ALWAYS	331	37	32	86.49
ALWAYS	426	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
81	1	1
82	1	1
85	1	1
86	1	1
88	1	1
99	1	1
134	1	1
141	1	1
142	1	1
144	1	1
145	1	1
			MISSING_ELSE
152	1	1
156	1	1
196	1	1
233	1	1
234	1	1
264	1	1
265	1	1
268	1	1
278	1	1
279	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
339	1	1
341	1	1
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
			MISSING_ELSE
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
			MISSING_ELSE
			MISSING_ELSE
399	0	1
400	0	1
412	1	1
413	0	1
414	0	1
415	0	1
			MISSING_ELSE
426	3	3

---

Cond Coverage for Instance : tb.dut.u_ping_timer

	Total	Covered	Percent
Conditions	37	33	89.19
Logical	37	33	89.19
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       81
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       134
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       196
 EXPRESSION ((esc_cnt >= 2'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ---------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       233
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       268
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       365
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Covered	T3,T37,T38
0	1	0	Covered	T2,T3,T4
1	0	0	Covered	T5,T37,T53

 LINE       385
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T5,T16,T33

 LINE       412
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	5	83.33	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt	347	Covered	T2,T3,T4
EscPingSt	376	Covered	T2,T3,T4
EscWaitSt	366	Covered	T2,T3,T4
FsmErrorSt	413	Not Covered
InitSt	345	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AlertPingSt->EscWaitSt	366	Covered	T2,T3,T4
AlertPingSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
AlertWaitSt->AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt->FsmErrorSt	413	Not Covered
EscPingSt->AlertWaitSt	386	Covered	T2,T3,T4
EscPingSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
EscWaitSt->EscPingSt	376	Covered	T2,T3,T4
EscWaitSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
InitSt->AlertWaitSt	347	Covered	T2,T3,T4
InitSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.

---

Branch Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	29	90.62
TERNARY	78	3	3	100.00
TERNARY	99	2	2	100.00
TERNARY	134	2	2	100.00
TERNARY	268	2	2	100.00
IF	85	2	2	100.00
IF	141	3	3	100.00
CASE	341	14	12	85.71
IF	412	2	1	50.00
IF	426	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	((reseed_timer_q > '0)) ? 
-2-:	78	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	134	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	144	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	case (state_q)
-2-:	346	if (en_i)
-3-:	353	if (timer_expired)
-4-:	365	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	368	if (timer_expired)
-6-:	375	if (timer_expired)
-7-:	385	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	389	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T2,T3,T4
AlertWaitSt	-	0	-	-	-	-	-	Covered	T2,T3,T4
AlertPingSt	-	-	1	1	-	-	-	Covered	T5,T37,T53
AlertPingSt	-	-	1	0	-	-	-	Covered	T2,T3,T4
AlertPingSt	-	-	0	-	-	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	1	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	0	-	-	Covered	T2,T3,T4
EscPingSt	-	-	-	-	-	1	1	Covered	T5,T16,T33
EscPingSt	-	-	-	-	-	1	0	Covered	T2,T3,T4
EscPingSt	-	-	-	-	-	0	-	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	412	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	704783609	187767	0	0
EscPingOH_A	704783609	131277	0	0
MaxIdDw_A	622	622	0	0
PingOH0_A	704783609	704712947	0	0
WaitCycMaskIsRightAlignedMask_A	704783609	704712947	0	0
WaitCycMaskMin_A	704783609	704712947	0	0
u_state_regs_A	704783609	704712947	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	187767	0	0
T2	104346	3778	0	0
T3	542890	5	0	0
T4	313288	137	0	0
T5	641580	3696	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T15	0	169	0	0
T27	8802	0	0	0
T35	0	3418	0	0
T36	0	3209	0	0
T37	268485	234	0	0
T38	159887	26	0	0
T53	0	464	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	131277	0	0
T2	104346	3730	0	0
T3	542890	10	0	0
T4	313288	85	0	0
T5	641580	1878	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T15	0	120	0	0
T27	8802	0	0	0
T35	0	3400	0	0
T36	0	3195	0	0
T37	268485	200	0	0
T38	159887	110	0	0
T53	0	200	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	622	622	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0
T27	1	1	0	0
T37	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0