Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.69	96.04	76.60		65.00	88.46	82.35

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[3].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[0].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35
tb.dut.gen_classes[2].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.42	100.00		97.39			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T5
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T3,T4,T9

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T9
0	1	Covered	T3,T4,T24
1	0	Covered	T10,T39,T40

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T9
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T39,T40

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T9
1	0	Covered	T41,T42
1	1	Covered	T3,T4,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	20	13	65.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T4,T9

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T9
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T9,T40
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T3,T39,T40
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T10,T43
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T44,T45,T46
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T4,T9
TimeoutSt->Phase0St	172	Covered	T3,T4,T10

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T10
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T40,T47
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T40,T48
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T43,T49
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T44,T45,T46
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	0	0	0
CheckAccumTrig0_A	2147483647	2275	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1033	0	0
CheckEn_A	2147483647	1142645939	0	0
CheckPhase0_A	2147483647	2584	0	0
CheckPhase1_A	2147483647	2529	0	0
CheckPhase2_A	2147483647	2474	0	0
CheckPhase3_A	2147483647	2423	0	0
CheckTimeout0_A	2147483647	7544	0	0
CheckTimeoutSt1_A	2147483647	916655	0	0
CheckTimeoutSt2_A	2147483647	7163	0	0
CheckTimeoutStTrig_A	2147483647	249	0	0
ErrorStAllEscAsserted_A	2147483647	0	0	0
ErrorStIsTerminal_A	2147483647	0	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2275	0	0
T1	107764	4	0	0
T2	417384	0	0	0
T3	2171560	12	0	0
T4	1253152	22	0	0
T5	2566320	2	0	0
T9	735760	19	0	0
T10	70112	2	0	0
T14	324036	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T18	0	1	0	0
T24	0	3	0	0
T27	35208	0	0	0
T33	0	1	0	0
T37	1073940	3	0	0
T38	0	2	0	0
T43	0	4	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T10	17528	1	0	0
T14	81009	0	0	0
T15	157040	0	0	0
T17	212008	0	0	0
T19	123184	0	0	0
T20	0	2	0	0
T26	0	1	0	0
T35	33014	0	0	0
T36	31985	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	348192	4	0	0
T40	767266	1	0	0
T45	0	2	0	0
T48	82640	0	0	0
T49	156822	0	0	0
T50	10350	0	0	0
T51	78179	0	0	0
T52	1198	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	3	0	0
T68	0	4	0	0
T69	0	1	0	0
T70	22038	0	0	0
T71	76636	0	0	0
T72	48798	0	0	0
T73	587318	0	0	0
T74	851681	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1033	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	1628670	2	0	0
T4	939864	11	0	0
T5	1924740	0	0	0
T9	735760	6	0	0
T10	70112	2	0	0
T11	0	3	0	0
T13	0	2	0	0
T14	324036	0	0	0
T15	157040	0	0	0
T16	0	1	0	0
T24	0	1	0	0
T27	35208	0	0	0
T34	0	2	0	0
T35	33014	0	0	0
T37	1073940	0	0	0
T38	479661	0	0	0
T39	0	2	0	0
T40	0	6	0	0
T43	0	4	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	31050	0	0	0
T51	78179	0	0	0
T73	0	1	0	0
T75	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	6	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1142645939	0	0
T1	107764	31692	0	0
T2	417384	2716	0	0
T3	2171560	1112039	0	0
T4	1253152	1726728	0	0
T5	2566320	1038291	0	0
T9	735760	2755878	0	0
T10	70112	51839	0	0
T14	324036	96692	0	0
T27	35208	15525	0	0
T37	1073940	46240	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T1	107764	4	0	0
T2	417384	0	0	0
T3	2171560	21	0	0
T4	1253152	24	0	0
T5	2566320	2	0	0
T9	735760	18	0	0
T10	70112	3	0	0
T14	324036	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T24	0	5	0	0
T27	35208	0	0	0
T33	0	1	0	0
T37	1073940	3	0	0
T38	0	2	0	0
T43	0	4	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2529	0	0
T1	107764	4	0	0
T2	417384	0	0	0
T3	2171560	20	0	0
T4	1253152	24	0	0
T5	2566320	2	0	0
T9	735760	18	0	0
T10	70112	3	0	0
T14	324036	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T24	0	5	0	0
T27	35208	0	0	0
T33	0	1	0	0
T37	1073940	3	0	0
T38	0	2	0	0
T43	0	4	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T1	107764	4	0	0
T2	417384	0	0	0
T3	2171560	19	0	0
T4	1253152	24	0	0
T5	2566320	2	0	0
T9	735760	18	0	0
T10	70112	2	0	0
T14	324036	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T24	0	5	0	0
T27	35208	0	0	0
T33	0	1	0	0
T37	1073940	3	0	0
T38	0	2	0	0
T43	0	3	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T1	107764	4	0	0
T2	417384	0	0	0
T3	2171560	19	0	0
T4	1253152	24	0	0
T5	2566320	2	0	0
T9	735760	18	0	0
T10	70112	2	0	0
T14	324036	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T24	0	5	0	0
T27	35208	0	0	0
T33	0	1	0	0
T37	1073940	3	0	0
T38	0	2	0	0
T43	0	3	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7544	0	0
T3	2171560	112	0	0
T4	1253152	372	0	0
T5	2566320	0	0	0
T9	735760	2	0	0
T10	70112	1	0	0
T13	0	7	0	0
T14	324036	0	0	0
T15	0	1	0	0
T19	0	1	0	0
T20	0	40	0	0
T24	0	111	0	0
T25	0	10	0	0
T27	35208	2	0	0
T28	0	47	0	0
T34	0	1	0	0
T37	1073940	0	0	0
T38	639548	0	0	0
T39	0	11	0	0
T40	0	1	0	0
T48	0	1	0	0
T50	41400	3	0	0
T51	0	1	0	0
T78	0	9	0	0
T79	0	7	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	916655	0	0
T3	2171560	30501	0	0
T4	1253152	31234	0	0
T5	2566320	0	0	0
T9	735760	457	0	0
T10	70112	0	0	0
T13	0	4173	0	0
T14	324036	0	0	0
T15	0	123	0	0
T19	0	404	0	0
T20	0	5300	0	0
T24	0	18545	0	0
T25	0	1894	0	0
T27	35208	201	0	0
T28	0	1828	0	0
T34	0	145	0	0
T37	1073940	0	0	0
T38	639548	0	0	0
T39	0	418	0	0
T40	0	191	0	0
T48	0	56	0	0
T50	41400	1372	0	0
T51	0	420	0	0
T73	0	29	0	0
T78	0	1605	0	0
T79	0	1063	0	0
T80	0	88	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7163	0	0
T3	2171560	146	0	0
T4	1253152	501	0	0
T5	2566320	0	0	0
T9	735760	2	0	0
T10	70112	0	0	0
T13	0	17	0	0
T14	324036	0	0	0
T15	0	1	0	0
T20	0	59	0	0
T24	0	279	0	0
T25	0	10	0	0
T27	35208	4	0	0
T28	0	47	0	0
T34	0	1	0	0
T37	1073940	0	0	0
T38	639548	0	0	0
T39	0	8	0	0
T50	41400	3	0	0
T51	0	3	0	0
T73	0	1	0	0
T78	0	4	0	0
T79	0	7	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	0	3	0	0
T83	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	249	0	0
T3	2171560	9	0	0
T4	1253152	3	0	0
T5	2566320	0	0	0
T9	735760	0	0	0
T10	70112	0	0	0
T13	0	1	0	0
T14	324036	0	0	0
T19	0	2	0	0
T21	0	1	0	0
T24	0	2	0	0
T26	0	3	0	0
T27	35208	0	0	0
T37	1073940	0	0	0
T38	639548	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T50	41400	0	0	0
T55	0	4	0	0
T59	0	3	0	0
T60	0	2	0	0
T62	0	1	0	0
T65	0	1	0	0
T78	0	5	0	0
T83	0	6	0	0
T84	0	1	0	0
T85	0	4	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107764	107504	0	0
T2	417384	416696	0	0
T3	2171560	2171456	0	0
T4	1253152	1253104	0	0
T5	2566320	2565960	0	0
T9	735760	735712	0	0
T10	70112	69728	0	0
T14	324036	323828	0	0
T27	35208	34896	0	0
T37	1073940	1073908	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	107764	107504	0	0
T2	417384	416696	0	0
T3	2171560	2171456	0	0
T4	1253152	1253104	0	0
T5	2566320	2565960	0	0
T9	735760	735712	0	0
T10	70112	69728	0	0
T14	324036	323828	0	0
T27	35208	34896	0	0
T37	1073940	1073908	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T5,T14
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T3,T4,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T24
0	1	Covered	T3,T78,T48
1	0	Covered	T39,T40,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T39,T40,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T24
1	0	Not Covered
1	1	Covered	T3,T78,T48

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T37

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T4,T34

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T9,T43

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T4,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T40,T28,T30
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T39,T48
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T43,T49,T45
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T46,T89,T90
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T24
TimeoutSt->Phase0St	172	Covered	T3,T78,T39

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T78,T39
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T40,T30,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T39,T48,T20
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T43,T49,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T46,T89,T90
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704783609	0	0	0
CheckAccumTrig0_A	704783609	488	0	0
CheckAccumTrig1_A	704783609	33	0	0
CheckClr_A	704783609	221	0	0
CheckEn_A	704783609	291374426	0	0
CheckPhase0_A	704783609	566	0	0
CheckPhase1_A	704783609	550	0	0
CheckPhase2_A	704783609	536	0	0
CheckPhase3_A	704783609	529	0	0
CheckTimeout0_A	704783609	1634	0	0
CheckTimeoutSt1_A	704783609	200036	0	0
CheckTimeoutSt2_A	704783609	1541	0	0
CheckTimeoutStTrig_A	704783609	58	0	0
ErrorStAllEscAsserted_A	704783609	0	0	0
ErrorStIsTerminal_A	704783609	0	0	0
EscStateOut_A	704783609	704712947	0	0
u_state_regs_A	704783609	704712947	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	488	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	5	0	0
T4	313288	7	0	0
T5	641580	1	0	0
T9	183940	3	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T33	0	1	0	0
T37	268485	1	0	0
T43	0	4	0	0
T51	0	1	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	33	0	0
T17	106004	0	0	0
T19	61592	0	0	0
T20	0	1	0	0
T39	174096	3	0	0
T40	383633	1	0	0
T48	41320	0	0	0
T49	78411	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	11019	0	0	0
T71	38318	0	0	0
T72	24399	0	0	0
T73	293659	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	221	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	1	0	0
T4	313288	3	0	0
T5	641580	0	0	0
T9	183940	1	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T34	0	2	0	0
T37	268485	0	0	0
T39	0	2	0	0
T40	0	5	0	0
T43	0	3	0	0
T48	0	1	0	0
T78	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	291374426	0	0
T1	26941	24464	0	0
T2	104346	677	0	0
T3	542890	123312	0	0
T4	313288	966214	0	0
T5	641580	239142	0	0
T9	183940	708828	0	0
T10	17528	17431	0	0
T14	81009	2977	0	0
T27	8802	5375	0	0
T37	268485	11553	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	566	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	7	0	0
T4	313288	7	0	0
T5	641580	1	0	0
T9	183940	3	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T33	0	1	0	0
T37	268485	1	0	0
T43	0	4	0	0
T51	0	1	0	0
T54	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	550	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	6	0	0
T4	313288	7	0	0
T5	641580	1	0	0
T9	183940	3	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T33	0	1	0	0
T37	268485	1	0	0
T43	0	4	0	0
T51	0	1	0	0
T54	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	536	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	6	0	0
T4	313288	7	0	0
T5	641580	1	0	0
T9	183940	3	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T33	0	1	0	0
T37	268485	1	0	0
T43	0	3	0	0
T51	0	1	0	0
T54	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	529	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	6	0	0
T4	313288	7	0	0
T5	641580	1	0	0
T9	183940	3	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T27	8802	0	0	0
T33	0	1	0	0
T37	268485	1	0	0
T43	0	3	0	0
T51	0	1	0	0
T54	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1634	0	0
T3	542890	9	0	0
T4	313288	174	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	108	0	0
T25	0	9	0	0
T27	8802	0	0	0
T34	0	1	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	7	0	0
T40	0	1	0	0
T48	0	1	0	0
T50	10350	0	0	0
T78	0	7	0	0
T79	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	200036	0	0
T3	542890	1525	0	0
T4	313288	10245	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	7509	0	0
T25	0	1755	0	0
T27	8802	0	0	0
T34	0	145	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	269	0	0
T40	0	4	0	0
T48	0	56	0	0
T50	10350	0	0	0
T78	0	833	0	0
T79	0	1063	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1541	0	0
T3	542890	7	0	0
T4	313288	174	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T20	0	19	0	0
T24	0	108	0	0
T25	0	9	0	0
T27	8802	0	0	0
T34	0	1	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	4	0	0
T50	10350	0	0	0
T78	0	2	0	0
T79	0	7	0	0
T82	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	58	0	0
T3	542890	2	0	0
T4	313288	0	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T48	0	1	0	0
T50	10350	0	0	0
T55	0	1	0	0
T78	0	4	0	0
T83	0	3	0	0
T85	0	2	0	0
T86	0	1	0	0
T87	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T3,T4,T9
1	1	1	Covered	T3,T4,T27

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T27
0	1	Covered	T3,T4,T24
1	0	Covered	T74,T89,T92

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T74,T89,T92

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T27
1	0	Not Covered
1	1	Covered	T3,T4,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T9,T52

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T4,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T51,T18,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T5,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T4,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T27
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T83,T93,T94
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T93,T95,T96
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T83,T46,T90
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T64,T97,T98
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T9
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T27
TimeoutSt->Phase0St	172	Covered	T3,T4,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T94,T99,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T93,T96,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T83,T46,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T64,T97,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T9,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704783609	0	0	0
CheckAccumTrig0_A	704783609	426	0	0
CheckAccumTrig1_A	704783609	16	0	0
CheckClr_A	704783609	156	0	0
CheckEn_A	704783609	317884624	0	0
CheckPhase0_A	704783609	496	0	0
CheckPhase1_A	704783609	491	0	0
CheckPhase2_A	704783609	488	0	0
CheckPhase3_A	704783609	481	0	0
CheckTimeout0_A	704783609	3005	0	0
CheckTimeoutSt1_A	704783609	343685	0	0
CheckTimeoutSt2_A	704783609	2927	0	0
CheckTimeoutStTrig_A	704783609	59	0	0
ErrorStAllEscAsserted_A	704783609	0	0	0
ErrorStIsTerminal_A	704783609	0	0	0
EscStateOut_A	704783609	704712947	0	0
u_state_regs_A	704783609	704712947	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	426	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	1	0	0
T4	313288	1	0	0
T5	641580	1	0	0
T9	183940	4	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T18	0	1	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T38	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	16	0	0
T20	424972	0	0	0
T28	214885	0	0	0
T47	104261	0	0	0
T74	851681	1	0	0
T89	0	1	0	0
T92	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	22916	0	0	0
T110	111167	0	0	0
T111	46314	0	0	0
T112	497528	0	0	0
T113	143518	0	0	0
T114	95081	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	156	0	0
T3	542890	1	0	0
T4	313288	0	0	0
T5	641580	0	0	0
T9	183940	1	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T19	0	2	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T40	0	1	0	0
T50	10350	0	0	0
T74	0	1	0	0
T81	0	1	0	0
T83	0	2	0	0
T111	0	1	0	0
T113	0	1	0	0
T115	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	317884624	0	0
T1	26941	594	0	0
T2	104346	685	0	0
T3	542890	395014	0	0
T4	313288	119243	0	0
T5	641580	115272	0	0
T9	183940	765528	0	0
T10	17528	17431	0	0
T14	81009	80956	0	0
T27	8802	1719	0	0
T37	268485	11593	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	496	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	3	0	0
T4	313288	2	0	0
T5	641580	1	0	0
T9	183940	4	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T38	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	491	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	3	0	0
T4	313288	2	0	0
T5	641580	1	0	0
T9	183940	4	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T38	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	488	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	3	0	0
T4	313288	2	0	0
T5	641580	1	0	0
T9	183940	4	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T38	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	481	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	3	0	0
T4	313288	2	0	0
T5	641580	1	0	0
T9	183940	4	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T38	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	3005	0	0
T3	542890	43	0	0
T4	313288	132	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	7	0	0
T14	81009	0	0	0
T24	0	170	0	0
T27	8802	2	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	10350	0	0	0
T51	0	2	0	0
T73	0	1	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	343685	0	0
T3	542890	9280	0	0
T4	313288	7935	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	1966	0	0
T14	81009	0	0	0
T24	0	10769	0	0
T27	8802	88	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	49	0	0
T40	0	187	0	0
T50	10350	0	0	0
T51	0	278	0	0
T73	0	29	0	0
T78	0	349	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	2927	0	0
T3	542890	41	0	0
T4	313288	131	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	6	0	0
T14	81009	0	0	0
T24	0	169	0	0
T27	8802	2	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	1	0	0
T50	10350	0	0	0
T51	0	2	0	0
T73	0	1	0	0
T78	0	1	0	0
T81	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	59	0	0
T3	542890	2	0	0
T4	313288	1	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	1	0	0
T14	81009	0	0	0
T20	0	2	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T40	0	1	0	0
T50	10350	0	0	0
T55	0	1	0	0
T83	0	2	0	0
T109	0	1	0	0
T116	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T37,T14
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T3,T4,T9

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T9
0	1	Covered	T3,T24,T78
1	0	Covered	T10,T20,T55

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T9
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T10,T20,T55

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T9
1	0	Covered	T41
1	1	Covered	T3,T24,T78

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T9
1	Covered	T1,T3,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T4,T9

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T9
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T9,T40
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T117,T45,T118
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T10,T20
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T44,T45,T64
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T9
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T9
TimeoutSt->Phase0St	172	Covered	T3,T10,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T9
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T40,T66
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T117,T45,T118
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T20,T119
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T44,T45,T64
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704783609	0	0	0
CheckAccumTrig0_A	704783609	867	0	0
CheckAccumTrig1_A	704783609	45	0	0
CheckClr_A	704783609	425	0	0
CheckEn_A	704783609	237215565	0	0
CheckPhase0_A	704783609	960	0	0
CheckPhase1_A	704783609	936	0	0
CheckPhase2_A	704783609	914	0	0
CheckPhase3_A	704783609	890	0	0
CheckTimeout0_A	704783609	1326	0	0
CheckTimeoutSt1_A	704783609	161440	0	0
CheckTimeoutSt2_A	704783609	1204	0	0
CheckTimeoutStTrig_A	704783609	77	0	0
ErrorStAllEscAsserted_A	704783609	0	0	0
ErrorStIsTerminal_A	704783609	0	0	0
EscStateOut_A	704783609	704712947	0	0
u_state_regs_A	704783609	704712947	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	867	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	4	0	0
T4	313288	13	0	0
T5	641580	0	0	0
T9	183940	7	0	0
T10	17528	2	0	0
T14	81009	1	0	0
T24	0	3	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	45	0	0
T10	17528	1	0	0
T14	81009	0	0	0
T15	157040	0	0	0
T20	0	1	0	0
T35	33014	0	0	0
T36	31985	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T50	10350	0	0	0
T51	78179	0	0	0
T52	1198	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T60	0	3	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	425	0	0
T3	542890	1	0	0
T4	313288	8	0	0
T5	641580	0	0	0
T9	183940	3	0	0
T10	17528	2	0	0
T11	0	3	0	0
T13	0	1	0	0
T14	81009	0	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T50	10350	0	0	0
T75	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	237215565	0	0
T1	26941	3313	0	0
T2	104346	673	0	0
T3	542890	275662	0	0
T4	313288	106656	0	0
T5	641580	83482	0	0
T9	183940	633431	0	0
T10	17528	582	0	0
T14	81009	2970	0	0
T27	8802	4121	0	0
T37	268485	11522	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	960	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	7	0	0
T4	313288	12	0	0
T5	641580	0	0	0
T9	183940	6	0	0
T10	17528	3	0	0
T14	81009	1	0	0
T24	0	4	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	936	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	7	0	0
T4	313288	12	0	0
T5	641580	0	0	0
T9	183940	6	0	0
T10	17528	3	0	0
T14	81009	1	0	0
T24	0	4	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	914	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	6	0	0
T4	313288	12	0	0
T5	641580	0	0	0
T9	183940	6	0	0
T10	17528	2	0	0
T14	81009	1	0	0
T24	0	4	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	890	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	6	0	0
T4	313288	12	0	0
T5	641580	0	0	0
T9	183940	6	0	0
T10	17528	2	0	0
T14	81009	1	0	0
T24	0	4	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1326	0	0
T3	542890	56	0	0
T4	313288	178	0	0
T5	641580	0	0	0
T9	183940	2	0	0
T10	17528	1	0	0
T14	81009	0	0	0
T15	0	1	0	0
T24	0	3	0	0
T25	0	1	0	0
T27	8802	2	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T50	10350	1	0	0
T51	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	161440	0	0
T3	542890	10626	0	0
T4	313288	11276	0	0
T5	641580	0	0	0
T9	183940	457	0	0
T10	17528	0	0	0
T13	0	663	0	0
T14	81009	0	0	0
T15	0	123	0	0
T24	0	267	0	0
T25	0	139	0	0
T27	8802	113	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T50	10350	498	0	0
T51	0	142	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1204	0	0
T3	542890	53	0	0
T4	313288	178	0	0
T5	641580	0	0	0
T9	183940	2	0	0
T10	17528	0	0	0
T13	0	4	0	0
T14	81009	0	0	0
T15	0	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	8802	2	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T50	10350	1	0	0
T51	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	77	0	0
T3	542890	3	0	0
T4	313288	0	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T24	0	1	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T45	0	1	0	0
T50	10350	0	0	0
T55	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T78	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T9
1	1	0	Covered	T3,T4,T9
1	1	1	Covered	T3,T4,T50

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T50
0	1	Covered	T3,T4,T19
1	0	Covered	T39,T45,T59

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T50
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T39,T45,T59

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T50
1	0	Covered	T42
1	1	Covered	T3,T4,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T4,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T14,T80

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T9,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T9
1	Covered	T1,T3,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T9

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T4,T50

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T50
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T47,T26,T30
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T26,T120
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T45,T121,T122
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T46,T60,T30
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T9
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T50
TimeoutSt->Phase0St	172	Covered	T3,T4,T39

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T50
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T39
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T50
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T50
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T47,T26,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T26,T120
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T45,T121,T122
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T46,T60,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T16,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	704783609	0	0	0
CheckAccumTrig0_A	704783609	494	0	0
CheckAccumTrig1_A	704783609	31	0	0
CheckClr_A	704783609	231	0	0
CheckEn_A	704783609	296171324	0	0
CheckPhase0_A	704783609	562	0	0
CheckPhase1_A	704783609	552	0	0
CheckPhase2_A	704783609	536	0	0
CheckPhase3_A	704783609	523	0	0
CheckTimeout0_A	704783609	1579	0	0
CheckTimeoutSt1_A	704783609	211494	0	0
CheckTimeoutSt2_A	704783609	1491	0	0
CheckTimeoutStTrig_A	704783609	55	0	0
ErrorStAllEscAsserted_A	704783609	0	0	0
ErrorStIsTerminal_A	704783609	0	0	0
EscStateOut_A	704783609	704712947	0	0
u_state_regs_A	704783609	704712947	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	494	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	2	0	0
T4	313288	1	0	0
T5	641580	0	0	0
T9	183940	5	0	0
T10	17528	0	0	0
T14	81009	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	31	0	0
T17	106004	0	0	0
T19	61592	0	0	0
T26	0	1	0	0
T30	0	1	0	0
T39	174096	1	0	0
T40	383633	0	0	0
T45	0	2	0	0
T48	41320	0	0	0
T49	78411	0	0	0
T59	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T70	11019	0	0	0
T71	38318	0	0	0
T72	24399	0	0	0
T73	293659	0	0	0
T123	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	231	0	0
T9	183940	2	0	0
T10	17528	0	0	0
T13	0	1	0	0
T14	81009	0	0	0
T15	157040	0	0	0
T16	0	1	0	0
T27	8802	0	0	0
T35	33014	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T40	0	1	0	0
T45	0	5	0	0
T47	0	1	0	0
T50	10350	0	0	0
T51	78179	0	0	0
T73	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	296171324	0	0
T1	26941	3321	0	0
T2	104346	681	0	0
T3	542890	318051	0	0
T4	313288	534615	0	0
T5	641580	600395	0	0
T9	183940	648091	0	0
T10	17528	16395	0	0
T14	81009	9789	0	0
T27	8802	4310	0	0
T37	268485	11572	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	562	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	4	0	0
T4	313288	3	0	0
T5	641580	0	0	0
T9	183940	5	0	0
T10	17528	0	0	0
T14	81009	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	552	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	4	0	0
T4	313288	3	0	0
T5	641580	0	0	0
T9	183940	5	0	0
T10	17528	0	0	0
T14	81009	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	536	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	4	0	0
T4	313288	3	0	0
T5	641580	0	0	0
T9	183940	5	0	0
T10	17528	0	0	0
T14	81009	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	523	0	0
T1	26941	1	0	0
T2	104346	0	0	0
T3	542890	4	0	0
T4	313288	3	0	0
T5	641580	0	0	0
T9	183940	5	0	0
T10	17528	0	0	0
T14	81009	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T27	8802	0	0	0
T37	268485	1	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1579	0	0
T3	542890	47	0	0
T4	313288	20	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	7	0	0
T14	81009	0	0	0
T19	0	1	0	0
T20	0	40	0	0
T27	8802	0	0	0
T28	0	47	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	4	0	0
T50	10350	2	0	0
T78	0	2	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	211494	0	0
T3	542890	9070	0	0
T4	313288	1778	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	1544	0	0
T14	81009	0	0	0
T19	0	404	0	0
T20	0	5300	0	0
T27	8802	0	0	0
T28	0	1828	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	100	0	0
T50	10350	874	0	0
T78	0	423	0	0
T80	0	88	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	1491	0	0
T3	542890	45	0	0
T4	313288	18	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T13	0	7	0	0
T14	81009	0	0	0
T20	0	40	0	0
T27	8802	0	0	0
T28	0	47	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T39	0	3	0	0
T50	10350	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T83	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	55	0	0
T3	542890	2	0	0
T4	313288	2	0	0
T5	641580	0	0	0
T9	183940	0	0	0
T10	17528	0	0	0
T14	81009	0	0	0
T19	0	1	0	0
T26	0	3	0	0
T27	8802	0	0	0
T37	268485	0	0	0
T38	159887	0	0	0
T50	10350	0	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	704783609	704712947	0	0
T1	26941	26876	0	0
T2	104346	104174	0	0
T3	542890	542864	0	0
T4	313288	313276	0	0
T5	641580	641490	0	0
T9	183940	183928	0	0
T10	17528	17432	0	0
T14	81009	80957	0	0
T27	8802	8724	0	0
T37	268485	268477	0	0