Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.27	100.00	100.00	81.08			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	81.08			81.08

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.27	100.00	100.00	81.08			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	81.08			81.08

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T201,T202
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16515	0	0
DisabledNoTrigBkwd_A	2147483647	749407	0	0
DisabledNoTrigFwd_A	2147483647	1449541810	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16515	0	0
T9	446214	0	0	0
T19	302224	0	0	0
T70	411671	0	0	0
T113	72308	0	0	0
T200	0	1584	0	0
T201	3856	837	0	0
T202	0	747	0	0
T203	3451	1083	0	0
T204	4018	1108	0	0
T205	0	1506	0	0
T206	0	1309	0	0
T207	3490	945	0	0
T208	0	673	0	0
T209	0	159	0	0
T210	0	754	0	0
T211	0	207	0	0
T212	0	980	0	0
T213	0	701	0	0
T214	0	614	0	0
T215	0	1468	0	0
T216	0	419	0	0
T217	0	357	0	0
T218	0	799	0	0
T219	0	265	0	0
T220	104426	0	0	0
T221	340749	0	0	0
T222	10254	0	0	0
T223	46032	0	0	0
T224	2381	0	0	0
T225	5543	0	0	0
T226	11146	0	0	0
T227	29352	0	0	0
T228	485565	0	0	0
T229	555029	0	0	0
T230	87161	0	0	0
T231	112432	0	0	0
T232	34704	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	749407	0	0
T1	1204278	1085	0	0
T2	236118	90	0	0
T3	2994171	8	0	0
T4	3050060	6319	0	0
T5	0	6749	0	0
T6	106971	2256	0	0
T7	419024	83	0	0
T8	275076	53	0	0
T13	0	4	0	0
T15	255453	166	0	0
T21	0	156	0	0
T37	452073	319	0	0
T42	0	1436	0	0
T55	284064	42	0	0
T56	102932	159	0	0
T57	159476	37	0	0
T58	187064	50	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449541810	0	0
T1	1605704	1792520	0	0
T2	314824	243073	0	0
T3	3992228	2932348	0	0
T4	3050060	1476138	0	0
T7	419024	160381	0	0
T8	275076	153393	0	0
T55	284064	143923	0	0
T56	102932	21308	0	0
T57	159476	103942	0	0
T58	187064	113246	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	664374816	945	0	0
DisabledNoTrigBkwd_A	664374816	215377	0	0
DisabledNoTrigFwd_A	664374816	309738490	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	945	0	0
T19	302224	0	0	0
T207	3490	945	0	0
T225	5543	0	0	0
T226	11146	0	0	0
T227	29352	0	0	0
T228	485565	0	0	0
T229	555029	0	0	0
T230	87161	0	0	0
T231	112432	0	0	0
T232	34704	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	215377	0	0
T1	401426	104	0	0
T2	78706	90	0	0
T3	998057	8	0	0
T4	762515	4912	0	0
T7	104756	31	0	0
T8	68769	21	0	0
T55	71016	42	0	0
T56	25733	16	0	0
T57	39869	37	0	0
T58	46766	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	309738490	0	0
T1	401426	366659	0	0
T2	78706	7222	0	0
T3	998057	141829	0	0
T4	762515	192175	0	0
T7	104756	25673	0	0
T8	68769	2067	0	0
T55	71016	9261	0	0
T56	25733	11173	0	0
T57	39869	6285	0	0
T58	46766	29905	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T203,T204,T209
1	1	Covered	T1,T4,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	664374816	5690	0	0
DisabledNoTrigBkwd_A	664374816	163882	0	0
DisabledNoTrigFwd_A	664374816	377474720	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	5690	0	0
T9	446214	0	0	0
T70	411671	0	0	0
T113	72308	0	0	0
T203	3451	1083	0	0
T204	4018	1108	0	0
T209	0	159	0	0
T210	0	754	0	0
T211	0	207	0	0
T213	0	701	0	0
T214	0	614	0	0
T218	0	799	0	0
T219	0	265	0	0
T220	104426	0	0	0
T221	340749	0	0	0
T222	10254	0	0	0
T223	46032	0	0	0
T224	2381	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	163882	0	0
T4	762515	479	0	0
T5	0	766	0	0
T6	106971	0	0	0
T7	104756	23	0	0
T8	68769	32	0	0
T15	255453	64	0	0
T21	0	106	0	0
T37	452073	317	0	0
T42	0	1429	0	0
T55	71016	0	0	0
T56	25733	48	0	0
T57	39869	0	0	0
T58	46766	35	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	377474720	0	0
T1	401426	400112	0	0
T2	78706	78617	0	0
T3	998057	859186	0	0
T4	762515	332230	0	0
T7	104756	21821	0	0
T8	68769	13976	0	0
T55	71016	3919	0	0
T56	25733	2047	0	0
T57	39869	39785	0	0
T58	46766	2017	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T205,T215
1	1	Covered	T1,T4,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	664374816	4168	0	0
DisabledNoTrigBkwd_A	664374816	178820	0	0
DisabledNoTrigFwd_A	664374816	399875362	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	4168	0	0
T53	441620	0	0	0
T64	874478	0	0	0
T90	20962	0	0	0
T201	3856	837	0	0
T205	0	1506	0	0
T215	0	1468	0	0
T217	0	357	0	0
T233	17179	0	0	0
T234	109266	0	0	0
T235	15080	0	0	0
T236	144299	0	0	0
T237	442581	0	0	0
T238	421397	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	178820	0	0
T1	401426	435	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	224	0	0
T5	0	899	0	0
T6	0	1052	0	0
T7	104756	15	0	0
T8	68769	0	0	0
T13	0	4	0	0
T15	0	22	0	0
T21	0	50	0	0
T42	0	2	0	0
T55	71016	0	0	0
T56	25733	81	0	0
T57	39869	0	0	0
T58	46766	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	399875362	0	0
T1	401426	660330	0	0
T2	78706	78617	0	0
T3	998057	933359	0	0
T4	762515	426214	0	0
T7	104756	38353	0	0
T8	68769	68675	0	0
T55	71016	59819	0	0
T56	25733	2018	0	0
T57	39869	18087	0	0
T58	46766	46685	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T202,T206
1	1	Covered	T1,T4,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	664374816	5712	0	0
DisabledNoTrigBkwd_A	664374816	191328	0	0
DisabledNoTrigFwd_A	664374816	362453238	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	5712	0	0
T22	329528	0	0	0
T27	503180	0	0	0
T40	20050	0	0	0
T48	494611	0	0	0
T87	459350	0	0	0
T200	5238	1584	0	0
T202	0	747	0	0
T206	0	1309	0	0
T208	0	673	0	0
T212	0	980	0	0
T216	0	419	0	0
T239	13800	0	0	0
T240	199756	0	0	0
T241	11442	0	0	0
T242	421937	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	191328	0	0
T1	401426	546	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	704	0	0
T5	0	5084	0	0
T6	0	1204	0	0
T7	104756	14	0	0
T8	68769	0	0	0
T15	0	80	0	0
T37	0	2	0	0
T42	0	5	0	0
T55	71016	0	0	0
T56	25733	14	0	0
T57	39869	0	0	0
T58	46766	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	362453238	0	0
T1	401426	365419	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	525519	0	0
T7	104756	74534	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	6070	0	0
T57	39869	39785	0	0
T58	46766	34639	0	0