Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.25			74.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[1].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[2].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[3].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[0].u_accu.u_prim_count	81.08			81.08
tb.dut.gen_classes[1].u_accu.u_prim_count	81.08			81.08
tb.dut.gen_classes[3].u_accu.u_prim_count	86.49			86.49
tb.dut.u_ping_timer.u_prim_count_esc_cnt	88.89			88.89
tb.dut.gen_classes[2].u_accu.u_prim_count	89.19			89.19
tb.dut.u_ping_timer.u_prim_count_cnt	98.08			98.08

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.94	96.04	80.00		92.86	88.46	82.35	gen_classes[0].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	96.04	77.78		92.86	88.46	82.35	gen_classes[1].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	96.04	77.78		92.86	88.46	82.35	gen_classes[2].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	96.04	77.78		92.86	88.46	82.35	gen_classes[3].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.08			81.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.08			81.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[0].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.08			81.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.08			81.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[1].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49			86.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49			86.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[3].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89			88.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.02	91.94	89.19		83.33	90.62	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.19			89.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.19			89.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[2].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08			98.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08			98.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.02	91.94	89.19		83.33	90.62	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=5,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
88.89	88.89

tb.dut.u_ping_timer.u_prim_count_esc_cnt

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	18	16	88.89
Total Bits 0->1	9	8	88.89
Total Bits 1->0	9	8	88.89

Ports	7	6	85.71
Port Bits	18	16	88.89
Port Bits 0->1	9	8	88.89
Port Bits 1->0	9	8	88.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=10,NumCnt=2 + Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
98.08	98.08

tb.dut.u_ping_timer.u_prim_count_cnt

SCORE	TOGGLE
81.08	81.08

tb.dut.gen_classes[0].u_accu.u_prim_count

SCORE	TOGGLE
81.08	81.08

tb.dut.gen_classes[1].u_accu.u_prim_count

SCORE	TOGGLE
89.19	89.19

tb.dut.gen_classes[2].u_accu.u_prim_count

SCORE	TOGGLE
86.49	86.49

tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	9	8	88.89
Total Bits	108	106	98.15
Total Bits 0->1	54	53	98.15
Total Bits 1->0	54	53	98.15

Ports	9	8	88.89
Port Bits	108	106	98.15
Port Bits 0->1	54	53	98.15
Port Bits 1->0	54	53	98.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
set_cnt_i[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=7,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[0].u_esc_timer.u_prim_count

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[1].u_esc_timer.u_prim_count

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[2].u_esc_timer.u_prim_count

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
set_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
set_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
set_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	60	81.08
Total Bits 0->1	37	30	81.08
Total Bits 1->0	37	30	81.08

Ports	7	4	57.14
Port Bits	74	60	81.08
Port Bits 0->1	37	30	81.08
Port Bits 1->0	37	30	81.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[15:13]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:13]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	60	81.08
Total Bits 0->1	37	30	81.08
Total Bits 1->0	37	30	81.08

Ports	7	4	57.14
Port Bits	74	60	81.08
Port Bits 0->1	37	30	81.08
Port Bits 1->0	37	30	81.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_o[15:13]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_after_commit_o[15:13]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	64	86.49
Total Bits 0->1	37	32	86.49
Total Bits 1->0	37	32	86.49

Ports	7	4	57.14
Port Bits	74	64	86.49
Port Bits 0->1	37	32	86.49
Port Bits 1->0	37	32	86.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[13:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[13:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	18	16	88.89
Total Bits 0->1	9	8	88.89
Total Bits 1->0	9	8	88.89

Ports	7	6	85.71
Port Bits	18	16	88.89
Port Bits 0->1	9	8	88.89
Port Bits 1->0	9	8	88.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	66	89.19
Total Bits 0->1	37	34	91.89
Total Bits 1->0	37	32	86.49

Ports	7	4	57.14
Port Bits	74	66	89.19
Port Bits 0->1	37	34	91.89
Port Bits 1->0	37	32	86.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[13:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_o[14]	No	No		Yes	T9	OUTPUT
cnt_o[15]	No	No		No		OUTPUT
cnt_after_commit_o[13:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_after_commit_o[14]	No	No		Yes	T9	OUTPUT
cnt_after_commit_o[15]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_cnt

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	104	102	98.08
Total Bits 0->1	52	51	98.08
Total Bits 1->0	52	51	98.08

Ports	7	6	85.71
Port Bits	104	102	98.08
Port Bits 0->1	52	51	98.08
Port Bits 1->0	52	51	98.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	INPUT
set_cnt_i[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
err_o	No	No		No		OUTPUT