Module Definition
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Module : alert_handler_ping_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.35 91.94 89.19 50.00 90.62 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_ping_timer 91.02 91.94 89.19 83.33 90.62 100.00



Module Instance : tb.dut.u_ping_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.02 91.94 89.19 83.33 90.62 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.46 94.12 87.18 98.97 83.33 91.18 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.06 100.00 96.31 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_buf_spurious_alert_ping 100.00 100.00
u_prim_buf_spurious_esc_ping 100.00 100.00
u_prim_count_cnt 98.08 98.08
u_prim_count_esc_cnt 88.89 88.89
u_prim_double_lfsr 87.50 100.00 50.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : alert_handler_ping_timer
Line No.TotalCoveredPercent
TOTAL625791.94
CONT_ASSIGN7811100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
ALWAYS8533100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN13411100.00
ALWAYS14144100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
ALWAYS331373286.49
ALWAYS42633100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1
81 1 1
82 1 1
85 1 1
86 1 1
88 1 1
99 1 1
134 1 1
141 1 1
142 1 1
144 1 1
145 1 1
MISSING_ELSE
152 1 1
156 1 1
196 1 1
233 1 1
234 1 1
264 1 1
265 1 1
268 1 1
278 1 1
279 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
338 1 1
339 1 1
341 1 1
346 1 1
347 1 1
348 1 1
MISSING_ELSE
353 1 1
354 1 1
355 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
MISSING_ELSE
375 1 1
376 1 1
377 1 1
MISSING_ELSE
384 1 1
385 1 1
386 1 1
387 1 1
388 1 1
389 1 1
390 1 1
MISSING_ELSE
MISSING_ELSE
399 0 1
400 0 1
412 1 1
413 0 1
414 0 1
415 0 1
MISSING_ELSE
426 3 3


Cond Coverage for Module : alert_handler_ping_timer
TotalCoveredPercent
Conditions373389.19
Logical373389.19
Non-Logical00
Event00

 LINE       78
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       78
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       82
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       99
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       117
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T6
10CoveredT1,T2,T3

 LINE       134
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION ((esc_cnt >= 2'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ---------------------1---------------------    -----2----
-1--2-StatusTests
01CoveredT3,T4,T6
10CoveredT3,T4,T6
11CoveredT3,T4,T6

 LINE       233
 EXPRESSION (cnt == '0)
            -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       234
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T6
10CoveredT3,T4,T6

 LINE       268
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       365
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----
-1--2--3-StatusTests
000CoveredT3,T4,T6
001CoveredT6,T37,T42
010CoveredT4,T6,T37
100CoveredT3,T37,T51

 LINE       385
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT3,T4,T6
10CoveredT3,T35,T36

 LINE       412
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

FSM Coverage for Module : alert_handler_ping_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 6 5 83.33 (Not included in score)
Transitions 10 5 50.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AlertPingSt 354 Covered T3,T4,T6
AlertWaitSt 347 Covered T3,T4,T6
EscPingSt 376 Covered T3,T4,T6
EscWaitSt 366 Covered T3,T4,T6
FsmErrorSt 413 Not Covered
InitSt 345 Covered T1,T2,T3


transitionsLine No.CoveredTests
AlertPingSt->EscWaitSt 366 Covered T3,T4,T6
AlertPingSt->FsmErrorSt 413 Not Covered
AlertWaitSt->AlertPingSt 354 Covered T3,T4,T6
AlertWaitSt->FsmErrorSt 413 Not Covered
EscPingSt->AlertWaitSt 386 Covered T3,T4,T6
EscPingSt->FsmErrorSt 413 Not Covered
EscWaitSt->EscPingSt 376 Covered T3,T4,T6
EscWaitSt->FsmErrorSt 413 Not Covered
InitSt->AlertWaitSt 347 Covered T3,T4,T6
InitSt->FsmErrorSt 413 Not Covered



Branch Coverage for Module : alert_handler_ping_timer
Line No.TotalCoveredPercent
Branches 32 29 90.62
TERNARY 78 3 3 100.00
TERNARY 99 2 2 100.00
TERNARY 134 2 2 100.00
TERNARY 268 2 2 100.00
IF 85 2 2 100.00
IF 141 3 3 100.00
CASE 341 14 12 85.71
IF 412 2 1 50.00
IF 426 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 ((reseed_timer_q > '0)) ? -2-: 78 (reseed_en) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 99 (reseed_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 134 ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 268 (wait_cnt_set) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 85 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (cnt_set)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 341 case (state_q) -2-: 346 if (en_i) -3-: 353 if (timer_expired) -4-: 365 if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld))) -5-: 368 if (timer_expired) -6-: 375 if (timer_expired) -7-: 385 if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o)))) -8-: 389 if (timer_expired)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
InitSt 1 - - - - - - Covered T3,T4,T6
InitSt 0 - - - - - - Covered T1,T2,T3
AlertWaitSt - 1 - - - - - Covered T3,T4,T6
AlertWaitSt - 0 - - - - - Covered T3,T4,T6
AlertPingSt - - 1 1 - - - Covered T3,T37,T51
AlertPingSt - - 1 0 - - - Covered T4,T6,T37
AlertPingSt - - 0 - - - - Covered T3,T4,T6
EscWaitSt - - - - 1 - - Covered T3,T4,T6
EscWaitSt - - - - 0 - - Covered T3,T4,T6
EscPingSt - - - - - 1 1 Covered T3,T35,T36
EscPingSt - - - - - 1 0 Covered T3,T4,T6
EscPingSt - - - - - 0 - Covered T3,T4,T6
FsmErrorSt - - - - - - - Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 412 if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : alert_handler_ping_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertPingOH_A 664374816 195657 0 0
EscPingOH_A 664374816 124518 0 0
MaxIdDw_A 618 618 0 0
PingOH0_A 664374816 664308212 0 0
WaitCycMaskIsRightAlignedMask_A 664374816 664308212 0 0
WaitCycMaskMin_A 664374816 664308212 0 0
u_state_regs_A 664374816 664308212 0 0


AlertPingOH_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 195657 0 0
T3 998057 4940 0 0
T4 762515 27 0 0
T6 106971 54 0 0
T7 104756 0 0 0
T8 68769 0 0 0
T11 0 337 0 0
T12 0 26 0 0
T15 255453 0 0 0
T37 0 235 0 0
T38 0 214 0 0
T42 0 129 0 0
T46 0 9 0 0
T51 0 797 0 0
T55 71016 0 0 0
T56 25733 0 0 0
T57 39869 0 0 0
T58 46766 0 0 0

EscPingOH_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 124518 0 0
T3 998057 2895 0 0
T4 762515 20 0 0
T6 106971 75 0 0
T7 104756 0 0 0
T8 68769 0 0 0
T11 0 290 0 0
T12 0 100 0 0
T15 255453 0 0 0
T37 0 360 0 0
T38 0 145 0 0
T42 0 205 0 0
T46 0 70 0 0
T51 0 280 0 0
T55 71016 0 0 0
T56 25733 0 0 0
T57 39869 0 0 0
T58 46766 0 0 0

MaxIdDw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 618 618 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0
T58 1 1 0 0

PingOH0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

WaitCycMaskIsRightAlignedMask_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

WaitCycMaskMin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

Line Coverage for Instance : tb.dut.u_ping_timer
Line No.TotalCoveredPercent
TOTAL625791.94
CONT_ASSIGN7811100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
ALWAYS8533100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN13411100.00
ALWAYS14144100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN23311100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
ALWAYS331373286.49
ALWAYS42633100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1
81 1 1
82 1 1
85 1 1
86 1 1
88 1 1
99 1 1
134 1 1
141 1 1
142 1 1
144 1 1
145 1 1
MISSING_ELSE
152 1 1
156 1 1
196 1 1
233 1 1
234 1 1
264 1 1
265 1 1
268 1 1
278 1 1
279 1 1
331 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
338 1 1
339 1 1
341 1 1
346 1 1
347 1 1
348 1 1
MISSING_ELSE
353 1 1
354 1 1
355 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
369 1 1
MISSING_ELSE
MISSING_ELSE
375 1 1
376 1 1
377 1 1
MISSING_ELSE
384 1 1
385 1 1
386 1 1
387 1 1
388 1 1
389 1 1
390 1 1
MISSING_ELSE
MISSING_ELSE
399 0 1
400 0 1
412 1 1
413 0 1
414 0 1
415 0 1
MISSING_ELSE
426 3 3


Cond Coverage for Instance : tb.dut.u_ping_timer
TotalCoveredPercent
Conditions373389.19
Logical373389.19
Non-Logical00
Event00

 LINE       78
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       78
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       81
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       82
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       99
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       117
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T6
10CoveredT1,T2,T3

 LINE       134
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION ((esc_cnt >= 2'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ---------------------1---------------------    -----2----
-1--2-StatusTests
01CoveredT3,T4,T6
10CoveredT3,T4,T6
11CoveredT3,T4,T6

 LINE       233
 EXPRESSION (cnt == '0)
            -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       234
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T6
10CoveredT3,T4,T6

 LINE       268
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T6

 LINE       365
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----
-1--2--3-StatusTests
000CoveredT3,T4,T6
001CoveredT6,T37,T42
010CoveredT4,T6,T37
100CoveredT3,T37,T51

 LINE       385
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------
-1--2-StatusTests
00CoveredT3,T4,T6
01CoveredT3,T4,T6
10CoveredT3,T35,T36

 LINE       412
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100Not Covered

FSM Coverage for Instance : tb.dut.u_ping_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 6 5 83.33 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AlertPingSt 354 Covered T3,T4,T6
AlertWaitSt 347 Covered T3,T4,T6
EscPingSt 376 Covered T3,T4,T6
EscWaitSt 366 Covered T3,T4,T6
FsmErrorSt 413 Not Covered
InitSt 345 Covered T1,T2,T3


transitionsLine No.CoveredTestsExclude Annotation
AlertPingSt->EscWaitSt 366 Covered T3,T4,T6
AlertPingSt->FsmErrorSt 413 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
AlertWaitSt->AlertPingSt 354 Covered T3,T4,T6
AlertWaitSt->FsmErrorSt 413 Not Covered
EscPingSt->AlertWaitSt 386 Covered T3,T4,T6
EscPingSt->FsmErrorSt 413 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
EscWaitSt->EscPingSt 376 Covered T3,T4,T6
EscWaitSt->FsmErrorSt 413 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
InitSt->AlertWaitSt 347 Covered T3,T4,T6
InitSt->FsmErrorSt 413 Excluded [LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.



Branch Coverage for Instance : tb.dut.u_ping_timer
Line No.TotalCoveredPercent
Branches 32 29 90.62
TERNARY 78 3 3 100.00
TERNARY 99 2 2 100.00
TERNARY 134 2 2 100.00
TERNARY 268 2 2 100.00
IF 85 2 2 100.00
IF 141 3 3 100.00
CASE 341 14 12 85.71
IF 412 2 1 50.00
IF 426 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 ((reseed_timer_q > '0)) ? -2-: 78 (reseed_en) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 99 (reseed_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 134 ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 268 (wait_cnt_set) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 85 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 141 if ((!rst_ni)) -2-: 144 if (cnt_set)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 341 case (state_q) -2-: 346 if (en_i) -3-: 353 if (timer_expired) -4-: 365 if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld))) -5-: 368 if (timer_expired) -6-: 375 if (timer_expired) -7-: 385 if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o)))) -8-: 389 if (timer_expired)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
InitSt 1 - - - - - - Covered T3,T4,T6
InitSt 0 - - - - - - Covered T1,T2,T3
AlertWaitSt - 1 - - - - - Covered T3,T4,T6
AlertWaitSt - 0 - - - - - Covered T3,T4,T6
AlertPingSt - - 1 1 - - - Covered T3,T37,T51
AlertPingSt - - 1 0 - - - Covered T4,T6,T37
AlertPingSt - - 0 - - - - Covered T3,T4,T6
EscWaitSt - - - - 1 - - Covered T3,T4,T6
EscWaitSt - - - - 0 - - Covered T3,T4,T6
EscPingSt - - - - - 1 1 Covered T3,T35,T36
EscPingSt - - - - - 1 0 Covered T3,T4,T6
EscPingSt - - - - - 0 - Covered T3,T4,T6
FsmErrorSt - - - - - - - Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 412 if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_ping_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertPingOH_A 664374816 195657 0 0
EscPingOH_A 664374816 124518 0 0
MaxIdDw_A 618 618 0 0
PingOH0_A 664374816 664308212 0 0
WaitCycMaskIsRightAlignedMask_A 664374816 664308212 0 0
WaitCycMaskMin_A 664374816 664308212 0 0
u_state_regs_A 664374816 664308212 0 0


AlertPingOH_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 195657 0 0
T3 998057 4940 0 0
T4 762515 27 0 0
T6 106971 54 0 0
T7 104756 0 0 0
T8 68769 0 0 0
T11 0 337 0 0
T12 0 26 0 0
T15 255453 0 0 0
T37 0 235 0 0
T38 0 214 0 0
T42 0 129 0 0
T46 0 9 0 0
T51 0 797 0 0
T55 71016 0 0 0
T56 25733 0 0 0
T57 39869 0 0 0
T58 46766 0 0 0

EscPingOH_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 124518 0 0
T3 998057 2895 0 0
T4 762515 20 0 0
T6 106971 75 0 0
T7 104756 0 0 0
T8 68769 0 0 0
T11 0 290 0 0
T12 0 100 0 0
T15 255453 0 0 0
T37 0 360 0 0
T38 0 145 0 0
T42 0 205 0 0
T46 0 70 0 0
T51 0 280 0 0
T55 71016 0 0 0
T56 25733 0 0 0
T57 39869 0 0 0
T58 46766 0 0 0

MaxIdDw_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 618 618 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T55 1 1 0 0
T56 1 1 0 0
T57 1 1 0 0
T58 1 1 0 0

PingOH0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

WaitCycMaskIsRightAlignedMask_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

WaitCycMaskMin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 664374816 664308212 0 0
T1 401426 401416 0 0
T2 78706 78617 0 0
T3 998057 997974 0 0
T4 762515 762501 0 0
T7 104756 104669 0 0
T8 68769 68675 0 0
T55 71016 70924 0 0
T56 25733 25681 0 0
T57 39869 39785 0 0
T58 46766 46685 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%