Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.69	96.04	76.60		65.00	88.46	82.35

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[2].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[3].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[0].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.06	100.00		96.31			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T59
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T4,T7
1	1	1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T4,T5,T11
1	0	Covered	T2,T4,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T4,T5,T11

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	20	13	65.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T42,T14,T49
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T6,T60
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T60,T11,T49
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T49,T61,T62
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T4,T7
TimeoutSt->Phase0St	172	Covered	T2,T4,T6

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T42,T49
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T60,T63
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T60,T11,T49
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T61,T62
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	0	0	0
CheckAccumTrig0_A	2147483647	2195	0	0
CheckAccumTrig1_A	2147483647	121	0	0
CheckClr_A	2147483647	977	0	0
CheckEn_A	2147483647	1148352556	0	0
CheckPhase0_A	2147483647	2488	0	0
CheckPhase1_A	2147483647	2451	0	0
CheckPhase2_A	2147483647	2413	0	0
CheckPhase3_A	2147483647	2378	0	0
CheckTimeout0_A	2147483647	2643	0	0
CheckTimeoutSt1_A	2147483647	317923	0	0
CheckTimeoutSt2_A	2147483647	2297	0	0
CheckTimeoutStTrig_A	2147483647	219	0	0
ErrorStAllEscAsserted_A	2147483647	0	0	0
ErrorStIsTerminal_A	2147483647	0	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2195	0	0
T1	1204278	8	0	0
T2	236118	1	0	0
T3	2994171	2	0	0
T4	3050060	18	0	0
T5	0	4	0	0
T6	106971	7	0	0
T7	419024	7	0	0
T8	275076	2	0	0
T13	0	2	0	0
T15	255453	3	0	0
T21	0	2	0	0
T37	452073	3	0	0
T42	0	4	0	0
T55	284064	1	0	0
T56	102932	4	0	0
T57	159476	1	0	0
T58	187064	6	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121	0	0
T2	78706	1	0	0
T3	998057	0	0	0
T4	1525030	1	0	0
T6	106971	1	0	0
T7	209512	0	0	0
T8	137538	0	0	0
T11	397374	1	0	0
T12	136065	0	0	0
T14	107513	0	0	0
T15	510906	0	0	0
T23	0	1	0	0
T27	0	1	0	0
T28	0	6	0	0
T35	862624	0	0	0
T38	223477	0	0	0
T41	0	1	0	0
T51	376542	0	0	0
T53	0	1	0	0
T55	142032	0	0	0
T56	51466	0	0	0
T57	79738	0	0	0
T58	93532	0	0	0
T60	33044	2	0	0
T61	0	1	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	29120	0	0	0
T74	23512	0	0	0
T75	135631	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	977	0	0
T1	401426	0	0	0
T2	157412	1	0	0
T3	1996114	1	0	0
T4	2287545	2	0	0
T5	816579	1	0	0
T6	213942	2	0	0
T7	314268	1	0	0
T8	206307	0	0	0
T10	64346	0	0	0
T11	0	2	0	0
T13	4910	2	0	0
T14	0	1	0	0
T15	510906	0	0	0
T21	462612	0	0	0
T27	0	2	0	0
T37	904146	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	277839	2	0	0
T49	0	3	0	0
T55	213048	0	0	0
T56	77199	0	0	0
T57	119607	0	0	0
T58	140298	3	0	0
T60	0	9	0	0
T74	0	1	0	0
T75	0	8	0	0
T76	0	1	0	0
T77	0	4	0	0
T78	0	1	0	0
T79	33825	0	0	0
T80	31869	0	0	0
T81	11197	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1148352556	0	0
T1	1605704	1790036	0	0
T2	314824	240454	0	0
T3	3992228	2932345	0	0
T4	3050060	1251037	0	0
T7	419024	118330	0	0
T8	275076	144844	0	0
T55	284064	143921	0	0
T56	102932	10810	0	0
T57	159476	103940	0	0
T58	187064	57020	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2488	0	0
T1	1204278	7	0	0
T2	236118	2	0	0
T3	2994171	2	0	0
T4	3050060	23	0	0
T5	0	4	0	0
T6	106971	8	0	0
T7	419024	7	0	0
T8	275076	2	0	0
T13	0	2	0	0
T15	255453	3	0	0
T21	0	2	0	0
T37	452073	3	0	0
T42	0	4	0	0
T55	284064	1	0	0
T56	102932	4	0	0
T57	159476	1	0	0
T58	187064	6	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2451	0	0
T1	1204278	7	0	0
T2	236118	2	0	0
T3	2994171	2	0	0
T4	3050060	22	0	0
T5	0	4	0	0
T6	106971	7	0	0
T7	419024	7	0	0
T8	275076	2	0	0
T13	0	2	0	0
T15	255453	3	0	0
T21	0	2	0	0
T37	452073	3	0	0
T42	0	4	0	0
T55	284064	1	0	0
T56	102932	4	0	0
T57	159476	1	0	0
T58	187064	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2413	0	0
T1	1204278	7	0	0
T2	236118	2	0	0
T3	2994171	2	0	0
T4	3050060	22	0	0
T5	0	4	0	0
T6	106971	6	0	0
T7	419024	7	0	0
T8	275076	2	0	0
T13	0	2	0	0
T15	255453	3	0	0
T21	0	2	0	0
T37	452073	3	0	0
T42	0	4	0	0
T55	284064	1	0	0
T56	102932	4	0	0
T57	159476	1	0	0
T58	187064	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2378	0	0
T1	1204278	7	0	0
T2	236118	2	0	0
T3	2994171	2	0	0
T4	3050060	22	0	0
T5	0	4	0	0
T6	106971	6	0	0
T7	419024	7	0	0
T8	275076	2	0	0
T13	0	2	0	0
T15	255453	3	0	0
T21	0	2	0	0
T37	452073	3	0	0
T42	0	4	0	0
T55	284064	1	0	0
T56	102932	4	0	0
T57	159476	1	0	0
T58	187064	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2643	0	0
T1	401426	1	0	0
T2	78706	1	0	0
T3	998057	0	0	0
T4	3050060	18	0	0
T5	0	61	0	0
T6	320913	4	0	0
T7	419024	2	0	0
T8	275076	0	0	0
T11	0	8	0	0
T13	0	1	0	0
T14	0	4	0	0
T15	766359	0	0	0
T37	1356219	0	0	0
T44	0	51	0	0
T49	0	1	0	0
T55	284064	0	0	0
T56	102932	0	0	0
T57	159476	0	0	0
T58	187064	0	0	0
T60	0	3	0	0
T73	0	8	0	0
T74	0	1	0	0
T76	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	3	0	0
T85	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	317923	0	0
T1	401426	178	0	0
T2	78706	1	0	0
T3	998057	0	0	0
T4	3050060	3856	0	0
T5	0	3678	0	0
T6	320913	324	0	0
T7	419024	178	0	0
T8	275076	0	0	0
T11	0	508	0	0
T13	0	64	0	0
T14	0	887	0	0
T15	766359	0	0	0
T37	1356219	0	0	0
T44	0	8729	0	0
T49	0	37	0	0
T55	284064	0	0	0
T56	102932	0	0	0
T57	159476	0	0	0
T58	187064	0	0	0
T60	0	51	0	0
T73	0	1542	0	0
T74	0	194	0	0
T76	0	141	0	0
T82	0	1039	0	0
T83	0	900	0	0
T84	0	821	0	0
T85	0	388	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2297	0	0
T1	401426	1	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	3050060	13	0	0
T5	0	60	0	0
T6	320913	3	0	0
T7	419024	2	0	0
T8	275076	0	0	0
T11	0	4	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	766359	0	0	0
T27	0	13	0	0
T37	1356219	0	0	0
T44	0	49	0	0
T49	0	1	0	0
T55	284064	0	0	0
T56	102932	0	0	0
T57	159476	0	0	0
T58	187064	0	0	0
T60	0	1	0	0
T73	0	8	0	0
T74	0	1	0	0
T76	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	5	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	219	0	0
T4	2287545	3	0	0
T5	0	1	0	0
T6	320913	0	0	0
T7	314268	0	0	0
T8	206307	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	766359	0	0	0
T27	0	5	0	0
T36	125677	0	0	0
T37	1356219	0	0	0
T44	620383	2	0	0
T45	0	1	0	0
T49	713807	0	0	0
T50	908087	0	0	0
T53	0	1	0	0
T55	213048	0	0	0
T56	77199	0	0	0
T57	119607	0	0	0
T58	140298	0	0	0
T63	0	6	0	0
T64	0	1	0	0
T77	0	1	0	0
T82	15690	1	0	0
T83	44803	0	0	0
T84	30616	0	0	0
T85	40977	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	6	0	0
T95	14337	0	0	0
T96	495760	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1605704	1605664	0	0
T2	314824	314468	0	0
T3	3992228	3991896	0	0
T4	3050060	3050004	0	0
T7	419024	418676	0	0
T8	275076	274700	0	0
T55	284064	283696	0	0
T56	102932	102724	0	0
T57	159476	159140	0	0
T58	187064	186740	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1605704	1605664	0	0
T2	314824	314468	0	0
T3	3992228	3991896	0	0
T4	3050060	3050004	0	0
T7	419024	418676	0	0
T8	275076	274700	0	0
T55	284064	283696	0	0
T56	102932	102724	0	0
T57	159476	159140	0	0
T58	187064	186740	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T7,T8
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T8

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T4,T15,T37
1	1	0	Covered	T1,T4,T7
1	1	1	Covered	T4,T7,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T5
0	1	Covered	T4,T11,T14
1	0	Covered	T60,T53,T66

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T7,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T60,T53,T66

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T5
1	0	Not Covered
1	1	Covered	T4,T11,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T8
1	Covered	T4,T56,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T8
1	Covered	T4,T14,T76

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T7,T56
1	Covered	T8,T58,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T56
1	Covered	T4,T7,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T8,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T8,T58

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T8,T58

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T7,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T7,T8
Phase1St	198	Covered	T4,T7,T8
Phase2St	215	Covered	T4,T7,T8
Phase3St	233	Covered	T4,T7,T8
TerminalSt	249	Covered	T4,T7,T8
TimeoutSt	159	Covered	T4,T7,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T4,T7,T8
IdleSt->TimeoutSt	159	Covered	T4,T7,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T14,T49,T16
Phase0St->Phase1St	198	Covered	T4,T7,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T60,T97,T98
Phase1St->Phase2St	215	Covered	T4,T7,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T60,T99,T100
Phase2St->Phase3St	233	Covered	T4,T7,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T101,T102,T25
Phase3St->TerminalSt	249	Covered	T4,T7,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T58,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T7,T5
TimeoutSt->Phase0St	172	Covered	T4,T60,T11

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T60,T11
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T49,T16,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T7,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T7,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T60,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T7,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T7,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T60,T99,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T7,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T101,T102,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T7,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T58,T60
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T7,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	664374816	0	0	0
CheckAccumTrig0_A	664374816	495	0	0
CheckAccumTrig1_A	664374816	29	0	0
CheckClr_A	664374816	233	0	0
CheckEn_A	664374816	313157507	0	0
CheckPhase0_A	664374816	561	0	0
CheckPhase1_A	664374816	556	0	0
CheckPhase2_A	664374816	551	0	0
CheckPhase3_A	664374816	542	0	0
CheckTimeout0_A	664374816	596	0	0
CheckTimeoutSt1_A	664374816	69582	0	0
CheckTimeoutSt2_A	664374816	520	0	0
CheckTimeoutStTrig_A	664374816	45	0	0
ErrorStAllEscAsserted_A	664374816	0	0	0
ErrorStIsTerminal_A	664374816	0	0	0
EscStateOut_A	664374816	664308212	0	0
u_state_regs_A	664374816	664308212	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	495	0	0
T4	762515	4	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	1	0	0
T15	255453	1	0	0
T21	0	1	0	0
T37	452073	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	29	0	0
T11	397374	0	0	0
T12	136065	0	0	0
T14	107513	0	0	0
T23	0	1	0	0
T28	0	1	0	0
T35	862624	0	0	0
T38	223477	0	0	0
T51	376542	0	0	0
T53	0	1	0	0
T60	33044	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	29120	0	0	0
T74	23512	0	0	0
T75	135631	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	233	0	0
T4	762515	1	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T15	255453	0	0	0
T27	0	2	0	0
T37	452073	0	0	0
T39	0	1	0	0
T49	0	2	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	1	0	0
T60	0	9	0	0
T75	0	5	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	313157507	0	0
T1	401426	400112	0	0
T2	78706	78616	0	0
T3	998057	859185	0	0
T4	762515	298427	0	0
T7	104756	15926	0	0
T8	68769	5429	0	0
T55	71016	3919	0	0
T56	25733	2047	0	0
T57	39869	39784	0	0
T58	46766	2017	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	561	0	0
T4	762515	5	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	1	0	0
T15	255453	1	0	0
T21	0	1	0	0
T37	452073	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	556	0	0
T4	762515	5	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	1	0	0
T15	255453	1	0	0
T21	0	1	0	0
T37	452073	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	551	0	0
T4	762515	5	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	1	0	0
T15	255453	1	0	0
T21	0	1	0	0
T37	452073	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	542	0	0
T4	762515	5	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	1	0	0
T15	255453	1	0	0
T21	0	1	0	0
T37	452073	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	596	0	0
T4	762515	3	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T11	0	1	0	0
T14	0	1	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	12	0	0
T49	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T60	0	2	0	0
T73	0	3	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	69582	0	0
T4	762515	621	0	0
T5	0	121	0	0
T6	106971	0	0	0
T7	104756	54	0	0
T8	68769	0	0	0
T11	0	19	0	0
T14	0	35	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	2038	0	0
T49	0	37	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T60	0	8	0	0
T73	0	580	0	0
T76	0	141	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	520	0	0
T4	762515	2	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T15	255453	0	0	0
T27	0	1	0	0
T37	452073	0	0	0
T44	0	11	0	0
T49	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	3	0	0
T76	0	1	0	0
T86	0	1	0	0
T87	0	10	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	45	0	0
T4	762515	1	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	1	0	0
T14	0	1	0	0
T15	255453	0	0	0
T27	0	2	0	0
T37	452073	0	0	0
T44	0	1	0	0
T53	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T63	0	1	0	0
T90	0	1	0	0
T93	0	1	0	0
T94	0	6	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T1,T15,T37
1	1	0	Covered	T1,T4,T7
1	1	1	Covered	T4,T7,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T6
0	1	Covered	T82,T44,T45
1	0	Covered	T4,T6,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T7,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T6
1	0	Not Covered
1	1	Covered	T82,T44,T45

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T4,T5,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T4,T11,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T4,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Covered	T1,T4,T7

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T56,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T7
Phase1St	198	Covered	T1,T4,T7
Phase2St	215	Covered	T1,T4,T7
Phase3St	233	Covered	T1,T4,T7
TerminalSt	249	Covered	T1,T4,T7
TimeoutSt	159	Covered	T4,T7,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T4,T7
IdleSt->TimeoutSt	159	Covered	T4,T7,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T16,T104,T105
Phase0St->Phase1St	198	Covered	T1,T4,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T6,T14
Phase1St->Phase2St	215	Covered	T1,T4,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T106,T107,T108
Phase2St->Phase3St	233	Covered	T1,T4,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T62,T100,T109
Phase3St->TerminalSt	249	Covered	T1,T4,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T7,T6
TimeoutSt->Phase0St	172	Covered	T4,T6,T82

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T82
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T105,T110,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T63,T9
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T106,T107,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T62,T100,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T42,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	664374816	0	0	0
CheckAccumTrig0_A	664374816	443	0	0
CheckAccumTrig1_A	664374816	19	0	0
CheckClr_A	664374816	189	0	0
CheckEn_A	664374816	328679862	0	0
CheckPhase0_A	664374816	522	0	0
CheckPhase1_A	664374816	510	0	0
CheckPhase2_A	664374816	501	0	0
CheckPhase3_A	664374816	497	0	0
CheckTimeout0_A	664374816	535	0	0
CheckTimeoutSt1_A	664374816	74069	0	0
CheckTimeoutSt2_A	664374816	450	0	0
CheckTimeoutStTrig_A	664374816	65	0	0
ErrorStAllEscAsserted_A	664374816	0	0	0
ErrorStIsTerminal_A	664374816	0	0	0
EscStateOut_A	664374816	664308212	0	0
u_state_regs_A	664374816	664308212	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	443	0	0
T1	401426	2	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	3	0	0
T5	0	1	0	0
T6	0	2	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T21	0	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	19	0	0
T4	762515	1	0	0
T6	106971	1	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T45	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T99	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	189	0	0
T5	816579	0	0	0
T6	106971	2	0	0
T10	64346	0	0	0
T13	4910	2	0	0
T21	462612	0	0	0
T37	452073	0	0	0
T38	0	1	0	0
T42	277839	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T75	0	3	0	0
T77	0	2	0	0
T79	33825	0	0	0
T80	31869	0	0	0
T81	11197	0	0	0
T85	0	1	0	0
T87	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	328679862	0	0
T1	401426	660328	0	0
T2	78706	78616	0	0
T3	998057	933358	0	0
T4	762515	339403	0	0
T7	104756	38353	0	0
T8	68769	68674	0	0
T55	71016	59818	0	0
T56	25733	2018	0	0
T57	39869	18087	0	0
T58	46766	46684	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	522	0	0
T1	401426	2	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	4	0	0
T5	0	1	0	0
T6	0	3	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T21	0	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	510	0	0
T1	401426	2	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	3	0	0
T5	0	1	0	0
T6	0	2	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T21	0	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	501	0	0
T1	401426	2	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	3	0	0
T5	0	1	0	0
T6	0	2	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T21	0	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	497	0	0
T1	401426	2	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	3	0	0
T5	0	1	0	0
T6	0	2	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T13	0	2	0	0
T15	0	1	0	0
T21	0	1	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	535	0	0
T4	762515	3	0	0
T5	0	1	0	0
T6	106971	3	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	17	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	1	0	0
T82	0	2	0	0
T84	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	74069	0	0
T4	762515	294	0	0
T5	0	69	0	0
T6	106971	206	0	0
T7	104756	124	0	0
T8	68769	0	0	0
T11	0	199	0	0
T14	0	108	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	2896	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	184	0	0
T82	0	1039	0	0
T84	0	542	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	450	0	0
T4	762515	2	0	0
T5	0	1	0	0
T6	106971	2	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	16	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	1	0	0
T82	0	1	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	65	0	0
T27	0	2	0	0
T36	125677	0	0	0
T44	620383	1	0	0
T45	0	1	0	0
T49	713807	0	0	0
T50	908087	0	0	0
T63	0	3	0	0
T77	0	1	0	0
T82	15690	1	0	0
T83	44803	0	0	0
T84	30616	0	0	0
T85	40977	0	0	0
T87	0	1	0	0
T89	0	1	0	0
T95	14337	0	0	0
T96	495760	0	0	0
T112	0	1	0	0
T116	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T7
1	0	1	Covered	T1,T4,T15
1	1	0	Covered	T1,T4,T7
1	1	1	Covered	T4,T5,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T13
0	1	Covered	T4,T27,T63
1	0	Covered	T11,T14,T66

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T11,T14,T66

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Not Covered
1	1	Covered	T4,T27,T63

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T4,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T4,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T7,T15,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T4,T6,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T56,T58

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T7
Phase1St	198	Covered	T1,T4,T7
Phase2St	215	Covered	T1,T4,T7
Phase3St	233	Covered	T1,T4,T7
TerminalSt	249	Covered	T1,T4,T7
TimeoutSt	159	Covered	T4,T5,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T4,T7
IdleSt->TimeoutSt	159	Covered	T4,T5,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T16,T110
Phase0St->Phase1St	198	Covered	T1,T4,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T112,T19,T102
Phase1St->Phase2St	215	Covered	T1,T4,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T49,T90
Phase2St->Phase3St	233	Covered	T1,T4,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T94,T117,T118
Phase3St->TerminalSt	249	Covered	T1,T4,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T13
TimeoutSt->Phase0St	172	Covered	T4,T11,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T11,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T110,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T112,T19,T102
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T49,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T94,T117,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	664374816	0	0	0
CheckAccumTrig0_A	664374816	487	0	0
CheckAccumTrig1_A	664374816	24	0	0
CheckClr_A	664374816	208	0	0
CheckEn_A	664374816	281792578	0	0
CheckPhase0_A	664374816	545	0	0
CheckPhase1_A	664374816	538	0	0
CheckPhase2_A	664374816	527	0	0
CheckPhase3_A	664374816	523	0	0
CheckTimeout0_A	664374816	911	0	0
CheckTimeoutSt1_A	664374816	93830	0	0
CheckTimeoutSt2_A	664374816	837	0	0
CheckTimeoutStTrig_A	664374816	48	0	0
ErrorStAllEscAsserted_A	664374816	0	0	0
ErrorStIsTerminal_A	664374816	0	0	0
EscStateOut_A	664374816	664308212	0	0
u_state_regs_A	664374816	664308212	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	487	0	0
T1	401426	5	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	4	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	104756	3	0	0
T8	68769	0	0	0
T15	0	1	0	0
T37	0	2	0	0
T42	0	2	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	24	0	0
T11	397374	1	0	0
T12	136065	0	0	0
T14	107513	0	0	0
T29	0	1	0	0
T35	862624	0	0	0
T44	620383	0	0	0
T51	376542	0	0	0
T66	0	1	0	0
T68	0	1	0	0
T75	135631	0	0	0
T76	15995	0	0	0
T82	15690	0	0	0
T83	44803	0	0	0
T108	0	2	0	0
T112	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	208	0	0
T1	401426	4	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	1	0	0
T6	0	4	0	0
T7	104756	2	0	0
T8	68769	0	0	0
T14	0	1	0	0
T27	0	3	0	0
T37	0	1	0	0
T42	0	1	0	0
T49	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T85	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	281792578	0	0
T1	401426	363669	0	0
T2	78706	78616	0	0
T3	998057	997973	0	0
T4	762515	444759	0	0
T7	104756	38378	0	0
T8	68769	68674	0	0
T55	71016	70923	0	0
T56	25733	6070	0	0
T57	39869	39784	0	0
T58	46766	2045	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	545	0	0
T1	401426	4	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	5	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	104756	3	0	0
T8	68769	0	0	0
T15	0	1	0	0
T37	0	2	0	0
T42	0	2	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	538	0	0
T1	401426	4	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	5	0	0
T5	0	2	0	0
T6	0	5	0	0
T7	104756	3	0	0
T8	68769	0	0	0
T15	0	1	0	0
T37	0	2	0	0
T42	0	2	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	527	0	0
T1	401426	4	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	5	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	104756	3	0	0
T8	68769	0	0	0
T15	0	1	0	0
T37	0	2	0	0
T42	0	2	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	523	0	0
T1	401426	4	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	5	0	0
T5	0	2	0	0
T6	0	4	0	0
T7	104756	3	0	0
T8	68769	0	0	0
T15	0	1	0	0
T37	0	2	0	0
T42	0	2	0	0
T55	71016	0	0	0
T56	25733	1	0	0
T57	39869	0	0	0
T58	46766	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	911	0	0
T4	762515	6	0	0
T5	0	27	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	3	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	15	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	93830	0	0
T4	762515	1862	0	0
T5	0	1741	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	158	0	0
T13	0	64	0	0
T14	0	744	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	2611	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	144	0	0
T83	0	900	0	0
T84	0	279	0	0
T85	0	388	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	837	0	0
T4	762515	5	0	0
T5	0	27	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	255453	0	0	0
T37	452073	0	0	0
T44	0	15	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T73	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	48	0	0
T4	762515	1	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T15	255453	0	0	0
T27	0	1	0	0
T37	452073	0	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T63	0	2	0	0
T64	0	1	0	0
T70	0	1	0	0
T88	0	2	0	0
T93	0	1	0	0
T101	0	1	0	0
T112	0	2	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T59
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T4,T7
1	1	1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T4,T5,T11
1	0	Covered	T2,T11,T27

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T27

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T4,T5,T11

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T7
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T55,T79

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T4,T55

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T42,T63,T64
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T124,T99,T71
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T11,T49,T63
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T49,T61,T99
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T3
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T6
TimeoutSt->Phase0St	172	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T42,T63,T64
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T124,T99,T125
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T11,T49,T63
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T61,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	664374816	0	0	0
CheckAccumTrig0_A	664374816	770	0	0
CheckAccumTrig1_A	664374816	49	0	0
CheckClr_A	664374816	347	0	0
CheckEn_A	664374816	224722609	0	0
CheckPhase0_A	664374816	860	0	0
CheckPhase1_A	664374816	847	0	0
CheckPhase2_A	664374816	834	0	0
CheckPhase3_A	664374816	816	0	0
CheckTimeout0_A	664374816	601	0	0
CheckTimeoutSt1_A	664374816	80442	0	0
CheckTimeoutSt2_A	664374816	490	0	0
CheckTimeoutStTrig_A	664374816	61	0	0
ErrorStAllEscAsserted_A	664374816	0	0	0
ErrorStIsTerminal_A	664374816	0	0	0
EscStateOut_A	664374816	664308212	0	0
u_state_regs_A	664374816	664308212	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	770	0	0
T1	401426	1	0	0
T2	78706	1	0	0
T3	998057	2	0	0
T4	762515	7	0	0
T7	104756	2	0	0
T8	68769	1	0	0
T55	71016	1	0	0
T56	25733	1	0	0
T57	39869	1	0	0
T58	46766	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	49	0	0
T2	78706	1	0	0
T3	998057	0	0	0
T4	762515	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	1	0	0
T15	255453	0	0	0
T27	0	1	0	0
T28	0	5	0	0
T41	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T61	0	1	0	0
T63	0	4	0	0
T64	0	1	0	0
T65	0	2	0	0
T69	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	347	0	0
T2	78706	1	0	0
T3	998057	1	0	0
T4	762515	1	0	0
T5	0	1	0	0
T7	104756	1	0	0
T8	68769	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	255453	0	0	0
T42	0	1	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	2	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	224722609	0	0
T1	401426	365927	0	0
T2	78706	4606	0	0
T3	998057	141829	0	0
T4	762515	168448	0	0
T7	104756	25673	0	0
T8	68769	2067	0	0
T55	71016	9261	0	0
T56	25733	675	0	0
T57	39869	6285	0	0
T58	46766	6274	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	860	0	0
T1	401426	1	0	0
T2	78706	2	0	0
T3	998057	2	0	0
T4	762515	9	0	0
T7	104756	2	0	0
T8	68769	1	0	0
T55	71016	1	0	0
T56	25733	1	0	0
T57	39869	1	0	0
T58	46766	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	847	0	0
T1	401426	1	0	0
T2	78706	2	0	0
T3	998057	2	0	0
T4	762515	9	0	0
T7	104756	2	0	0
T8	68769	1	0	0
T55	71016	1	0	0
T56	25733	1	0	0
T57	39869	1	0	0
T58	46766	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	834	0	0
T1	401426	1	0	0
T2	78706	2	0	0
T3	998057	2	0	0
T4	762515	9	0	0
T7	104756	2	0	0
T8	68769	1	0	0
T55	71016	1	0	0
T56	25733	1	0	0
T57	39869	1	0	0
T58	46766	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	816	0	0
T1	401426	1	0	0
T2	78706	2	0	0
T3	998057	2	0	0
T4	762515	9	0	0
T7	104756	2	0	0
T8	68769	1	0	0
T55	71016	1	0	0
T56	25733	1	0	0
T57	39869	1	0	0
T58	46766	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	601	0	0
T1	401426	1	0	0
T2	78706	1	0	0
T3	998057	0	0	0
T4	762515	6	0	0
T5	0	32	0	0
T6	0	1	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	2	0	0
T44	0	7	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T60	0	1	0	0
T73	0	3	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	80442	0	0
T1	401426	178	0	0
T2	78706	1	0	0
T3	998057	0	0	0
T4	762515	1079	0	0
T5	0	1747	0	0
T6	0	118	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	132	0	0
T44	0	1184	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T60	0	43	0	0
T73	0	634	0	0
T74	0	194	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	490	0	0
T1	401426	1	0	0
T2	78706	0	0	0
T3	998057	0	0	0
T4	762515	4	0	0
T5	0	31	0	0
T6	0	1	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T27	0	12	0	0
T44	0	7	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T60	0	1	0	0
T73	0	3	0	0
T74	0	1	0	0
T84	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	61	0	0
T4	762515	2	0	0
T5	0	1	0	0
T6	106971	0	0	0
T7	104756	0	0	0
T8	68769	0	0	0
T11	0	1	0	0
T15	255453	0	0	0
T27	0	1	0	0
T37	452073	0	0	0
T55	71016	0	0	0
T56	25733	0	0	0
T57	39869	0	0	0
T58	46766	0	0	0
T63	0	2	0	0
T64	0	1	0	0
T85	0	1	0	0
T88	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	664374816	664308212	0	0
T1	401426	401416	0	0
T2	78706	78617	0	0
T3	998057	997974	0	0
T4	762515	762501	0	0
T7	104756	104669	0	0
T8	68769	68675	0	0
T55	71016	70924	0	0
T56	25733	25681	0	0
T57	39869	39785	0	0
T58	46766	46685	0	0