Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63778654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30908882

1

T1

1033

T2

823

T3

1296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14174896	1			T1	411		T2	408		T3	1510
values[0x0]	39303342	1			T1	1495		T2	1090		T3	1063
values[0x1]	41209298	1			T1	1489		T2	1064		T3	1029

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	54526307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40161229

1

T1

1303

T2

1040

T3

1631

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	305432	1			T1	12		T2	8		T3	34
valid_sources[0x01]	315746	1			T1	7		T2	10		T3	17
valid_sources[0x02]	316407	1			T1	9		T2	13		T3	47
valid_sources[0x03]	319890	1			T1	13		T2	11		T3	16
valid_sources[0x04]	317063	1			T1	16		T2	20		T7	1825
valid_sources[0x05]	316560	1			T1	12		T2	8		T3	5
valid_sources[0x06]	325607	1			T1	16		T2	23		T3	2
valid_sources[0x07]	849136	1			T1	11		T2	12		T3	10
valid_sources[0x08]	309078	1			T1	13		T2	8		T3	19
valid_sources[0x09]	321544	1			T1	15		T2	13		T3	3
valid_sources[0x0a]	308942	1			T1	15		T2	10		T3	1
valid_sources[0x0b]	315162	1			T1	10		T2	12		T3	1
valid_sources[0x0c]	315094	1			T1	13		T2	11		T7	1814
valid_sources[0x0d]	316732	1			T1	14		T2	3		T3	27
valid_sources[0x0e]	314505	1			T1	15		T2	8		T3	1
valid_sources[0x0f]	318883	1			T1	11		T2	11		T3	6
valid_sources[0x10]	308375	1			T1	11		T2	12		T3	23
valid_sources[0x11]	315549	1			T1	19		T2	14		T3	11
valid_sources[0x12]	319221	1			T1	15		T2	2		T3	24
valid_sources[0x13]	317206	1			T1	23		T2	8		T3	25
valid_sources[0x14]	314011	1			T1	11		T2	7		T3	3
valid_sources[0x15]	569135	1			T1	5		T2	17		T3	10
valid_sources[0x16]	310554	1			T1	14		T2	8		T7	1787
valid_sources[0x17]	353716	1			T1	13		T2	25		T3	17
valid_sources[0x18]	311659	1			T1	9		T2	14		T7	1521
valid_sources[0x19]	316963	1			T1	10		T2	5		T7	1951
valid_sources[0x1a]	316291	1			T1	10		T2	14		T3	23
valid_sources[0x1b]	608768	1			T1	18		T2	21		T3	23
valid_sources[0x1c]	319873	1			T1	17		T2	5		T3	30
valid_sources[0x1d]	315267	1			T1	11		T2	6		T7	1766
valid_sources[0x1e]	307738	1			T1	16		T2	2		T7	1984
valid_sources[0x1f]	324760	1			T1	14		T2	1		T3	22
valid_sources[0x20]	328300	1			T1	23		T2	2		T3	2
valid_sources[0x21]	315983	1			T1	10		T2	23		T3	7
valid_sources[0x22]	310823	1			T1	16		T2	4		T3	28
valid_sources[0x23]	316340	1			T1	22		T2	19		T3	39
valid_sources[0x24]	311571	1			T1	20		T2	8		T3	15
valid_sources[0x25]	728678	1			T1	6		T2	4		T7	1510
valid_sources[0x26]	315248	1			T1	14		T2	16		T3	47
valid_sources[0x27]	313556	1			T1	6		T2	11		T3	17
valid_sources[0x28]	593848	1			T1	11		T2	26		T3	17
valid_sources[0x29]	301911	1			T1	12		T2	16		T3	9
valid_sources[0x2a]	313763	1			T1	12		T2	10		T3	3
valid_sources[0x2b]	314964	1			T1	15		T2	8		T3	55
valid_sources[0x2c]	312795	1			T1	10		T2	17		T3	33
valid_sources[0x2d]	904433	1			T1	17		T2	3		T3	8
valid_sources[0x2e]	316166	1			T1	13		T2	2		T3	23
valid_sources[0x2f]	313893	1			T1	23		T2	11		T3	12
valid_sources[0x30]	713392	1			T1	15		T2	3		T3	6
valid_sources[0x31]	320707	1			T1	14		T2	14		T7	1786
valid_sources[0x32]	319150	1			T1	16		T2	11		T3	10
valid_sources[0x33]	680831	1			T1	12		T2	4		T3	4
valid_sources[0x34]	306033	1			T1	18		T2	3		T3	28
valid_sources[0x35]	304735	1			T1	14		T2	8		T7	1838
valid_sources[0x36]	317763	1			T1	15		T2	11		T3	3
valid_sources[0x37]	318296	1			T1	13		T2	7		T3	11
valid_sources[0x38]	319534	1			T1	15		T2	6		T7	1851
valid_sources[0x39]	314462	1			T1	14		T2	5		T3	25
valid_sources[0x3a]	317948	1			T1	12		T2	14		T3	5
valid_sources[0x3b]	309471	1			T1	14		T2	19		T3	23
valid_sources[0x3c]	314390	1			T1	8		T2	16		T3	2
valid_sources[0x3d]	313163	1			T1	5		T2	22		T3	20
valid_sources[0x3e]	327000	1			T1	21		T2	7		T3	1
valid_sources[0x3f]	315391	1			T1	14		T2	11		T7	1750
valid_sources[0x40]	310110	1			T1	13		T2	9		T3	10
valid_sources[0x41]	314781	1			T1	12		T2	2		T3	13
valid_sources[0x42]	320034	1			T1	18		T2	1		T3	22
valid_sources[0x43]	308068	1			T1	20		T2	3		T3	5
valid_sources[0x44]	320802	1			T1	11		T2	11		T3	20
valid_sources[0x45]	312937	1			T1	12		T2	10		T3	10
valid_sources[0x46]	317916	1			T1	10		T2	4		T3	10
valid_sources[0x47]	639895	1			T1	11		T2	4		T3	17
valid_sources[0x48]	317837	1			T1	15		T2	12		T3	24
valid_sources[0x49]	314008	1			T1	15		T2	9		T3	29
valid_sources[0x4a]	311557	1			T1	16		T2	6		T3	9
valid_sources[0x4b]	308028	1			T1	7		T2	14		T3	8
valid_sources[0x4c]	349707	1			T1	17		T2	10		T3	8
valid_sources[0x4d]	308105	1			T1	11		T2	11		T3	49
valid_sources[0x4e]	327239	1			T1	7		T2	8		T3	21
valid_sources[0x4f]	582482	1			T1	14		T2	10		T3	26
valid_sources[0x50]	787422	1			T1	10		T2	8		T7	1782
valid_sources[0x51]	322593	1			T1	13		T3	12		T7	1801
valid_sources[0x52]	312543	1			T1	8		T2	10		T3	5
valid_sources[0x53]	314465	1			T1	15		T2	4		T3	42
valid_sources[0x54]	316781	1			T1	10		T2	12		T3	3
valid_sources[0x55]	328346	1			T1	15		T2	11		T3	33
valid_sources[0x56]	314223	1			T1	11		T2	16		T3	26
valid_sources[0x57]	1003744	1			T1	10		T2	12		T7	1657
valid_sources[0x58]	322007	1			T1	11		T2	20		T3	6
valid_sources[0x59]	317431	1			T1	11		T2	15		T3	18
valid_sources[0x5a]	313971	1			T1	20		T2	8		T3	20
valid_sources[0x5b]	320289	1			T1	18		T2	3		T3	42
valid_sources[0x5c]	318414	1			T1	13		T2	7		T7	1774
valid_sources[0x5d]	333784	1			T1	17		T2	4		T7	1649
valid_sources[0x5e]	313716	1			T1	8		T2	21		T3	16
valid_sources[0x5f]	310676	1			T1	4		T2	16		T7	1586
valid_sources[0x60]	312445	1			T1	16		T2	14		T3	1
valid_sources[0x61]	308457	1			T1	18		T2	9		T3	13
valid_sources[0x62]	320228	1			T1	15		T2	2		T3	18
valid_sources[0x63]	318824	1			T1	12		T2	9		T7	1860
valid_sources[0x64]	310560	1			T1	13		T2	3		T3	2
valid_sources[0x65]	315653	1			T1	15		T2	13		T3	22
valid_sources[0x66]	364316	1			T1	12		T2	20		T3	31
valid_sources[0x67]	318594	1			T1	12		T2	5		T3	18
valid_sources[0x68]	312835	1			T1	13		T2	2		T7	1589
valid_sources[0x69]	314105	1			T1	16		T2	11		T7	1829
valid_sources[0x6a]	323430	1			T1	14		T2	15		T3	17
valid_sources[0x6b]	306555	1			T1	14		T2	9		T3	7
valid_sources[0x6c]	315611	1			T1	11		T2	7		T3	49
valid_sources[0x6d]	305883	1			T1	21		T2	31		T3	12
valid_sources[0x6e]	324341	1			T1	18		T2	3		T3	52
valid_sources[0x6f]	316672	1			T1	13		T2	2		T3	2
valid_sources[0x70]	318134	1			T1	19		T2	6		T7	1615
valid_sources[0x71]	328730	1			T1	8		T2	18		T3	66
valid_sources[0x72]	312938	1			T1	11		T2	7		T7	1545
valid_sources[0x73]	322874	1			T1	30		T2	15		T7	1963
valid_sources[0x74]	308566	1			T1	17		T2	8		T3	2
valid_sources[0x75]	338942	1			T1	12		T2	14		T3	4
valid_sources[0x76]	316569	1			T1	13		T2	1		T3	4
valid_sources[0x77]	313479	1			T1	16		T2	10		T3	33
valid_sources[0x78]	327074	1			T1	16		T2	2		T3	11
valid_sources[0x79]	304051	1			T1	7		T2	3		T3	4
valid_sources[0x7a]	311790	1			T1	13		T2	9		T3	60
valid_sources[0x7b]	321259	1			T1	6		T2	6		T3	9
valid_sources[0x7c]	309256	1			T1	15		T3	6		T7	1648
valid_sources[0x7d]	316687	1			T1	17		T2	5		T3	4
valid_sources[0x7e]	307218	1			T1	7		T2	6		T3	16
valid_sources[0x7f]	318508	1			T1	6		T2	5		T3	13
valid_sources[0x80]	310634	1			T1	9		T2	19		T3	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7073471

1

T1

229

T2

201

T3

713

values[0x0]

all_enables

biggest_size

15051689

1

T1

514

T2

398

T3

388

values[0x1]

all_enables

biggest_size

8783722

1

T1

290

T2

224

T3

195