Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T233,T234,T235
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15028	0	0
DisabledNoTrigBkwd_A	2147483647	819636	0	0
DisabledNoTrigFwd_A	2147483647	1597803492	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15028	0	0
T18	167925	0	0	0
T23	10745	0	0	0
T24	198957	0	0	0
T31	77837	0	0	0
T35	215308	0	0	0
T103	62516	0	0	0
T104	93990	0	0	0
T105	36281	0	0	0
T112	51951	0	0	0
T113	250175	0	0	0
T114	21831	0	0	0
T119	122658	0	0	0
T233	0	532	0	0
T234	1153	389	0	0
T235	4450	963	0	0
T236	2806	530	0	0
T237	0	531	0	0
T238	0	962	0	0
T239	0	740	0	0
T240	0	1069	0	0
T241	0	1357	0	0
T242	0	888	0	0
T243	0	531	0	0
T244	0	655	0	0
T245	0	383	0	0
T246	0	481	0	0
T247	0	374	0	0
T248	0	1414	0	0
T249	0	986	0	0
T250	0	756	0	0
T251	0	490	0	0
T252	0	997	0	0
T253	276961	0	0	0
T254	459287	0	0	0
T255	76405	0	0	0
T256	108652	0	0	0
T257	769636	0	0	0
T258	12746	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	819636	0	0
T1	353769	0	0	0
T2	96860	17	0	0
T3	58248	5	0	0
T4	0	870	0	0
T5	0	53	0	0
T7	2055964	4828	0	0
T8	1888108	825	0	0
T9	313476	25	0	0
T10	1664128	1712	0	0
T11	0	9	0	0
T15	238808	7	0	0
T16	174936	0	0	0
T19	435072	2	0	0
T20	0	1	0	0
T21	0	26	0	0
T25	0	38	0	0
T26	0	4	0	0
T33	0	8345	0	0
T49	2817966	240	0	0
T56	0	2	0	0
T63	0	1201	0	0
T67	0	1	0	0
T71	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1597803492	0	0
T1	1415076	362921	0	0
T2	96860	38017	0	0
T3	58248	44077	0	0
T7	2055964	547664	0	0
T8	1888108	519452	0	0
T9	313476	231913	0	0
T10	1664128	842112	0	0
T15	238808	180910	0	0
T16	174936	98628	0	0
T19	435072	322327	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T8
1	1	Covered	T2,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T234,T238,T239
1	1	Covered	T2,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709906063	5599	0	0
DisabledNoTrigBkwd_A	709906063	219338	0	0
DisabledNoTrigFwd_A	709906063	361578291	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	5599	0	0
T18	167925	0	0	0
T23	10745	0	0	0
T24	198957	0	0	0
T35	215308	0	0	0
T103	62516	0	0	0
T112	51951	0	0	0
T113	250175	0	0	0
T114	21831	0	0	0
T234	1153	389	0	0
T238	0	962	0	0
T239	0	740	0	0
T241	0	1357	0	0
T243	0	531	0	0
T245	0	383	0	0
T246	0	481	0	0
T250	0	756	0	0
T253	276961	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	219338	0	0
T2	24215	5	0	0
T3	14562	5	0	0
T7	513991	3065	0	0
T8	472027	825	0	0
T9	78369	0	0	0
T10	416032	6	0	0
T15	59702	7	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	0	1	0	0
T33	0	6228	0	0
T49	939322	240	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	361578291	0	0
T1	353769	353702	0	0
T2	24215	12547	0	0
T3	14562	601	0	0
T7	513991	3128	0	0
T8	472027	32620	0	0
T9	78369	78305	0	0
T10	416032	414754	0	0
T15	59702	6797	0	0
T16	43734	12861	0	0
T19	108768	3073	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T2,T7,T16
1	1	Covered	T2,T7,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T235
1	1	Covered	T2,T7,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709906063	963	0	0
DisabledNoTrigBkwd_A	709906063	190994	0	0
DisabledNoTrigFwd_A	709906063	406373530	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	963	0	0
T31	77837	0	0	0
T104	93990	0	0	0
T105	36281	0	0	0
T119	122658	0	0	0
T235	4450	963	0	0
T254	459287	0	0	0
T255	76405	0	0	0
T256	108652	0	0	0
T257	769636	0	0	0
T258	12746	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	190994	0	0
T2	24215	2	0	0
T3	14562	0	0	0
T4	0	831	0	0
T5	0	27	0	0
T7	513991	1763	0	0
T8	472027	0	0	0
T9	78369	25	0	0
T10	416032	0	0	0
T11	0	2	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	26	0	0
T25	0	2	0	0
T33	0	2117	0	0
T49	939322	0	0	0
T67	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	406373530	0	0
T1	353769	3053	0	0
T2	24215	9687	0	0
T3	14562	14492	0	0
T7	513991	27353	0	0
T8	472027	7630	0	0
T9	78369	2986	0	0
T10	416032	415437	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T7,T8,T16
1	1	Covered	T1,T2,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T236,T248,T252
1	1	Covered	T1,T2,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709906063	2941	0	0
DisabledNoTrigBkwd_A	709906063	181566	0	0
DisabledNoTrigFwd_A	709906063	452061029	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	2941	0	0
T12	478557	0	0	0
T32	334642	0	0	0
T84	62236	0	0	0
T85	349434	0	0	0
T236	2806	530	0	0
T248	0	1414	0	0
T252	0	997	0	0
T259	17163	0	0	0
T260	342972	0	0	0
T261	185325	0	0	0
T262	411712	0	0	0
T263	198166	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	181566	0	0
T2	24215	10	0	0
T3	14562	0	0	0
T4	0	39	0	0
T5	0	26	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	1706	0	0
T11	0	7	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T25	0	36	0	0
T26	0	4	0	0
T49	939322	0	0	0
T56	0	2	0	0
T63	0	1201	0	0
T71	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	452061029	0	0
T1	353769	3076	0	0
T2	24215	2093	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	471534	0	0
T9	78369	78305	0	0
T10	416032	3018	0	0
T15	59702	54867	0	0
T16	43734	40117	0	0
T19	108768	101910	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T233,T237,T240
1	1	Covered	T1,T2,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	709906063	5525	0	0
DisabledNoTrigBkwd_A	709906063	227738	0	0
DisabledNoTrigFwd_A	709906063	377790642	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	5525	0	0
T18	167925	0	0	0
T23	10745	0	0	0
T24	198957	0	0	0
T35	215308	0	0	0
T103	62516	0	0	0
T112	51951	0	0	0
T113	250175	0	0	0
T233	1953	532	0	0
T234	1153	0	0	0
T237	0	531	0	0
T240	0	1069	0	0
T242	0	888	0	0
T244	0	655	0	0
T247	0	374	0	0
T249	0	986	0	0
T251	0	490	0	0
T253	276961	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	227738	0	0
T1	353769	1	0	0
T2	24215	2	0	0
T3	14562	0	0	0
T7	513991	3220	0	0
T8	472027	411	0	0
T9	78369	2	0	0
T10	416032	2589	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T20	0	3	0	0
T25	0	16	0	0
T33	0	28	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	377790642	0	0
T1	353769	3090	0	0
T2	24215	13690	0	0
T3	14562	14492	0	0
T7	513991	3199	0	0
T8	472027	7668	0	0
T9	78369	72317	0	0
T10	416032	8903	0	0
T15	59702	59623	0	0
T16	43734	2011	0	0
T19	108768	108672	0	0