Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T10 Yes T7,T8,T10 INPUT
ping_ok_o Yes Yes T7,T8,T10 Yes T7,T8,T10 OUTPUT
integ_fail_o Yes Yes T33,T11,T25 Yes T33,T11,T25 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T7,T33,T64 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T33,T64 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T10 Yes T7,T8,T10 INPUT
ping_ok_o Yes Yes T7,T8,T10 Yes T7,T8,T10 OUTPUT
integ_fail_o Yes Yes T40,T99,T72 Yes T40,T99,T72 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T7,T6,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T6,T60 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T33,T54 Yes T10,T33,T54 INPUT
ping_ok_o Yes Yes T10,T33,T67 Yes T10,T33,T67 OUTPUT
integ_fail_o Yes Yes T33,T11,T25 Yes T33,T11,T25 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T33,T54 Yes T33,T40,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T33,T40,T6 Yes T10,T33,T54 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T49,T40,T61 Yes T49,T40,T61 INPUT
ping_ok_o Yes Yes T49,T40,T61 Yes T49,T40,T61 OUTPUT
integ_fail_o Yes Yes T33,T4,T22 Yes T33,T4,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T40,T61,T6 Yes T40,T6,T62 OUTPUT
alert_rx_o.ping_p Yes Yes T40,T6,T62 Yes T40,T61,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T40,T63 Yes T21,T40,T63 INPUT
ping_ok_o Yes Yes T21,T40,T63 Yes T21,T40,T63 OUTPUT
integ_fail_o Yes Yes T25,T4,T40 Yes T25,T4,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T40,T63 Yes T6,T30,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T30,T60 Yes T21,T40,T63 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T64,T26 Yes T8,T64,T26 INPUT
ping_ok_o Yes Yes T8,T64,T26 Yes T8,T64,T26 OUTPUT
integ_fail_o Yes Yes T33,T25,T72 Yes T33,T25,T72 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T64,T26,T40 Yes T64,T26,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T64,T26,T6 Yes T64,T26,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T21,T54 Yes T10,T21,T54 INPUT
ping_ok_o Yes Yes T10,T21,T40 Yes T10,T21,T40 OUTPUT
integ_fail_o Yes Yes T11,T40,T22 Yes T11,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T21,T54 Yes T21,T56,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T56,T6 Yes T10,T21,T54 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T49,T33 Yes T10,T49,T33 INPUT
ping_ok_o Yes Yes T10,T49,T33 Yes T10,T49,T33 OUTPUT
integ_fail_o Yes Yes T33,T11,T4 Yes T33,T11,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T33,T21 Yes T10,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T6,T65 Yes T10,T33,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T33 Yes T7,T10,T33 INPUT
ping_ok_o Yes Yes T7,T10,T33 Yes T7,T10,T33 OUTPUT
integ_fail_o Yes Yes T33,T4,T22 Yes T33,T4,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T10,T64,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T64,T6 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T33 Yes T7,T10,T33 INPUT
ping_ok_o Yes Yes T7,T10,T33 Yes T7,T10,T33 OUTPUT
integ_fail_o Yes Yes T33,T4,T27 Yes T33,T4,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T10,T6,T62 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T6,T62 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T64,T26 Yes T21,T64,T26 INPUT
ping_ok_o Yes Yes T21,T64,T26 Yes T21,T64,T26 OUTPUT
integ_fail_o Yes Yes T11,T4,T22 Yes T11,T4,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T64,T26 Yes T64,T63,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T64,T63,T6 Yes T21,T64,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T10,T64 Yes T8,T10,T64 INPUT
ping_ok_o Yes Yes T10,T64,T40 Yes T10,T64,T40 OUTPUT
integ_fail_o Yes Yes T20,T33,T40 Yes T20,T33,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T10,T64 Yes T40,T6,T66 OUTPUT
alert_rx_o.ping_p Yes Yes T40,T6,T66 Yes T8,T10,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T21,T64 Yes T10,T21,T64 INPUT
ping_ok_o Yes Yes T10,T21,T64 Yes T10,T21,T64 OUTPUT
integ_fail_o Yes Yes T33,T25,T4 Yes T33,T25,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T21,T64 Yes T21,T6,T62 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T6,T62 Yes T10,T21,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T33 Yes T7,T8,T33 INPUT
ping_ok_o Yes Yes T7,T8,T33 Yes T7,T8,T33 OUTPUT
integ_fail_o Yes Yes T4,T40,T22 Yes T4,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T21 Yes T7,T55,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T55,T6 Yes T7,T33,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T10 Yes T7,T8,T10 INPUT
ping_ok_o Yes Yes T7,T8,T10 Yes T7,T8,T10 OUTPUT
integ_fail_o Yes Yes T33,T4,T22 Yes T33,T4,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T21 Yes T21,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T6,T65 Yes T7,T10,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T33,T54,T67 Yes T33,T54,T67 INPUT
ping_ok_o Yes Yes T33,T67,T40 Yes T33,T67,T40 OUTPUT
integ_fail_o Yes Yes T33,T56,T17 Yes T33,T56,T17 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T33,T54,T67 Yes T6,T65,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T65,T60 Yes T33,T54,T67 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
ping_ok_o Yes Yes T7,T8,T10 Yes T7,T8,T10 OUTPUT
integ_fail_o Yes Yes T4,T40,T27 Yes T4,T40,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T7,T10 Yes T6,T62,T18 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T62,T18 Yes T1,T7,T10 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T49 Yes T7,T10,T49 INPUT
ping_ok_o Yes Yes T7,T10,T49 Yes T7,T10,T49 OUTPUT
integ_fail_o Yes Yes T4,T40,T72 Yes T4,T40,T72 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T6,T66,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T66,T65 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T10 Yes T7,T8,T10 INPUT
ping_ok_o Yes Yes T7,T8,T10 Yes T7,T8,T10 OUTPUT
integ_fail_o Yes Yes T40,T17,T24 Yes T40,T17,T24 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T7,T10,T40 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T10,T40 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T40,T6,T65 Yes T40,T6,T65 INPUT
ping_ok_o Yes Yes T40,T6,T65 Yes T40,T6,T65 OUTPUT
integ_fail_o Yes Yes T20,T25,T4 Yes T20,T25,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T40,T6,T65 Yes T6,T65,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T65,T60 Yes T40,T6,T65 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T64,T26 Yes T7,T64,T26 INPUT
ping_ok_o Yes Yes T7,T64,T26 Yes T7,T64,T26 OUTPUT
integ_fail_o Yes Yes T33,T4,T40 Yes T33,T4,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T64,T26 Yes T7,T26,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T26,T68 Yes T7,T64,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T49 Yes T7,T8,T49 INPUT
ping_ok_o Yes Yes T7,T8,T49 Yes T7,T8,T49 OUTPUT
integ_fail_o Yes Yes T11,T25,T40 Yes T11,T25,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T55 Yes T33,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T33,T6,T65 Yes T7,T33,T55 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T40,T6 Yes T8,T40,T6 INPUT
ping_ok_o Yes Yes T8,T40,T6 Yes T8,T40,T6 OUTPUT
integ_fail_o Yes Yes T20,T25,T4 Yes T20,T25,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T40,T6,T69 Yes T40,T6,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T40,T6,T69 Yes T40,T6,T69 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T33 Yes T7,T10,T33 INPUT
ping_ok_o Yes Yes T7,T10,T33 Yes T7,T10,T33 OUTPUT
integ_fail_o Yes Yes T20,T33,T4 Yes T20,T33,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T33,T21,T22 OUTPUT
alert_rx_o.ping_p Yes Yes T33,T21,T22 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T64,T26 Yes T10,T64,T26 INPUT
ping_ok_o Yes Yes T10,T64,T26 Yes T10,T64,T26 OUTPUT
integ_fail_o Yes Yes T20,T27,T65 Yes T20,T27,T65 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T64,T26 Yes T6,T65,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T65,T60 Yes T10,T64,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T10,T67 Yes T8,T10,T67 INPUT
ping_ok_o Yes Yes T10,T67,T40 Yes T10,T67,T40 OUTPUT
integ_fail_o Yes Yes T20,T4,T27 Yes T20,T4,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T10,T67 Yes T8,T67,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T67,T6 Yes T8,T10,T67 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T67,T40 Yes T7,T67,T40 INPUT
ping_ok_o Yes Yes T7,T67,T40 Yes T7,T67,T40 OUTPUT
integ_fail_o Yes Yes T20,T33,T22 Yes T20,T33,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T67,T40 Yes T6,T65,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T65,T60 Yes T7,T67,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T1,T7,T21 Yes T1,T7,T21 INPUT
ping_ok_o Yes Yes T7,T21,T64 Yes T7,T21,T64 OUTPUT
integ_fail_o Yes Yes T33,T25,T22 Yes T33,T25,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T7,T21 Yes T7,T21,T64 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T21,T64 Yes T1,T7,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T33 Yes T7,T8,T33 INPUT
ping_ok_o Yes Yes T7,T8,T33 Yes T7,T8,T33 OUTPUT
integ_fail_o Yes Yes T20,T33,T40 Yes T20,T33,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T67 Yes T67,T6,T70 OUTPUT
alert_rx_o.ping_p Yes Yes T67,T6,T70 Yes T7,T33,T67 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T64,T26,T40 Yes T64,T26,T40 INPUT
ping_ok_o Yes Yes T64,T26,T40 Yes T64,T26,T40 OUTPUT
integ_fail_o Yes Yes T33,T25,T4 Yes T33,T25,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T64,T26,T40 Yes T40,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T40,T6,T65 Yes T64,T26,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T33,T26 Yes T7,T33,T26 INPUT
ping_ok_o Yes Yes T7,T33,T26 Yes T7,T33,T26 OUTPUT
integ_fail_o Yes Yes T20,T33,T4 Yes T20,T33,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T26 Yes T6,T30,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T30,T60 Yes T7,T33,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T33,T64 Yes T10,T33,T64 INPUT
ping_ok_o Yes Yes T10,T33,T64 Yes T10,T33,T64 OUTPUT
integ_fail_o Yes Yes T40,T56,T27 Yes T40,T56,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T33,T64 Yes T10,T64,T71 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T64,T71 Yes T10,T33,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T21,T40 Yes T7,T21,T40 INPUT
ping_ok_o Yes Yes T7,T21,T40 Yes T7,T21,T40 OUTPUT
integ_fail_o Yes Yes T33,T40,T22 Yes T33,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T21,T40 Yes T7,T6,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T6,T69 Yes T7,T21,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T10,T40 Yes T8,T10,T40 INPUT
ping_ok_o Yes Yes T8,T10,T40 Yes T8,T10,T40 OUTPUT
integ_fail_o Yes Yes T4,T56,T72 Yes T4,T56,T72 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T40,T6 Yes T6,T72,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T72,T65 Yes T10,T40,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T49 Yes T7,T8,T49 INPUT
ping_ok_o Yes Yes T7,T8,T49 Yes T7,T8,T49 OUTPUT
integ_fail_o Yes Yes T25,T22,T56 Yes T25,T22,T56 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T21,T64 Yes T21,T64,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T64,T26 Yes T7,T21,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T33 Yes T7,T8,T33 INPUT
ping_ok_o Yes Yes T7,T8,T33 Yes T7,T8,T33 OUTPUT
integ_fail_o Yes Yes T20,T4,T40 Yes T20,T4,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T6 Yes T6,T65,T73 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T65,T73 Yes T7,T33,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T49,T21 Yes T8,T49,T21 INPUT
ping_ok_o Yes Yes T8,T49,T21 Yes T8,T49,T21 OUTPUT
integ_fail_o Yes Yes T11,T40,T22 Yes T11,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T26,T22 Yes T26,T6,T62 OUTPUT
alert_rx_o.ping_p Yes Yes T26,T6,T62 Yes T21,T26,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T33 Yes T7,T10,T33 INPUT
ping_ok_o Yes Yes T7,T10,T33 Yes T7,T10,T33 OUTPUT
integ_fail_o Yes Yes T4,T40,T27 Yes T4,T40,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T7,T10,T40 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T10,T40 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T33,T21 Yes T7,T33,T21 INPUT
ping_ok_o Yes Yes T7,T33,T21 Yes T7,T33,T21 OUTPUT
integ_fail_o Yes Yes T4,T22,T27 Yes T4,T22,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T21 Yes T7,T6,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T6,T60 Yes T7,T33,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T64,T63 Yes T21,T64,T63 INPUT
ping_ok_o Yes Yes T21,T64,T63 Yes T21,T64,T63 OUTPUT
integ_fail_o Yes Yes T33,T25,T4 Yes T33,T25,T4 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T64,T63 Yes T21,T64,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T64,T6 Yes T21,T64,T63 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T64,T26 Yes T21,T64,T26 INPUT
ping_ok_o Yes Yes T21,T64,T26 Yes T21,T64,T26 OUTPUT
integ_fail_o Yes Yes T33,T40,T22 Yes T33,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T64,T26 Yes T55,T6,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T55,T6,T60 Yes T21,T64,T26 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T1,T8,T10 Yes T1,T8,T10 INPUT
ping_ok_o Yes Yes T8,T10,T21 Yes T8,T10,T21 OUTPUT
integ_fail_o Yes Yes T11,T25,T22 Yes T11,T25,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T10,T21 Yes T10,T21,T22 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T21,T22 Yes T1,T10,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T40,T63 Yes T21,T40,T63 INPUT
ping_ok_o Yes Yes T21,T40,T63 Yes T21,T40,T63 OUTPUT
integ_fail_o Yes Yes T40,T22,T27 Yes T40,T22,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T40,T63 Yes T63,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T63,T6,T65 Yes T21,T40,T63 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T26,T40 Yes T8,T26,T40 INPUT
ping_ok_o Yes Yes T8,T26,T40 Yes T8,T26,T40 OUTPUT
integ_fail_o Yes Yes T25,T22,T27 Yes T25,T22,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T26,T40,T6 Yes T6,T74,T18 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T74,T18 Yes T26,T40,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T26,T40 Yes T10,T26,T40 INPUT
ping_ok_o Yes Yes T10,T26,T40 Yes T10,T26,T40 OUTPUT
integ_fail_o Yes Yes T33,T25,T40 Yes T33,T25,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T26,T40 Yes T26,T63,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T26,T63,T6 Yes T10,T26,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T4,T5,T6 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T22,T71 Yes T7,T22,T71 INPUT
ping_ok_o Yes Yes T7,T22,T68 Yes T7,T22,T68 OUTPUT
integ_fail_o Yes Yes T33,T25,T40 Yes T33,T25,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T22,T71 Yes T7,T6,T62 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T6,T62 Yes T7,T22,T71 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T64,T40 Yes T7,T64,T40 INPUT
ping_ok_o Yes Yes T7,T64,T40 Yes T7,T64,T40 OUTPUT
integ_fail_o Yes Yes T25,T4,T40 Yes T25,T4,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T64,T40 Yes T7,T64,T40 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T64,T40 Yes T7,T64,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T1,T8,T26 Yes T1,T8,T26 INPUT
ping_ok_o Yes Yes T8,T26,T40 Yes T8,T26,T40 OUTPUT
integ_fail_o Yes Yes T4,T40,T56 Yes T4,T40,T56 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T26,T40 Yes T40,T6,T69 OUTPUT
alert_rx_o.ping_p Yes Yes T40,T6,T69 Yes T1,T26,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T10 Yes T7,T8,T10 INPUT
ping_ok_o Yes Yes T7,T8,T10 Yes T7,T8,T10 OUTPUT
integ_fail_o Yes Yes T20,T40,T27 Yes T20,T40,T27 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T21 Yes T7,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T6,T65 Yes T7,T10,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T49,T33 Yes T7,T49,T33 INPUT
ping_ok_o Yes Yes T7,T49,T33 Yes T7,T49,T33 OUTPUT
integ_fail_o Yes Yes T33,T40,T22 Yes T33,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T40 Yes T7,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T6,T65 Yes T7,T33,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T33 Yes T7,T8,T33 INPUT
ping_ok_o Yes Yes T7,T8,T33 Yes T7,T8,T33 OUTPUT
integ_fail_o Yes Yes T33,T40,T22 Yes T33,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T4 Yes T4,T6,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T4,T6,T60 Yes T7,T33,T4 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T64,T40 Yes T8,T64,T40 INPUT
ping_ok_o Yes Yes T8,T64,T40 Yes T8,T64,T40 OUTPUT
integ_fail_o Yes Yes T25,T4,T22 Yes T25,T4,T22 OUTPUT
alert_o Yes Yes T3,T7,T15 Yes T3,T7,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T7,T15 Yes T3,T7,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T64,T40,T63 Yes T40,T63,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T40,T63,T6 Yes T64,T40,T63 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T7,T15 Yes T3,T7,T8 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T49,T33 Yes T7,T49,T33 INPUT
ping_ok_o Yes Yes T7,T49,T33 Yes T7,T49,T33 OUTPUT
integ_fail_o Yes Yes T40,T72,T30 Yes T40,T72,T30 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T21 Yes T26,T22,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T26,T22,T6 Yes T7,T33,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T10,T40 Yes T8,T10,T40 INPUT
ping_ok_o Yes Yes T8,T10,T40 Yes T8,T10,T40 OUTPUT
integ_fail_o Yes Yes T25,T40,T22 Yes T25,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T40,T22 Yes T10,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T6,T65 Yes T10,T40,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T1,T8,T49 Yes T1,T8,T49 INPUT
ping_ok_o Yes Yes T8,T49,T6 Yes T8,T49,T6 OUTPUT
integ_fail_o Yes Yes T4,T40,T56 Yes T4,T40,T56 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T6,T74 Yes T6,T75,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T75,T65 Yes T1,T6,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T64,T40,T61 Yes T64,T40,T61 INPUT
ping_ok_o Yes Yes T64,T40,T61 Yes T64,T40,T61 OUTPUT
integ_fail_o Yes Yes T33,T40,T22 Yes T33,T40,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T64,T40,T61 Yes T64,T61,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T64,T61,T6 Yes T64,T40,T61 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T21 Yes T7,T10,T21 INPUT
ping_ok_o Yes Yes T7,T10,T21 Yes T7,T10,T21 OUTPUT
integ_fail_o Yes Yes T40,T99,T17 Yes T40,T99,T17 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T21 Yes T21,T40,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T40,T6 Yes T7,T10,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T64,T6 Yes T21,T64,T6 INPUT
ping_ok_o Yes Yes T21,T64,T6 Yes T21,T64,T6 OUTPUT
integ_fail_o Yes Yes T11,T25,T40 Yes T11,T25,T40 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T64,T6 Yes T6,T65,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T65,T60 Yes T21,T64,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T40,T22,T6 Yes T40,T22,T6 INPUT
ping_ok_o Yes Yes T40,T22,T6 Yes T40,T22,T6 OUTPUT
integ_fail_o Yes Yes T33,T25,T56 Yes T33,T25,T56 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T40,T22,T6 Yes T6,T76,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T76,T60 Yes T40,T22,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T8,T21 Yes T7,T8,T21 INPUT
ping_ok_o Yes Yes T7,T8,T21 Yes T7,T8,T21 OUTPUT
integ_fail_o Yes Yes T20,T4,T22 Yes T20,T4,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T21,T40 Yes T21,T6,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T6,T60 Yes T7,T21,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T21,T26,T40 Yes T21,T26,T40 INPUT
ping_ok_o Yes Yes T21,T26,T40 Yes T21,T26,T40 OUTPUT
integ_fail_o Yes Yes T11,T27,T18 Yes T11,T27,T18 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T21,T26,T40 Yes T6,T30,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T30,T60 Yes T21,T26,T40 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T33,T21 Yes T7,T33,T21 INPUT
ping_ok_o Yes Yes T7,T33,T21 Yes T7,T33,T21 OUTPUT
integ_fail_o Yes Yes T33,T25,T22 Yes T33,T25,T22 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T33,T21 Yes T21,T64,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T21,T64,T6 Yes T7,T33,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T10,T33 Yes T7,T10,T33 INPUT
ping_ok_o Yes Yes T7,T10,T33 Yes T7,T10,T33 OUTPUT
integ_fail_o Yes Yes T25,T40,T56 Yes T25,T40,T56 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T10,T33 Yes T33,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T33,T6,T65 Yes T7,T10,T33 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T8,T10,T21 Yes T8,T10,T21 INPUT
ping_ok_o Yes Yes T8,T10,T21 Yes T8,T10,T21 OUTPUT
integ_fail_o Yes Yes T4,T56,T72 Yes T4,T56,T72 OUTPUT
alert_o Yes Yes T3,T7,T15 Yes T3,T7,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T3,T7,T15 Yes T3,T7,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T21,T64 Yes T10,T21,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T21,T26 Yes T10,T21,T64 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T3,T7,T15 Yes T3,T7,T8 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T7,T22,T6 Yes T7,T22,T6 INPUT
ping_ok_o Yes Yes T7,T22,T6 Yes T7,T22,T6 OUTPUT
integ_fail_o Yes Yes T33,T40,T99 Yes T33,T40,T99 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T22,T6 Yes T7,T22,T6 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T22,T6 Yes T7,T22,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T49,T4,T5 Yes T3,T7,T15 INPUT
ping_req_i Yes Yes T10,T40,T6 Yes T10,T40,T6 INPUT
ping_ok_o Yes Yes T10,T40,T6 Yes T10,T40,T6 OUTPUT
integ_fail_o Yes Yes T33,T4,T56 Yes T33,T4,T56 OUTPUT
alert_o Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T2,T3,T7 Yes T2,T3,T7 OUTPUT
alert_rx_o.ping_n Yes Yes T10,T40,T6 Yes T10,T6,T65 OUTPUT
alert_rx_o.ping_p Yes Yes T10,T6,T65 Yes T10,T40,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T2,T3,T7 Yes T2,T3,T7 INPUT

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