Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.69	96.04	76.60		65.00	88.46	82.35

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[2].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[1].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35
tb.dut.gen_classes[3].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.19	100.00		96.69			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T16
1	0	1	Covered	T1,T7,T8
1	1	0	Covered	T16,T20,T11
1	1	1	Covered	T2,T16,T29

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T16,T29
0	1	Covered	T29,T77,T65
1	0	Covered	T4,T27,T65

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T16,T29
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T27,T65

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T29
1	0	Covered	T78,T79,T80
1	1	Covered	T29,T77,T65

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T3,T9,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T2,T7,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T2,T19,T33

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T19,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T7,T8

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	20	13	65.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T7
Phase1St	198	Covered	T2,T3,T7
Phase2St	215	Covered	T2,T3,T7
Phase3St	233	Covered	T2,T3,T7
TerminalSt	249	Covered	T2,T3,T7
TimeoutSt	159	Covered	T2,T16,T29

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T2,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T16,T29
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T81,T62,T18
Phase0St->Phase1St	198	Covered	T2,T3,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T15,T22,T27
Phase1St->Phase2St	215	Covered	T2,T3,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T56,T62,T18
Phase2St->Phase3St	233	Covered	T2,T3,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T64,T82,T27
Phase3St->TerminalSt	249	Covered	T2,T3,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T15,T10
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T16,T25
TimeoutSt->Phase0St	172	Covered	T29,T4,T56

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T29
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T4,T56
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T29
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T62,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T22,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T56,T62,T18
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T64,T82,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T15,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	0	0	0
CheckAccumTrig0_A	2147483647	2445	0	0
CheckAccumTrig1_A	2147483647	115	0	0
CheckClr_A	2147483647	1232	0	0
CheckEn_A	2147483647	1282405054	0	0
CheckPhase0_A	2147483647	2796	0	0
CheckPhase1_A	2147483647	2739	0	0
CheckPhase2_A	2147483647	2671	0	0
CheckPhase3_A	2147483647	2621	0	0
CheckTimeout0_A	2147483647	4441	0	0
CheckTimeoutSt1_A	2147483647	549168	0	0
CheckTimeoutSt2_A	2147483647	4023	0	0
CheckTimeoutStTrig_A	2147483647	295	0	0
ErrorStAllEscAsserted_A	2147483647	0	0	0
ErrorStIsTerminal_A	2147483647	0	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2445	0	0
T1	353769	0	0	0
T2	96860	3	0	0
T3	58248	1	0	0
T4	0	4	0	0
T5	0	5	0	0
T7	2055964	2	0	0
T8	1888108	1	0	0
T9	313476	1	0	0
T10	1664128	4	0	0
T11	0	3	0	0
T15	238808	4	0	0
T16	174936	0	0	0
T19	435072	2	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T33	0	2	0	0
T49	2817966	1	0	0
T56	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115	0	0
T4	637356	2	0	0
T5	449114	0	0	0
T17	258714	0	0	0
T22	379242	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	726974	0	0	0
T27	742298	1	0	0
T30	0	1	0	0
T34	38700	0	0	0
T37	0	4	0	0
T40	715124	0	0	0
T52	0	2	0	0
T55	215984	0	0	0
T63	642322	0	0	0
T65	0	1	0	0
T66	354368	0	0	0
T67	202080	0	0	0
T71	1943616	0	0	0
T72	944744	0	0	0
T75	712642	0	0	0
T77	101286	0	0	0
T82	25134	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	3	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	4	0	0
T95	0	2	0	0
T96	67444	0	0	0
T97	69688	0	0	0
T98	33711	0	0	0
T99	57598	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1232	0	0
T1	353769	0	0	0
T2	48430	1	0	0
T3	29124	0	0	0
T4	0	4	0	0
T5	0	8	0	0
T7	1027982	0	0	0
T8	944054	0	0	0
T9	235107	0	0	0
T10	1664128	2	0	0
T11	21386	2	0	0
T15	179106	3	0	0
T16	131202	0	0	0
T19	435072	2	0	0
T20	20616	0	0	0
T21	1084644	2	0	0
T22	0	4	0	0
T25	18486	1	0	0
T26	0	1	0	0
T27	0	3	0	0
T29	21980	0	0	0
T33	343246	0	0	0
T49	2817966	0	0	0
T56	0	2	0	0
T64	445980	6	0	0
T71	0	1	0	0
T72	0	1	0	0
T74	0	3	0	0
T77	0	1	0	0
T81	0	2	0	0
T82	0	2	0	0
T99	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1282405054	0	0
T1	1415076	362920	0	0
T2	96860	20240	0	0
T3	58248	44074	0	0
T7	2055964	547664	0	0
T8	1888108	519452	0	0
T9	313476	167708	0	0
T10	1664128	430325	0	0
T15	238808	180907	0	0
T16	174936	98626	0	0
T19	435072	322324	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2796	0	0
T1	353769	0	0	0
T2	96860	3	0	0
T3	58248	1	0	0
T4	0	5	0	0
T5	0	5	0	0
T7	2055964	2	0	0
T8	1888108	1	0	0
T9	313476	1	0	0
T10	1664128	4	0	0
T11	0	3	0	0
T15	238808	4	0	0
T16	174936	0	0	0
T19	435072	2	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T33	0	2	0	0
T49	2817966	1	0	0
T56	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2739	0	0
T1	353769	0	0	0
T2	96860	3	0	0
T3	58248	1	0	0
T4	0	5	0	0
T5	0	5	0	0
T7	2055964	2	0	0
T8	1888108	1	0	0
T9	313476	1	0	0
T10	1664128	4	0	0
T11	0	3	0	0
T15	238808	3	0	0
T16	174936	0	0	0
T19	435072	2	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T33	0	2	0	0
T49	2817966	1	0	0
T56	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2671	0	0
T1	353769	0	0	0
T2	96860	3	0	0
T3	58248	1	0	0
T4	0	5	0	0
T5	0	5	0	0
T7	2055964	2	0	0
T8	1888108	1	0	0
T9	313476	1	0	0
T10	1664128	4	0	0
T11	0	3	0	0
T15	238808	3	0	0
T16	174936	0	0	0
T19	435072	2	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T33	0	2	0	0
T49	2817966	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2621	0	0
T1	353769	0	0	0
T2	96860	3	0	0
T3	58248	1	0	0
T4	0	5	0	0
T5	0	5	0	0
T7	2055964	2	0	0
T8	1888108	1	0	0
T9	313476	1	0	0
T10	1664128	4	0	0
T11	0	3	0	0
T15	238808	3	0	0
T16	174936	0	0	0
T19	435072	2	0	0
T20	0	1	0	0
T21	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T33	0	2	0	0
T49	2817966	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4441	0	0
T2	24215	2	0	0
T3	14562	0	0	0
T4	318678	8	0	0
T5	224557	9	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	156738	0	0	0
T10	832064	0	0	0
T11	10693	0	0	0
T15	59702	0	0	0
T16	87468	8	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	217536	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T23	0	4	0	0
T24	0	6	0	0
T25	0	2	0	0
T26	363487	0	0	0
T27	0	3	0	0
T29	21980	3	0	0
T33	171623	0	0	0
T34	0	3	0	0
T35	0	4	0	0
T40	357562	1	0	0
T49	1878644	0	0	0
T56	0	3	0	0
T65	0	6	0	0
T67	101040	0	0	0
T77	0	1	0	0
T82	12567	0	0	0
T100	0	1	0	0
T101	0	8	0	0
T102	0	1	0	0
T103	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	549168	0	0
T2	24215	88	0	0
T3	14562	0	0	0
T4	318678	626	0	0
T5	224557	1546	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	156738	0	0	0
T10	832064	0	0	0
T11	10693	0	0	0
T15	59702	0	0	0
T16	87468	1858	0	0
T17	0	320	0	0
T18	0	74	0	0
T19	217536	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T23	0	1008	0	0
T24	0	9729	0	0
T25	0	574	0	0
T26	363487	0	0	0
T27	0	175	0	0
T29	21980	78	0	0
T33	171623	0	0	0
T34	0	408	0	0
T35	0	339	0	0
T40	357562	43	0	0
T49	1878644	0	0	0
T56	0	170	0	0
T65	0	1244	0	0
T67	101040	0	0	0
T77	0	53	0	0
T82	12567	0	0	0
T100	0	56	0	0
T101	0	1657	0	0
T102	0	6	0	0
T103	0	1211	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4023	0	0
T2	24215	2	0	0
T3	14562	0	0	0
T4	0	6	0	0
T5	0	9	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	156738	0	0	0
T10	832064	0	0	0
T11	10693	0	0	0
T15	59702	0	0	0
T16	87468	8	0	0
T17	0	1	0	0
T19	217536	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T23	0	1	0	0
T24	0	145	0	0
T25	0	2	0	0
T27	742298	2	0	0
T29	21980	0	0	0
T33	171623	0	0	0
T34	38700	3	0	0
T35	0	25	0	0
T40	0	1	0	0
T41	0	3	0	0
T49	1878644	0	0	0
T56	0	2	0	0
T65	0	1	0	0
T75	712642	0	0	0
T77	101286	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T96	67444	0	0	0
T97	69688	0	0	0
T100	0	1	0	0
T101	0	8	0	0
T103	0	5	0	0
T104	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	295	0	0
T17	0	1	0	0
T18	167925	0	0	0
T23	10745	3	0	0
T24	198957	3	0	0
T29	0	3	0	0
T30	0	5	0	0
T34	38700	0	0	0
T35	215308	3	0	0
T37	0	3	0	0
T44	0	4	0	0
T65	344333	4	0	0
T66	354368	0	0	0
T72	944744	0	0	0
T75	712642	0	0	0
T77	101286	1	0	0
T83	0	4	0	0
T84	0	3	0	0
T89	0	3	0	0
T96	67444	0	0	0
T97	69688	0	0	0
T98	33711	0	0	0
T99	57598	0	0	0
T103	62516	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	5	0	0
T110	0	2	0	0
T111	82023	0	0	0
T112	51951	0	0	0
T113	250175	0	0	0
T114	21831	0	0	0
T115	113679	0	0	0
T116	25939	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1415076	1414808	0	0
T2	96860	96624	0	0
T3	58248	57968	0	0
T7	2055964	2055936	0	0
T8	1888108	1888072	0	0
T9	313476	313220	0	0
T10	1664128	1664096	0	0
T15	238808	238492	0	0
T16	174936	174556	0	0
T19	435072	434688	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1415076	1414808	0	0
T2	96860	96624	0	0
T3	58248	57968	0	0
T7	2055964	2055936	0	0
T8	1888108	1888072	0	0
T9	313476	313220	0	0
T10	1664128	1664096	0	0
T15	238808	238492	0	0
T16	174936	174556	0	0
T19	435072	434688	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T19
1	0	1	Covered	T8,T15,T49
1	1	0	Covered	T16,T11,T29
1	1	1	Covered	T16,T25,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T25,T4
0	1	Covered	T23,T103,T24
1	0	Covered	T4,T65,T30

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T25,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T65,T30

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T25,T4
1	0	Not Covered
1	1	Covered	T23,T103,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T3,T4,T71

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T8
1	Covered	T7,T15,T10

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T2,T19,T33

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T8,T19,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T10,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T7,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T8,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T7
Phase1St	198	Covered	T2,T3,T7
Phase2St	215	Covered	T2,T3,T7
Phase3St	233	Covered	T2,T3,T7
TerminalSt	249	Covered	T2,T3,T7
TimeoutSt	159	Covered	T16,T25,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T2,T3,T7
IdleSt->TimeoutSt	159	Covered	T16,T25,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T81,T62,T83
Phase0St->Phase1St	198	Covered	T2,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T15,T111,T17
Phase1St->Phase2St	215	Covered	T2,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T62,T35,T117
Phase2St->Phase3St	233	Covered	T2,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T64,T82,T77
Phase3St->TerminalSt	249	Covered	T2,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T19,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T25,T4
TimeoutSt->Phase0St	172	Covered	T4,T65,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T25,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T65,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T25,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T25,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T62,T83
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T15,T111,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T62,T35,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T64,T82,T77
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T19,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709906063	0	0	0
CheckAccumTrig0_A	709906063	884	0	0
CheckAccumTrig1_A	709906063	37	0	0
CheckClr_A	709906063	463	0	0
CheckEn_A	709906063	275822624	0	0
CheckPhase0_A	709906063	993	0	0
CheckPhase1_A	709906063	975	0	0
CheckPhase2_A	709906063	944	0	0
CheckPhase3_A	709906063	927	0	0
CheckTimeout0_A	709906063	721	0	0
CheckTimeoutSt1_A	709906063	103236	0	0
CheckTimeoutSt2_A	709906063	588	0	0
CheckTimeoutStTrig_A	709906063	94	0	0
ErrorStAllEscAsserted_A	709906063	0	0	0
ErrorStIsTerminal_A	709906063	0	0	0
EscStateOut_A	709906063	709834722	0	0
u_state_regs_A	709906063	709834722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	884	0	0
T2	24215	1	0	0
T3	14562	1	0	0
T7	513991	1	0	0
T8	472027	1	0	0
T9	78369	0	0	0
T10	416032	1	0	0
T15	59702	4	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	0	1	0	0
T33	0	1	0	0
T49	939322	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	37	0	0
T4	318678	1	0	0
T5	224557	0	0	0
T22	189621	0	0	0
T26	363487	0	0	0
T30	0	1	0	0
T40	357562	0	0	0
T52	0	1	0	0
T55	107992	0	0	0
T63	321161	0	0	0
T65	0	1	0	0
T67	101040	0	0	0
T71	971808	0	0	0
T82	12567	0	0	0
T83	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	463	0	0
T4	0	3	0	0
T5	0	5	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T15	59702	3	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	10308	0	0	0
T21	542322	1	0	0
T26	0	1	0	0
T33	171623	0	0	0
T49	939322	0	0	0
T64	0	6	0	0
T74	0	1	0	0
T81	0	2	0	0
T82	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	275822624	0	0
T1	353769	353701	0	0
T2	24215	2070	0	0
T3	14562	601	0	0
T7	513991	3128	0	0
T8	472027	32620	0	0
T9	78369	78304	0	0
T10	416032	2967	0	0
T15	59702	6797	0	0
T16	43734	12861	0	0
T19	108768	3073	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	993	0	0
T2	24215	1	0	0
T3	14562	1	0	0
T7	513991	1	0	0
T8	472027	1	0	0
T9	78369	0	0	0
T10	416032	1	0	0
T15	59702	4	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	0	1	0	0
T33	0	1	0	0
T49	939322	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	975	0	0
T2	24215	1	0	0
T3	14562	1	0	0
T7	513991	1	0	0
T8	472027	1	0	0
T9	78369	0	0	0
T10	416032	1	0	0
T15	59702	3	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	0	1	0	0
T33	0	1	0	0
T49	939322	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	944	0	0
T2	24215	1	0	0
T3	14562	1	0	0
T7	513991	1	0	0
T8	472027	1	0	0
T9	78369	0	0	0
T10	416032	1	0	0
T15	59702	3	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	0	1	0	0
T33	0	1	0	0
T49	939322	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	927	0	0
T2	24215	1	0	0
T3	14562	1	0	0
T7	513991	1	0	0
T8	472027	1	0	0
T9	78369	0	0	0
T10	416032	1	0	0
T15	59702	3	0	0
T16	43734	0	0	0
T19	108768	2	0	0
T20	0	1	0	0
T33	0	1	0	0
T49	939322	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	721	0	0
T4	0	3	0	0
T5	0	2	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T16	43734	3	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T23	0	2	0	0
T24	0	3	0	0
T25	0	1	0	0
T29	21980	0	0	0
T33	171623	0	0	0
T49	939322	0	0	0
T65	0	2	0	0
T100	0	1	0	0
T101	0	2	0	0
T103	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	103236	0	0
T4	0	165	0	0
T5	0	369	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T16	43734	574	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T23	0	791	0	0
T24	0	173	0	0
T25	0	563	0	0
T29	21980	0	0	0
T33	171623	0	0	0
T49	939322	0	0	0
T65	0	144	0	0
T100	0	56	0	0
T101	0	401	0	0
T103	0	352	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	588	0	0
T4	0	2	0	0
T5	0	2	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T16	43734	3	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T29	21980	0	0	0
T33	171623	0	0	0
T49	939322	0	0	0
T65	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T103	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	94	0	0
T18	167925	0	0	0
T23	10745	1	0	0
T24	198957	1	0	0
T35	215308	0	0	0
T44	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T103	62516	1	0	0
T105	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	5	0	0
T112	51951	0	0	0
T113	250175	0	0	0
T114	21831	0	0	0
T115	113679	0	0	0
T116	25939	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T15,T16
1	0	1	Covered	T1,T8,T49
1	1	0	Covered	T16,T20,T29
1	1	1	Covered	T4,T27,T34

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T27,T34
0	1	Covered	T65,T17,T23
1	0	Covered	T4,T23,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T27,T34
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T23,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T34
1	0	Not Covered
1	1	Covered	T65,T17,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T25
1	Covered	T10,T4,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T11,T25
1	Covered	T2,T11,T56

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T25,T5,T71

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T11,T4,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T11,T4,T26

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T11,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T10,T11
Phase1St	198	Covered	T2,T10,T11
Phase2St	215	Covered	T2,T10,T11
Phase3St	233	Covered	T2,T10,T11
TerminalSt	249	Covered	T2,T10,T11
TimeoutSt	159	Covered	T4,T27,T34

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T2,T10,T11
IdleSt->TimeoutSt	159	Covered	T4,T27,T34
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T18,T118,T38
Phase0St->Phase1St	198	Covered	T2,T10,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T76,T102,T119
Phase1St->Phase2St	215	Covered	T2,T10,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T56,T35,T52
Phase2St->Phase3St	233	Covered	T2,T10,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T119,T85,T120
Phase3St->TerminalSt	249	Covered	T2,T10,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T10,T11,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T27,T34,T101
TimeoutSt->Phase0St	172	Covered	T4,T65,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T27,T34
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T65,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T27,T34
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T27,T34,T101
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T38,T121,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T10,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T76,T102,T119
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T10,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T10,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T56,T35,T94
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T10,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T119,T85,T120
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T10,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T10,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709906063	0	0	0
CheckAccumTrig0_A	709906063	509	0	0
CheckAccumTrig1_A	709906063	26	0	0
CheckClr_A	709906063	250	0	0
CheckEn_A	709906063	383099503	0	0
CheckPhase0_A	709906063	587	0	0
CheckPhase1_A	709906063	569	0	0
CheckPhase2_A	709906063	555	0	0
CheckPhase3_A	709906063	546	0	0
CheckTimeout0_A	709906063	1333	0	0
CheckTimeoutSt1_A	709906063	154735	0	0
CheckTimeoutSt2_A	709906063	1246	0	0
CheckTimeoutStTrig_A	709906063	61	0	0
ErrorStAllEscAsserted_A	709906063	0	0	0
ErrorStIsTerminal_A	709906063	0	0	0
EscStateOut_A	709906063	709834722	0	0
u_state_regs_A	709906063	709834722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	509	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	2	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	3	0	0
T11	0	2	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T49	939322	0	0	0
T56	0	1	0	0
T63	0	1	0	0
T71	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	26	0	0
T4	318678	1	0	0
T5	224557	0	0	0
T12	0	1	0	0
T22	189621	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T26	363487	0	0	0
T37	0	1	0	0
T40	357562	0	0	0
T50	0	1	0	0
T55	107992	0	0	0
T63	321161	0	0	0
T67	101040	0	0	0
T71	971808	0	0	0
T82	12567	0	0	0
T84	0	1	0	0
T85	0	2	0	0
T107	0	2	0	0
T123	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	250	0	0
T4	0	1	0	0
T5	0	1	0	0
T10	416032	2	0	0
T11	10693	1	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T25	18486	0	0	0
T29	21980	0	0	0
T33	171623	0	0	0
T49	939322	0	0	0
T56	0	1	0	0
T64	445980	0	0	0
T72	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T99	0	1	0	0
T102	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	383099503	0	0
T1	353769	3076	0	0
T2	24215	2093	0	0
T3	14562	14491	0	0
T7	513991	513984	0	0
T8	472027	471534	0	0
T9	78369	78304	0	0
T10	416032	3018	0	0
T15	59702	54866	0	0
T16	43734	40116	0	0
T19	108768	101909	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	587	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	3	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	3	0	0
T11	0	2	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T49	939322	0	0	0
T56	0	1	0	0
T63	0	1	0	0
T71	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	569	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	3	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	3	0	0
T11	0	2	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T49	939322	0	0	0
T56	0	1	0	0
T63	0	1	0	0
T71	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	555	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	3	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	3	0	0
T11	0	2	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T49	939322	0	0	0
T61	0	1	0	0
T63	0	1	0	0
T71	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	546	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	3	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	3	0	0
T11	0	2	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T49	939322	0	0	0
T61	0	1	0	0
T63	0	1	0	0
T71	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	1333	0	0
T4	318678	1	0	0
T5	224557	0	0	0
T17	0	1	0	0
T22	189621	0	0	0
T23	0	2	0	0
T24	0	3	0	0
T26	363487	0	0	0
T27	0	1	0	0
T34	0	2	0	0
T35	0	4	0	0
T40	357562	0	0	0
T55	107992	0	0	0
T63	321161	0	0	0
T65	0	1	0	0
T67	101040	0	0	0
T71	971808	0	0	0
T82	12567	0	0	0
T101	0	2	0	0
T103	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	154735	0	0
T4	318678	1	0	0
T5	224557	0	0	0
T17	0	125	0	0
T22	189621	0	0	0
T23	0	217	0	0
T24	0	518	0	0
T26	363487	0	0	0
T27	0	136	0	0
T34	0	233	0	0
T35	0	339	0	0
T40	357562	0	0	0
T55	107992	0	0	0
T63	321161	0	0	0
T65	0	895	0	0
T67	101040	0	0	0
T71	971808	0	0	0
T82	12567	0	0	0
T101	0	423	0	0
T103	0	859	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	1246	0	0
T24	0	2	0	0
T27	742298	1	0	0
T34	38700	2	0	0
T35	0	2	0	0
T41	0	1	0	0
T66	354368	0	0	0
T72	944744	0	0	0
T75	712642	0	0	0
T77	101286	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T96	67444	0	0	0
T97	69688	0	0	0
T98	33711	0	0	0
T99	57598	0	0	0
T101	0	2	0	0
T103	0	4	0	0
T104	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	61	0	0
T17	258714	1	0	0
T23	0	1	0	0
T28	188431	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T37	0	3	0	0
T62	514115	0	0	0
T65	344333	1	0	0
T76	141213	0	0	0
T83	0	1	0	0
T101	33306	0	0	0
T104	0	1	0	0
T106	0	1	0	0
T110	0	2	0	0
T124	101456	0	0	0
T125	501210	0	0	0
T126	554828	0	0	0
T127	41533	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T7,T9
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T25,T4
1	0	1	Covered	T7,T9,T21
1	1	0	Covered	T16,T11,T29
1	1	1	Covered	T2,T25,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T25,T4
0	1	Covered	T77,T65,T23
1	0	Covered	T27,T85,T37

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T25,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T85,T37

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T4
1	0	Covered	T79
1	1	Covered	T77,T65,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T33
1	Covered	T9,T21,T25

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T9,T11
1	Covered	T7,T33,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T9,T33
1	Covered	T2,T11,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T9
1	Covered	T4,T5,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T33,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T25,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T9,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T7,T33

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T7,T9
Phase1St	198	Covered	T2,T7,T9
Phase2St	215	Covered	T2,T7,T9
Phase3St	233	Covered	T2,T7,T9
TerminalSt	249	Covered	T2,T7,T9
TimeoutSt	159	Covered	T2,T25,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T2,T7,T9
IdleSt->TimeoutSt	159	Covered	T2,T25,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T94,T128
Phase0St->Phase1St	198	Covered	T2,T7,T9
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T27,T30
Phase1St->Phase2St	215	Covered	T2,T7,T9
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T18,T129,T130
Phase2St->Phase3St	233	Covered	T2,T7,T9
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T73,T18
Phase3St->TerminalSt	249	Covered	T2,T7,T9
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T11,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T25,T4
TimeoutSt->Phase0St	172	Covered	T27,T77,T65

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T7,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T27,T77,T65
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T25,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T94,T128
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T7,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T7,T9
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T27,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T7,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T7,T9
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T129,T130
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T7,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T7,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T73,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T7,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T7,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T11,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T7,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709906063	0	0	0
CheckAccumTrig0_A	709906063	532	0	0
CheckAccumTrig1_A	709906063	25	0	0
CheckClr_A	709906063	263	0	0
CheckEn_A	709906063	327342456	0	0
CheckPhase0_A	709906063	600	0	0
CheckPhase1_A	709906063	590	0	0
CheckPhase2_A	709906063	582	0	0
CheckPhase3_A	709906063	570	0	0
CheckTimeout0_A	709906063	1227	0	0
CheckTimeoutSt1_A	709906063	151355	0	0
CheckTimeoutSt2_A	709906063	1141	0	0
CheckTimeoutStTrig_A	709906063	56	0	0
ErrorStAllEscAsserted_A	709906063	0	0	0
ErrorStIsTerminal_A	709906063	0	0	0
EscStateOut_A	709906063	709834722	0	0
u_state_regs_A	709906063	709834722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	532	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	2	0	0
T5	0	3	0	0
T7	513991	1	0	0
T8	472027	0	0	0
T9	78369	1	0	0
T10	416032	0	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	2	0	0
T25	0	1	0	0
T33	0	1	0	0
T49	939322	0	0	0
T67	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	25	0	0
T27	742298	1	0	0
T34	38700	0	0	0
T37	0	3	0	0
T52	0	1	0	0
T66	354368	0	0	0
T72	944744	0	0	0
T75	712642	0	0	0
T77	101286	0	0	0
T85	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	2	0	0
T96	67444	0	0	0
T97	69688	0	0	0
T98	33711	0	0	0
T99	57598	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	263	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T25	0	1	0	0
T27	0	3	0	0
T49	939322	0	0	0
T56	0	1	0	0
T71	0	1	0	0
T74	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	327342456	0	0
T1	353769	3053	0	0
T2	24215	9687	0	0
T3	14562	14491	0	0
T7	513991	27353	0	0
T8	472027	7630	0	0
T9	78369	2986	0	0
T10	416032	415437	0	0
T15	59702	59622	0	0
T16	43734	43638	0	0
T19	108768	108671	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	600	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	2	0	0
T5	0	3	0	0
T7	513991	1	0	0
T8	472027	0	0	0
T9	78369	1	0	0
T10	416032	0	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	2	0	0
T25	0	1	0	0
T33	0	1	0	0
T49	939322	0	0	0
T67	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	590	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	2	0	0
T5	0	3	0	0
T7	513991	1	0	0
T8	472027	0	0	0
T9	78369	1	0	0
T10	416032	0	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	2	0	0
T25	0	1	0	0
T33	0	1	0	0
T49	939322	0	0	0
T67	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	582	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	2	0	0
T5	0	3	0	0
T7	513991	1	0	0
T8	472027	0	0	0
T9	78369	1	0	0
T10	416032	0	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	2	0	0
T25	0	1	0	0
T33	0	1	0	0
T49	939322	0	0	0
T67	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	570	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T4	0	2	0	0
T5	0	3	0	0
T7	513991	1	0	0
T8	472027	0	0	0
T9	78369	1	0	0
T10	416032	0	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T21	0	2	0	0
T25	0	1	0	0
T33	0	1	0	0
T49	939322	0	0	0
T67	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	1227	0	0
T2	24215	2	0	0
T3	14562	0	0	0
T4	0	4	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T17	0	1	0	0
T19	108768	0	0	0
T25	0	1	0	0
T27	0	2	0	0
T40	0	1	0	0
T49	939322	0	0	0
T65	0	1	0	0
T77	0	1	0	0
T101	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	151355	0	0
T2	24215	88	0	0
T3	14562	0	0	0
T4	0	460	0	0
T5	0	345	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T17	0	195	0	0
T19	108768	0	0	0
T25	0	11	0	0
T27	0	39	0	0
T40	0	43	0	0
T49	939322	0	0	0
T65	0	187	0	0
T77	0	53	0	0
T101	0	205	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	1141	0	0
T2	24215	2	0	0
T3	14562	0	0	0
T4	0	4	0	0
T5	0	2	0	0
T7	513991	0	0	0
T8	472027	0	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T17	0	1	0	0
T19	108768	0	0	0
T24	0	48	0	0
T25	0	1	0	0
T27	0	1	0	0
T35	0	13	0	0
T40	0	1	0	0
T49	939322	0	0	0
T101	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	56	0	0
T23	0	1	0	0
T24	0	2	0	0
T30	0	2	0	0
T34	38700	0	0	0
T35	0	1	0	0
T44	0	2	0	0
T65	0	1	0	0
T66	354368	0	0	0
T72	944744	0	0	0
T75	712642	0	0	0
T77	101286	1	0	0
T83	0	2	0	0
T89	0	1	0	0
T96	67444	0	0	0
T97	69688	0	0	0
T98	33711	0	0	0
T99	57598	0	0	0
T108	0	1	0	0
T111	82023	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T16,T20
1	0	1	Covered	T1,T10,T49
1	1	0	Covered	T25,T4,T22
1	1	1	Covered	T16,T29,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T29,T5
0	1	Covered	T29,T56,T65
1	0	Covered	T17,T18,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T29,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T18,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T29,T5
1	0	Covered	T78,T80
1	1	Covered	T29,T56,T65

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T33
1	Covered	T7,T8,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T29

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T11,T25,T61

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T33,T26,T67

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T10,T33

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T8,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T7,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T8,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T7
Phase1St	198	Covered	T1,T2,T7
Phase2St	215	Covered	T1,T2,T7
Phase3St	233	Covered	T1,T2,T7
TerminalSt	249	Covered	T1,T2,T7
TimeoutSt	159	Covered	T16,T29,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T1,T2,T7
IdleSt->TimeoutSt	159	Covered	T16,T29,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T18,T52
Phase0St->Phase1St	198	Covered	T1,T2,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T119,T131,T132
Phase1St->Phase2St	215	Covered	T1,T2,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T119,T118
Phase2St->Phase3St	233	Covered	T1,T2,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T30,T133
Phase3St->TerminalSt	249	Covered	T1,T2,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T8,T29
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T5,T56
TimeoutSt->Phase0St	172	Covered	T29,T56,T65

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T29,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T29,T56,T65
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T29,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T5,T56
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T134,T135
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T119,T131,T132
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T119,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T133
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	709906063	0	0	0
CheckAccumTrig0_A	709906063	520	0	0
CheckAccumTrig1_A	709906063	27	0	0
CheckClr_A	709906063	256	0	0
CheckEn_A	709906063	296140471	0	0
CheckPhase0_A	709906063	616	0	0
CheckPhase1_A	709906063	605	0	0
CheckPhase2_A	709906063	590	0	0
CheckPhase3_A	709906063	578	0	0
CheckTimeout0_A	709906063	1160	0	0
CheckTimeoutSt1_A	709906063	139842	0	0
CheckTimeoutSt2_A	709906063	1048	0	0
CheckTimeoutStTrig_A	709906063	84	0	0
ErrorStAllEscAsserted_A	709906063	0	0	0
ErrorStIsTerminal_A	709906063	0	0	0
EscStateOut_A	709906063	709834722	0	0
u_state_regs_A	709906063	709834722	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	520	0	0
T1	353769	1	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T7	513991	1	0	0
T8	472027	8	0	0
T9	78369	1	0	0
T10	416032	1	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T20	0	1	0	0
T25	0	1	0	0
T33	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	27	0	0
T12	0	1	0	0
T13	0	1	0	0
T17	258714	1	0	0
T18	0	1	0	0
T24	0	1	0	0
T28	188431	0	0	0
T44	0	1	0	0
T62	514115	0	0	0
T73	313386	0	0	0
T76	141213	0	0	0
T101	33306	0	0	0
T102	53306	0	0	0
T108	0	1	0	0
T125	501210	0	0	0
T126	554828	0	0	0
T127	41533	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	256	0	0
T1	353769	1	0	0
T2	24215	0	0	0
T3	14562	0	0	0
T4	0	1	0	0
T7	513991	0	0	0
T8	472027	7	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T27	0	2	0	0
T29	0	3	0	0
T55	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	2	0	0
T77	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	296140471	0	0
T1	353769	3090	0	0
T2	24215	6390	0	0
T3	14562	14491	0	0
T7	513991	3199	0	0
T8	472027	7668	0	0
T9	78369	8114	0	0
T10	416032	8903	0	0
T15	59702	59622	0	0
T16	43734	2011	0	0
T19	108768	108671	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	616	0	0
T1	353769	1	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T7	513991	1	0	0
T8	472027	8	0	0
T9	78369	1	0	0
T10	416032	1	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T20	0	1	0	0
T29	0	3	0	0
T33	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	605	0	0
T1	353769	1	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T7	513991	1	0	0
T8	472027	8	0	0
T9	78369	1	0	0
T10	416032	1	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T20	0	1	0	0
T29	0	3	0	0
T33	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	590	0	0
T1	353769	1	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T7	513991	1	0	0
T8	472027	8	0	0
T9	78369	1	0	0
T10	416032	1	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T20	0	1	0	0
T29	0	2	0	0
T33	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	578	0	0
T1	353769	1	0	0
T2	24215	1	0	0
T3	14562	0	0	0
T7	513991	1	0	0
T8	472027	8	0	0
T9	78369	1	0	0
T10	416032	1	0	0
T11	0	1	0	0
T15	59702	0	0	0
T16	43734	0	0	0
T19	108768	0	0	0
T20	0	1	0	0
T29	0	1	0	0
T33	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	1160	0	0
T5	0	5	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T16	43734	5	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T29	21980	3	0	0
T33	171623	0	0	0
T34	0	1	0	0
T49	939322	0	0	0
T56	0	3	0	0
T65	0	2	0	0
T101	0	3	0	0
T102	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	139842	0	0
T5	0	832	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T16	43734	1284	0	0
T18	0	74	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T24	0	9038	0	0
T29	21980	78	0	0
T33	171623	0	0	0
T34	0	175	0	0
T49	939322	0	0	0
T56	0	170	0	0
T65	0	18	0	0
T101	0	628	0	0
T102	0	6	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	1048	0	0
T5	0	5	0	0
T9	78369	0	0	0
T10	416032	0	0	0
T11	10693	0	0	0
T16	43734	5	0	0
T19	108768	0	0	0
T20	10308	0	0	0
T21	542322	0	0	0
T24	0	93	0	0
T29	21980	0	0	0
T30	0	4	0	0
T33	171623	0	0	0
T34	0	1	0	0
T35	0	10	0	0
T41	0	2	0	0
T49	939322	0	0	0
T56	0	2	0	0
T101	0	3	0	0
T139	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	84	0	0
T4	318678	0	0	0
T5	224557	0	0	0
T25	18486	0	0	0
T26	363487	0	0	0
T29	21980	3	0	0
T30	0	2	0	0
T40	357562	0	0	0
T44	0	1	0	0
T54	257963	0	0	0
T56	0	1	0	0
T64	445980	0	0	0
T65	0	2	0	0
T67	101040	0	0	0
T78	0	2	0	0
T82	12567	0	0	0
T84	0	1	0	0
T89	0	2	0	0
T102	0	1	0	0
T140	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709906063	709834722	0	0
T1	353769	353702	0	0
T2	24215	24156	0	0
T3	14562	14492	0	0
T7	513991	513984	0	0
T8	472027	472018	0	0
T9	78369	78305	0	0
T10	416032	416024	0	0
T15	59702	59623	0	0
T16	43734	43639	0	0
T19	108768	108672	0	0