Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65263060	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31590941

1

T1

2645

T2

3293

T3

750

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14615346	1			T1	1039		T2	1249		T3	413
values[0x0]	40148507	1			T1	3615		T2	4559		T3	886
values[0x1]	42090148	1			T1	3681		T2	4537		T3	840

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55801975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41052026

1

T1

3344

T2

4164

T3

945

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	300080	1			T1	30		T2	38		T3	6
valid_sources[0x01]	313094	1			T1	34		T2	133		T3	6
valid_sources[0x02]	310348	1			T1	26		T2	10		T3	5
valid_sources[0x03]	631928	1			T1	20		T2	32		T3	8
valid_sources[0x04]	536951	1			T1	44		T2	38		T3	5
valid_sources[0x05]	786992	1			T1	34		T2	39		T3	9
valid_sources[0x06]	761841	1			T1	37		T2	93		T3	5
valid_sources[0x07]	300352	1			T1	29		T2	72		T3	11
valid_sources[0x08]	304723	1			T1	39		T2	38		T3	6
valid_sources[0x09]	304753	1			T1	30		T2	121		T3	3
valid_sources[0x0a]	299582	1			T1	32		T2	43		T3	13
valid_sources[0x0b]	751673	1			T1	37		T2	15		T3	6
valid_sources[0x0c]	301840	1			T1	39		T2	40		T3	8
valid_sources[0x0d]	302182	1			T1	31		T2	55		T3	10
valid_sources[0x0e]	302004	1			T1	44		T2	74		T3	15
valid_sources[0x0f]	305331	1			T1	23		T2	110		T3	12
valid_sources[0x10]	535678	1			T1	33		T2	25		T3	16
valid_sources[0x11]	297111	1			T1	32		T2	20		T3	6
valid_sources[0x12]	295179	1			T1	33		T2	79		T3	7
valid_sources[0x13]	1159615	1			T1	19		T2	4		T3	8
valid_sources[0x14]	307754	1			T1	32		T2	67		T3	6
valid_sources[0x15]	1532370	1			T1	33		T2	76		T3	6
valid_sources[0x16]	311360	1			T1	25		T2	23		T3	3
valid_sources[0x17]	309013	1			T1	25		T2	46		T3	8
valid_sources[0x18]	302114	1			T1	36		T2	47		T3	10
valid_sources[0x19]	720588	1			T1	29		T2	93		T3	7
valid_sources[0x1a]	310561	1			T1	33		T2	12		T3	6
valid_sources[0x1b]	304627	1			T1	29		T2	46		T3	12
valid_sources[0x1c]	307372	1			T1	31		T2	43		T3	5
valid_sources[0x1d]	304871	1			T1	36		T2	95		T3	16
valid_sources[0x1e]	529894	1			T1	24		T2	30		T3	14
valid_sources[0x1f]	304890	1			T1	27		T2	71		T3	7
valid_sources[0x20]	304570	1			T1	30		T2	30		T3	8
valid_sources[0x21]	582813	1			T1	37		T2	18		T3	4
valid_sources[0x22]	323443	1			T1	22		T2	30		T3	7
valid_sources[0x23]	305501	1			T1	27		T2	61		T3	8
valid_sources[0x24]	306896	1			T1	37		T2	9		T3	12
valid_sources[0x25]	308395	1			T1	31		T2	34		T3	9
valid_sources[0x26]	300751	1			T1	36		T2	9		T3	7
valid_sources[0x27]	301023	1			T1	32		T2	31		T3	14
valid_sources[0x28]	316400	1			T1	24		T2	19		T3	3
valid_sources[0x29]	302548	1			T1	26		T2	13		T3	12
valid_sources[0x2a]	314734	1			T1	30		T2	73		T3	6
valid_sources[0x2b]	579107	1			T1	49		T2	64		T3	3
valid_sources[0x2c]	313919	1			T1	30		T2	30		T3	14
valid_sources[0x2d]	313137	1			T1	27		T2	14		T3	12
valid_sources[0x2e]	305143	1			T1	30		T2	2		T3	3
valid_sources[0x2f]	303678	1			T1	34		T2	44		T3	9
valid_sources[0x30]	311296	1			T1	30		T2	70		T3	2
valid_sources[0x31]	314473	1			T1	26		T2	58		T3	6
valid_sources[0x32]	317558	1			T1	32		T2	21		T3	8
valid_sources[0x33]	293792	1			T1	17		T2	31		T3	12
valid_sources[0x34]	292053	1			T1	42		T3	13		T16	159
valid_sources[0x35]	530460	1			T1	22		T2	57		T3	4
valid_sources[0x36]	704845	1			T1	25		T2	36		T3	7
valid_sources[0x37]	307239	1			T1	35		T2	38		T3	12
valid_sources[0x38]	294953	1			T1	31		T2	33		T3	10
valid_sources[0x39]	308959	1			T1	37		T2	50		T3	15
valid_sources[0x3a]	296248	1			T1	35		T2	33		T3	9
valid_sources[0x3b]	312964	1			T1	49		T3	7		T16	167
valid_sources[0x3c]	301900	1			T1	33		T2	115		T3	3
valid_sources[0x3d]	304146	1			T1	26		T2	65		T3	14
valid_sources[0x3e]	825630	1			T1	29		T2	26		T3	9
valid_sources[0x3f]	328986	1			T1	28		T2	23		T3	13
valid_sources[0x40]	305569	1			T1	36		T2	66		T3	3
valid_sources[0x41]	310985	1			T1	34		T2	50		T3	6
valid_sources[0x42]	310439	1			T1	40		T2	14		T3	6
valid_sources[0x43]	301588	1			T1	37		T2	107		T3	7
valid_sources[0x44]	311619	1			T1	27		T2	7		T3	2
valid_sources[0x45]	345128	1			T1	33		T2	21		T3	11
valid_sources[0x46]	319964	1			T1	28		T2	80		T3	11
valid_sources[0x47]	302462	1			T1	24		T2	28		T3	4
valid_sources[0x48]	314644	1			T1	24		T2	47		T3	11
valid_sources[0x49]	759675	1			T1	33		T2	48		T3	8
valid_sources[0x4a]	315147	1			T1	37		T3	8		T16	219
valid_sources[0x4b]	300353	1			T1	40		T2	36		T3	12
valid_sources[0x4c]	308016	1			T1	30		T2	57		T3	11
valid_sources[0x4d]	316896	1			T1	36		T2	62		T3	8
valid_sources[0x4e]	316580	1			T1	28		T2	63		T3	6
valid_sources[0x4f]	304554	1			T1	42		T2	10		T3	10
valid_sources[0x50]	507915	1			T1	26		T2	34		T3	4
valid_sources[0x51]	306416	1			T1	34		T2	48		T3	12
valid_sources[0x52]	312034	1			T1	27		T2	36		T3	4
valid_sources[0x53]	304416	1			T1	35		T2	44		T3	9
valid_sources[0x54]	302953	1			T1	28		T2	49		T3	3
valid_sources[0x55]	307381	1			T1	23		T2	56		T3	10
valid_sources[0x56]	305764	1			T1	26		T2	13		T3	8
valid_sources[0x57]	319338	1			T1	40		T2	32		T3	7
valid_sources[0x58]	294607	1			T1	36		T2	27		T3	16
valid_sources[0x59]	296367	1			T1	43		T2	106		T3	11
valid_sources[0x5a]	302195	1			T1	47		T2	119		T3	7
valid_sources[0x5b]	304544	1			T1	22		T2	28		T3	5
valid_sources[0x5c]	708781	1			T1	41		T2	33		T3	8
valid_sources[0x5d]	309035	1			T1	27		T2	7		T3	13
valid_sources[0x5e]	302779	1			T1	30		T3	14		T16	146
valid_sources[0x5f]	301287	1			T1	29		T3	10		T16	195
valid_sources[0x60]	310030	1			T1	25		T2	31		T3	9
valid_sources[0x61]	309785	1			T1	38		T2	119		T3	5
valid_sources[0x62]	587318	1			T1	34		T2	46		T3	9
valid_sources[0x63]	303258	1			T1	36		T2	3		T3	15
valid_sources[0x64]	302197	1			T1	47		T2	27		T3	8
valid_sources[0x65]	313792	1			T1	31		T2	26		T3	5
valid_sources[0x66]	297827	1			T1	46		T2	12		T3	5
valid_sources[0x67]	317763	1			T1	40		T2	59		T3	8
valid_sources[0x68]	301994	1			T1	26		T2	33		T3	8
valid_sources[0x69]	321050	1			T1	37		T2	26		T3	3
valid_sources[0x6a]	298575	1			T1	28		T2	7		T3	12
valid_sources[0x6b]	311488	1			T1	34		T2	24		T3	18
valid_sources[0x6c]	317761	1			T1	31		T2	4		T3	1
valid_sources[0x6d]	301897	1			T1	32		T3	5		T16	105
valid_sources[0x6e]	303457	1			T1	27		T2	58		T3	14
valid_sources[0x6f]	299097	1			T1	31		T2	28		T3	8
valid_sources[0x70]	317224	1			T1	40		T2	13		T3	3
valid_sources[0x71]	308491	1			T1	43		T2	7		T3	16
valid_sources[0x72]	331446	1			T1	30		T2	20		T3	9
valid_sources[0x73]	317784	1			T1	49		T2	9		T3	7
valid_sources[0x74]	304152	1			T1	42		T2	22		T3	6
valid_sources[0x75]	304856	1			T1	34		T2	19		T3	18
valid_sources[0x76]	752926	1			T1	39		T2	2		T3	5
valid_sources[0x77]	681223	1			T1	35		T2	39		T3	10
valid_sources[0x78]	302547	1			T1	24		T2	46		T3	15
valid_sources[0x79]	311904	1			T1	32		T2	37		T3	7
valid_sources[0x7a]	300764	1			T1	31		T2	14		T3	10
valid_sources[0x7b]	776355	1			T1	28		T2	23		T3	8
valid_sources[0x7c]	326933	1			T1	25		T2	51		T3	16
valid_sources[0x7d]	308431	1			T1	36		T2	20		T3	11
valid_sources[0x7e]	508354	1			T1	31		T2	24		T3	8
valid_sources[0x7f]	308360	1			T1	25		T2	3		T3	14
valid_sources[0x80]	311688	1			T1	33		T2	10		T3	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7274662

1

T1

500

T2

597

T3

217

values[0x0]

all_enables

biggest_size

15355683

1

T1

1367

T2

1680

T3

339

values[0x1]

all_enables

biggest_size

8960596

1

T1

778

T2

1016

T3

194