Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T198,T199
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T15

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13352	0	0
DisabledNoTrigBkwd_A	2147483647	725745	0	0
DisabledNoTrigFwd_A	2147483647	1476853534	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13352	0	0
T78	15912	0	0	0
T118	155838	0	0	0
T197	4590	775	0	0
T198	2809	521	0	0
T199	7676	463	0	0
T200	8091	382	0	0
T201	0	1142	0	0
T202	0	1095	0	0
T203	0	630	0	0
T204	0	700	0	0
T205	0	295	0	0
T206	0	860	0	0
T207	0	484	0	0
T208	0	638	0	0
T209	0	277	0	0
T210	0	1078	0	0
T211	0	986	0	0
T212	0	698	0	0
T213	0	855	0	0
T214	0	865	0	0
T215	0	395	0	0
T216	0	213	0	0
T217	388670	0	0	0
T218	346389	0	0	0
T219	17678	0	0	0
T220	24458	0	0	0
T221	74731	0	0	0
T222	13449	0	0	0
T223	1558618	0	0	0
T224	1827124	0	0	0
T225	43131	0	0	0
T226	1319595	0	0	0
T227	252162	0	0	0
T228	237392	0	0	0
T229	6290	0	0	0
T230	31032	0	0	0
T231	36361	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	725745	0	0
T1	740828	1	0	0
T2	222036	3	0	0
T3	52142	0	0	0
T4	487048	8537	0	0
T5	883180	4601	0	0
T6	1196528	1998	0	0
T8	902264	1585	0	0
T9	1654332	0	0	0
T14	0	2124	0	0
T15	89874	79	0	0
T16	664388	455	0	0
T17	327540	10	0	0
T21	0	40	0	0
T25	0	32	0	0
T39	86403	41	0	0
T40	42850	27	0	0
T41	24589	68	0	0
T42	0	21	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1476853534	0	0
T1	2963312	1129343	0	0
T2	444072	346560	0	0
T3	104284	79645	0	0
T4	487048	667245	0	0
T5	883180	271422	0	0
T6	1196528	971676	0	0
T8	902264	686121	0	0
T15	119832	56554	0	0
T16	664388	184163	0	0
T17	327540	254830	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T201,T205
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655319166	5381	0	0
DisabledNoTrigBkwd_A	655319166	213993	0	0
DisabledNoTrigFwd_A	655319166	324860126	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	5381	0	0
T198	2809	521	0	0
T199	3838	0	0	0
T200	2697	0	0	0
T201	0	1142	0	0
T205	0	295	0	0
T206	0	860	0	0
T207	0	484	0	0
T211	0	986	0	0
T212	0	698	0	0
T215	0	395	0	0
T220	24458	0	0	0
T221	74731	0	0	0
T222	13449	0	0	0
T223	779309	0	0	0
T224	913562	0	0	0
T225	14377	0	0	0
T226	439865	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	213993	0	0
T2	111018	3	0	0
T3	26071	0	0	0
T4	121762	656	0	0
T5	220795	0	0	0
T6	299132	1143	0	0
T8	225566	0	0	0
T15	29958	42	0	0
T16	166097	262	0	0
T17	81885	10	0	0
T25	0	10	0	0
T39	28801	17	0	0
T40	0	11	0	0
T41	0	68	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	324860126	0	0
T1	740828	92013	0	0
T2	111018	126707	0	0
T3	26071	20835	0	0
T4	121762	110915	0	0
T5	220795	220788	0	0
T6	299132	358065	0	0
T8	225566	225559	0	0
T15	29958	1703	0	0
T16	166097	4594	0	0
T17	81885	9355	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T213
1	1	Covered	T1,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655319166	1237	0	0
DisabledNoTrigBkwd_A	655319166	157136	0	0
DisabledNoTrigFwd_A	655319166	392112252	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1237	0	0
T78	15912	0	0	0
T118	77919	0	0	0
T200	2697	382	0	0
T213	0	855	0	0
T225	14377	0	0	0
T226	439865	0	0	0
T227	126081	0	0	0
T228	118696	0	0	0
T229	3145	0	0	0
T230	31032	0	0	0
T231	36361	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	157136	0	0
T1	740828	1	0	0
T2	111018	0	0	0
T3	26071	0	0	0
T4	121762	75	0	0
T5	220795	1238	0	0
T6	299132	513	0	0
T8	225566	0	0	0
T14	0	2	0	0
T15	29958	5	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T21	0	12	0	0
T25	0	12	0	0
T39	0	20	0	0
T42	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	392112252	0	0
T1	740828	265497	0	0
T2	111018	111008	0	0
T3	26071	20848	0	0
T4	121762	108531	0	0
T5	220795	17079	0	0
T6	299132	194444	0	0
T8	225566	225183	0	0
T15	29958	26560	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T3,T16
1	1	Covered	T3,T15,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T203
1	1	Covered	T3,T15,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T16,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655319166	1093	0	0
DisabledNoTrigBkwd_A	655319166	165208	0	0
DisabledNoTrigFwd_A	655319166	380407835	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1093	0	0
T118	77919	0	0	0
T199	3838	463	0	0
T200	2697	0	0	0
T203	0	630	0	0
T223	779309	0	0	0
T224	913562	0	0	0
T225	14377	0	0	0
T226	439865	0	0	0
T227	126081	0	0	0
T228	118696	0	0	0
T229	3145	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	165208	0	0
T4	121762	1801	0	0
T5	220795	1889	0	0
T6	299132	213	0	0
T8	225566	1585	0	0
T9	827166	0	0	0
T15	29958	32	0	0
T16	166097	89	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	3	0	0
T39	28801	2	0	0
T40	21425	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	380407835	0	0
T1	740828	740760	0	0
T2	111018	2042	0	0
T3	26071	18981	0	0
T4	121762	295960	0	0
T5	220795	2130	0	0
T6	299132	225822	0	0
T8	225566	10227	0	0
T15	29958	592	0	0
T16	166097	12906	0	0
T17	81885	81825	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T202,T204
1	1	Covered	T1,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	655319166	5641	0	0
DisabledNoTrigBkwd_A	655319166	189408	0	0
DisabledNoTrigFwd_A	655319166	379473321	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	5641	0	0
T46	98423	0	0	0
T47	226456	0	0	0
T72	28735	0	0	0
T108	19900	0	0	0
T197	4590	775	0	0
T202	0	1095	0	0
T204	0	700	0	0
T208	0	638	0	0
T209	0	277	0	0
T210	0	1078	0	0
T214	0	865	0	0
T216	0	213	0	0
T217	388670	0	0	0
T218	346389	0	0	0
T219	17678	0	0	0
T232	41570	0	0	0
T233	666826	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	189408	0	0
T4	121762	6005	0	0
T5	220795	1474	0	0
T6	299132	129	0	0
T8	225566	0	0	0
T9	827166	0	0	0
T14	0	2122	0	0
T16	166097	104	0	0
T17	81885	0	0	0
T21	0	27	0	0
T25	0	7	0	0
T39	28801	2	0	0
T40	21425	7	0	0
T41	24589	0	0	0
T42	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	379473321	0	0
T1	740828	31073	0	0
T2	111018	106803	0	0
T3	26071	18981	0	0
T4	121762	151839	0	0
T5	220795	31425	0	0
T6	299132	193345	0	0
T8	225566	225152	0	0
T15	29958	27699	0	0
T16	166097	663	0	0
T17	81885	81825	0	0