Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.87	100.00	89.36		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	42	89.36
Logical	47	42	89.36
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T4
1	0	1	Covered	T1,T2,T15
1	1	0	Covered	T3,T15,T4
1	1	1	Covered	T3,T15,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T15,T4
0	1	Covered	T18,T19,T20
1	0	Covered	T6,T21,T19

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T21,T19

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T4
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T4,T5,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T2,T15,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T1,T15,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T4,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T15,T16

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T15,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T2,T15
IdleSt->TimeoutSt	159	Covered	T3,T15,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T19,T20
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T19,T22,T23
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T6,T19,T24
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T25,T26,T27
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T15,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T15,T4
TimeoutSt->Phase0St	172	Covered	T6,T21,T18

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T21,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T22,T23
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T19,T24
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T15,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	988	0	0
CheckAccumTrig0_A	2147483647	2344	0	0
CheckAccumTrig1_A	2147483647	107	0	0
CheckClr_A	2147483647	1100	0	0
CheckEn_A	2147483647	1092411492	0	0
CheckPhase0_A	2147483647	2645	0	0
CheckPhase1_A	2147483647	2589	0	0
CheckPhase2_A	2147483647	2532	0	0
CheckPhase3_A	2147483647	2495	0	0
CheckTimeout0_A	2147483647	6281	0	0
CheckTimeoutSt1_A	2147483647	591867	0	0
CheckTimeoutSt2_A	2147483647	5915	0	0
CheckTimeoutStTrig_A	2147483647	253	0	0
ErrorStAllEscAsserted_A	2147483647	4977	0	0
ErrorStIsTerminal_A	2147483647	4137	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	988	0	0
T10	124620	289	0	0
T11	0	136	0	0
T12	0	146	0	0
T22	1494396	0	0	0
T29	0	269	0	0
T30	0	148	0	0
T31	497720	0	0	0
T32	578944	0	0	0
T33	772656	0	0	0
T34	3504608	0	0	0
T35	1226728	0	0	0
T36	255520	0	0	0
T37	1693488	0	0	0
T38	145960	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2344	0	0
T1	740828	1	0	0
T2	222036	1	0	0
T3	52142	0	0	0
T4	487048	20	0	0
T5	883180	3	0	0
T6	1196528	35	0	0
T8	902264	2	0	0
T9	1654332	0	0	0
T14	0	2	0	0
T15	89874	5	0	0
T16	664388	3	0	0
T17	327540	1	0	0
T21	0	1	0	0
T25	0	8	0	0
T39	86403	6	0	0
T40	42850	3	0	0
T41	24589	1	0	0
T42	0	2	0	0
T43	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107	0	0
T6	299132	2	0	0
T7	44339	0	0	0
T9	827166	0	0	0
T13	394208	0	0	0
T14	458225	0	0	0
T17	81885	0	0	0
T18	58985	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T21	154486	1	0	0
T23	359305	2	0	0
T24	826266	1	0	0
T25	44619	0	0	0
T26	32685	0	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T41	24589	0	0	0
T42	281135	0	0	0
T43	180264	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	4486	0	0	0
T60	14444	0	0	0
T61	483164	0	0	0
T62	83883	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1100	0	0
T3	26071	1	0	0
T4	487048	10	0	0
T5	883180	0	0	0
T6	1196528	24	0	0
T7	44339	0	0	0
T8	902264	1	0	0
T9	2481498	0	0	0
T15	89874	3	0	0
T16	498291	0	0	0
T17	327540	0	0	0
T19	0	24	0	0
T20	0	7	0	0
T23	0	5	0	0
T25	0	7	0	0
T26	0	1	0	0
T27	0	1	0	0
T38	0	3	0	0
T39	115204	3	0	0
T40	85700	0	0	0
T41	24589	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1092411492	0	0
T1	2963312	867514	0	0
T2	444072	346560	0	0
T3	104284	79641	0	0
T4	487048	648448	0	0
T5	883180	234789	0	0
T6	1196528	804819	0	0
T8	902264	684510	0	0
T15	119832	56552	0	0
T16	664388	184162	0	0
T17	327540	254827	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2645	0	0
T1	740828	1	0	0
T2	222036	1	0	0
T3	78213	1	0	0
T4	487048	21	0	0
T5	883180	3	0	0
T6	1196528	33	0	0
T8	902264	2	0	0
T9	827166	0	0	0
T14	0	2	0	0
T15	119832	5	0	0
T16	664388	3	0	0
T17	327540	1	0	0
T21	0	3	0	0
T25	0	9	0	0
T39	86403	6	0	0
T40	42850	3	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2589	0	0
T1	740828	1	0	0
T2	222036	1	0	0
T3	78213	1	0	0
T4	487048	21	0	0
T5	883180	3	0	0
T6	1196528	32	0	0
T8	902264	2	0	0
T9	827166	0	0	0
T14	0	2	0	0
T15	119832	5	0	0
T16	664388	3	0	0
T17	327540	1	0	0
T21	0	3	0	0
T25	0	9	0	0
T39	86403	6	0	0
T40	42850	3	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2532	0	0
T1	740828	1	0	0
T2	222036	1	0	0
T3	78213	1	0	0
T4	487048	21	0	0
T5	883180	3	0	0
T6	1196528	28	0	0
T8	902264	2	0	0
T9	827166	0	0	0
T14	0	2	0	0
T15	119832	5	0	0
T16	664388	3	0	0
T17	327540	1	0	0
T21	0	3	0	0
T25	0	9	0	0
T39	86403	6	0	0
T40	42850	3	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2495	0	0
T1	740828	1	0	0
T2	222036	1	0	0
T3	78213	1	0	0
T4	487048	21	0	0
T5	883180	3	0	0
T6	1196528	28	0	0
T8	902264	2	0	0
T9	827166	0	0	0
T14	0	2	0	0
T15	119832	5	0	0
T16	664388	3	0	0
T17	327540	1	0	0
T21	0	3	0	0
T25	0	8	0	0
T39	86403	6	0	0
T40	42850	3	0	0
T41	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6281	0	0
T3	104284	4	0	0
T4	487048	11	0	0
T5	883180	0	0	0
T6	1196528	11	0	0
T8	902264	1	0	0
T15	119832	1	0	0
T16	664388	0	0	0
T17	327540	0	0	0
T18	0	6	0	0
T19	0	15	0	0
T20	0	14	0	0
T21	0	2	0	0
T23	0	4	0	0
T24	0	164	0	0
T25	0	3	0	0
T38	0	1	0	0
T39	115204	1	0	0
T40	85700	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	27	0	0
T66	0	9	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	591867	0	0
T3	104284	621	0	0
T4	487048	871	0	0
T5	883180	0	0	0
T6	1196528	1562	0	0
T8	902264	263	0	0
T15	119832	57	0	0
T16	664388	0	0	0
T17	327540	0	0	0
T18	0	971	0	0
T19	0	1042	0	0
T20	0	2053	0	0
T21	0	2	0	0
T23	0	393	0	0
T24	0	9698	0	0
T25	0	391	0	0
T38	0	293	0	0
T39	115204	15	0	0
T40	85700	0	0	0
T44	0	3	0	0
T62	0	111	0	0
T65	0	5743	0	0
T66	0	5516	0	0
T67	0	68	0	0
T68	0	120	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5915	0	0
T3	78213	3	0	0
T4	487048	10	0	0
T5	883180	0	0	0
T6	1196528	8	0	0
T8	902264	1	0	0
T9	827166	0	0	0
T15	119832	1	0	0
T16	664388	0	0	0
T17	327540	0	0	0
T18	0	5	0	0
T19	0	11	0	0
T20	0	8	0	0
T23	0	3	0	0
T24	0	206	0	0
T25	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	115204	1	0	0
T40	85700	0	0	0
T62	0	10	0	0
T65	0	60	0	0
T66	0	8	0	0
T68	0	1	0	0
T69	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253	0	0
T18	58985	1	0	0
T19	301796	2	0	0
T20	1294372	3	0	0
T24	0	2	0	0
T26	32685	0	0	0
T42	281135	0	0	0
T43	180264	0	0	0
T44	131768	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	9	0	0
T59	4486	0	0	0
T60	14444	0	0	0
T61	483164	0	0	0
T62	0	1	0	0
T63	52542	0	0	0
T64	16641	0	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	67986	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	6	0	0
T73	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	343019	0	0	0
T80	646570	0	0	0
T81	706106	0	0	0
T82	29370	0	0	0
T83	211382	0	0	0
T84	46880	0	0	0
T85	19390	0	0	0
T86	121349	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4977	0	0
T10	124620	1446	0	0
T11	0	680	0	0
T12	0	713	0	0
T22	1494396	0	0	0
T29	0	1439	0	0
T30	0	699	0	0
T31	497720	0	0	0
T32	578944	0	0	0
T33	772656	0	0	0
T34	3504608	0	0	0
T35	1226728	0	0	0
T36	255520	0	0	0
T37	1693488	0	0	0
T38	145960	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4137	0	0
T10	124620	1206	0	0
T11	0	560	0	0
T12	0	593	0	0
T22	1494396	0	0	0
T29	0	1199	0	0
T30	0	579	0	0
T31	497720	0	0	0
T32	578944	0	0	0
T33	772656	0	0	0
T34	3504608	0	0	0
T35	1226728	0	0	0
T36	255520	0	0	0
T37	1693488	0	0	0
T38	145960	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2963312	2963040	0	0
T2	444072	444032	0	0
T3	104284	103964	0	0
T4	487048	486704	0	0
T5	883180	883152	0	0
T6	1196528	1196396	0	0
T8	902264	902236	0	0
T15	119832	119464	0	0
T16	664388	664000	0	0
T17	327540	327300	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2963312	2963040	0	0
T2	444072	444032	0	0
T3	104284	103964	0	0
T4	487048	486704	0	0
T5	883180	883152	0	0
T6	1196528	1196396	0	0
T8	902264	902236	0	0
T15	119832	119464	0	0
T16	664388	664000	0	0
T17	327540	327300	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T4
1	0	1	Covered	T1,T2,T16
1	1	0	Covered	T3,T4,T8
1	1	1	Covered	T3,T6,T39

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T39
0	1	Covered	T19,T20,T67
1	0	Covered	T6,T20,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T39
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T20,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T39
1	0	Not Covered
1	1	Covered	T19,T20,T67

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T4,T6,T39

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T6,T39,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T4,T6
1	Covered	T2,T15,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T15,T4,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T15,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T4,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T15,T16
Phase1St	198	Covered	T2,T15,T16
Phase2St	215	Covered	T2,T15,T16
Phase3St	233	Covered	T2,T15,T16
TerminalSt	249	Covered	T2,T15,T16
TimeoutSt	159	Covered	T3,T6,T39

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T15,T16
IdleSt->TimeoutSt	159	Covered	T3,T6,T39
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T19,T28
Phase0St->Phase1St	198	Covered	T2,T15,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T22,T69,T55
Phase1St->Phase2St	215	Covered	T2,T15,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T19,T24
Phase2St->Phase3St	233	Covered	T2,T15,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T26,T87
Phase3St->TerminalSt	249	Covered	T2,T15,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T4,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T6,T39
TimeoutSt->Phase0St	172	Covered	T6,T19,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T39
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T19,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T39
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T39
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T28,T55
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T15,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T15,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T22,T69,T55
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T15,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T15,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T19,T24
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T15,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T26,T87
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T15,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T15,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655319166	238	0	0
CheckAccumTrig0_A	655319166	890	0	0
CheckAccumTrig1_A	655319166	46	0	0
CheckClr_A	655319166	467	0	0
CheckEn_A	655084264	228279553	0	0
CheckPhase0_A	655319166	979	0	0
CheckPhase1_A	655319166	955	0	0
CheckPhase2_A	655319166	927	0	0
CheckPhase3_A	655319166	911	0	0
CheckTimeout0_A	655319166	1656	0	0
CheckTimeoutSt1_A	655319166	126935	0	0
CheckTimeoutSt2_A	655319166	1545	0	0
CheckTimeoutStTrig_A	655319166	64	0	0
ErrorStAllEscAsserted_A	655319166	1274	0	0
ErrorStIsTerminal_A	655319166	1064	0	0
EscStateOut_A	655082827	655014024	0	0
u_state_regs_A	655319166	655160807	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	238	0	0
T10	31155	84	0	0
T11	0	28	0	0
T12	0	32	0	0
T22	373599	0	0	0
T29	0	60	0	0
T30	0	34	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	890	0	0
T2	111018	1	0	0
T3	26071	0	0	0
T4	121762	6	0	0
T5	220795	0	0	0
T6	299132	14	0	0
T8	225566	0	0	0
T15	29958	2	0	0
T16	166097	1	0	0
T17	81885	1	0	0
T25	0	3	0	0
T39	28801	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	46	0	0
T6	299132	2	0	0
T7	44339	0	0	0
T9	827166	0	0	0
T13	197104	0	0	0
T17	81885	0	0	0
T20	0	2	0	0
T21	77243	0	0	0
T24	0	1	0	0
T25	44619	0	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T41	24589	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	467	0	0
T4	121762	4	0	0
T5	220795	0	0	0
T6	299132	9	0	0
T8	225566	0	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T19	0	6	0	0
T20	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T39	28801	2	0	0
T40	21425	0	0	0
T42	0	1	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655084264	228279553	0	0
T1	740828	92013	0	0
T2	111018	126707	0	0
T3	26071	20834	0	0
T4	121762	108557	0	0
T5	220795	220788	0	0
T6	299132	192025	0	0
T8	225566	225559	0	0
T15	29958	1703	0	0
T16	166097	4594	0	0
T17	81885	9355	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	979	0	0
T2	111018	1	0	0
T3	26071	0	0	0
T4	121762	6	0	0
T5	220795	0	0	0
T6	299132	14	0	0
T8	225566	0	0	0
T15	29958	2	0	0
T16	166097	1	0	0
T17	81885	1	0	0
T25	0	3	0	0
T39	28801	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	955	0	0
T2	111018	1	0	0
T3	26071	0	0	0
T4	121762	6	0	0
T5	220795	0	0	0
T6	299132	14	0	0
T8	225566	0	0	0
T15	29958	2	0	0
T16	166097	1	0	0
T17	81885	1	0	0
T25	0	3	0	0
T39	28801	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	927	0	0
T2	111018	1	0	0
T3	26071	0	0	0
T4	121762	6	0	0
T5	220795	0	0	0
T6	299132	13	0	0
T8	225566	0	0	0
T15	29958	2	0	0
T16	166097	1	0	0
T17	81885	1	0	0
T25	0	3	0	0
T39	28801	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	911	0	0
T2	111018	1	0	0
T3	26071	0	0	0
T4	121762	6	0	0
T5	220795	0	0	0
T6	299132	13	0	0
T8	225566	0	0	0
T15	29958	2	0	0
T16	166097	1	0	0
T17	81885	1	0	0
T25	0	2	0	0
T39	28801	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1656	0	0
T3	26071	1	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	6	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T19	0	7	0	0
T20	0	4	0	0
T25	0	1	0	0
T39	28801	1	0	0
T40	21425	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T65	0	15	0	0
T67	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	126935	0	0
T3	26071	167	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	683	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T19	0	439	0	0
T20	0	157	0	0
T25	0	137	0	0
T39	28801	15	0	0
T40	21425	0	0	0
T44	0	3	0	0
T65	0	3254	0	0
T66	0	52	0	0
T67	0	68	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1545	0	0
T3	26071	1	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	4	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T19	0	5	0	0
T20	0	1	0	0
T24	0	43	0	0
T25	0	1	0	0
T35	0	1	0	0
T39	28801	1	0	0
T40	21425	0	0	0
T65	0	15	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	64	0	0
T19	301796	2	0	0
T20	647186	1	0	0
T24	0	1	0	0
T44	65884	0	0	0
T48	0	1	0	0
T67	33993	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	343019	0	0	0
T80	323285	0	0	0
T81	353053	0	0	0
T82	14685	0	0	0
T83	105691	0	0	0
T84	23440	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1274	0	0
T10	31155	358	0	0
T11	0	169	0	0
T12	0	173	0	0
T22	373599	0	0	0
T29	0	392	0	0
T30	0	182	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1064	0	0
T10	31155	298	0	0
T11	0	139	0	0
T12	0	143	0	0
T22	373599	0	0	0
T29	0	332	0	0
T30	0	152	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655082827	655014024	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	655160807	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T15,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T8
1	0	1	Covered	T1,T4,T42
1	1	0	Covered	T3,T15,T4
1	1	1	Covered	T3,T4,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T20,T65,T66
1	0	Covered	T21,T19,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T19,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Not Covered
1	1	Covered	T20,T65,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T6
1	Covered	T4,T5,T42

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T4
1	Covered	T6,T25,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T4
1	Covered	T15,T6,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T4,T5
1	Covered	T1,T15,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T15,T6,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T6,T39

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T6,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T15,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T15,T4
Phase1St	198	Covered	T1,T15,T4
Phase2St	215	Covered	T1,T15,T4
Phase3St	233	Covered	T1,T15,T4
TerminalSt	249	Covered	T1,T15,T4
TimeoutSt	159	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T1,T15,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T20,T88
Phase0St->Phase1St	198	Covered	T1,T15,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T19,T47,T75
Phase1St->Phase2St	215	Covered	T1,T15,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T48,T89,T90
Phase2St->Phase3St	233	Covered	T1,T15,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T54,T91,T92
Phase3St->TerminalSt	249	Covered	T1,T15,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T4,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T6
TimeoutSt->Phase0St	172	Covered	T21,T19,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T19,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T88,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T15,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T15,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T47,T75
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T15,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T15,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T48,T89,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T15,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T15,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T54,T91,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T15,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T15,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T6,T61
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655319166	234	0	0
CheckAccumTrig0_A	655319166	454	0	0
CheckAccumTrig1_A	655319166	20	0	0
CheckClr_A	655319166	183	0	0
CheckEn_A	655084264	282300684	0	0
CheckPhase0_A	655319166	538	0	0
CheckPhase1_A	655319166	528	0	0
CheckPhase2_A	655319166	521	0	0
CheckPhase3_A	655319166	514	0	0
CheckTimeout0_A	655319166	1043	0	0
CheckTimeoutSt1_A	655319166	133294	0	0
CheckTimeoutSt2_A	655319166	946	0	0
CheckTimeoutStTrig_A	655319166	75	0	0
ErrorStAllEscAsserted_A	655319166	1262	0	0
ErrorStIsTerminal_A	655319166	1052	0	0
EscStateOut_A	655082827	655014024	0	0
u_state_regs_A	655319166	655160807	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	234	0	0
T10	31155	66	0	0
T11	0	22	0	0
T12	0	35	0	0
T22	373599	0	0	0
T29	0	61	0	0
T30	0	50	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	454	0	0
T1	740828	1	0	0
T2	111018	0	0	0
T3	26071	0	0	0
T4	121762	1	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	2	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T25	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	20	0	0
T13	197104	0	0	0
T14	458225	0	0	0
T18	58985	0	0	0
T19	0	2	0	0
T21	77243	1	0	0
T26	32685	0	0	0
T42	281135	0	0	0
T43	180264	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	4486	0	0	0
T60	14444	0	0	0
T61	483164	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	183	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	2	0	0
T8	225566	0	0	0
T9	827166	0	0	0
T15	29958	2	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T19	0	8	0	0
T20	0	2	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T45	0	1	0	0
T61	0	1	0	0
T65	0	1	0	0
T66	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655084264	282300684	0	0
T1	740828	3669	0	0
T2	111018	111008	0	0
T3	26071	20847	0	0
T4	121762	108530	0	0
T5	220795	2120	0	0
T6	299132	194444	0	0
T8	225566	225183	0	0
T15	29958	26559	0	0
T16	166097	165999	0	0
T17	81885	81824	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	538	0	0
T1	740828	1	0	0
T2	111018	0	0	0
T3	26071	0	0	0
T4	121762	1	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	2	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	528	0	0
T1	740828	1	0	0
T2	111018	0	0	0
T3	26071	0	0	0
T4	121762	1	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	2	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	521	0	0
T1	740828	1	0	0
T2	111018	0	0	0
T3	26071	0	0	0
T4	121762	1	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	2	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	514	0	0
T1	740828	1	0	0
T2	111018	0	0	0
T3	26071	0	0	0
T4	121762	1	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	2	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1043	0	0
T3	26071	1	0	0
T4	121762	9	0	0
T5	220795	0	0	0
T6	299132	2	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	0	1	0	0
T38	0	1	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T65	0	11	0	0
T66	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	133294	0	0
T3	26071	167	0	0
T4	121762	792	0	0
T5	220795	0	0	0
T6	299132	386	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	409	0	0
T20	0	745	0	0
T21	0	1	0	0
T23	0	141	0	0
T38	0	293	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T65	0	2229	0	0
T66	0	5464	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	946	0	0
T3	26071	1	0	0
T4	121762	9	0	0
T5	220795	0	0	0
T6	299132	1	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	2	0	0
T20	0	2	0	0
T23	0	1	0	0
T38	0	1	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T62	0	10	0	0
T65	0	9	0	0
T66	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	75	0	0
T20	647186	2	0	0
T44	65884	0	0	0
T49	0	2	0	0
T50	0	9	0	0
T65	0	2	0	0
T66	0	3	0	0
T67	33993	0	0	0
T69	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T80	323285	0	0	0
T81	353053	0	0	0
T82	14685	0	0	0
T83	105691	0	0	0
T84	23440	0	0	0
T85	19390	0	0	0
T86	121349	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1262	0	0
T10	31155	370	0	0
T11	0	180	0	0
T12	0	173	0	0
T22	373599	0	0	0
T29	0	341	0	0
T30	0	198	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1052	0	0
T10	31155	310	0	0
T11	0	150	0	0
T12	0	143	0	0
T22	373599	0	0	0
T29	0	281	0	0
T30	0	168	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655082827	655014024	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	655160807	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T16,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T8
1	0	1	Covered	T15,T16,T4
1	1	0	Covered	T4,T6,T39
1	1	1	Covered	T3,T6,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T18
0	1	Covered	T18,T62,T24
1	0	Covered	T23,T94,T77

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T94,T77

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Not Covered
1	1	Covered	T18,T62,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T4
1	Covered	T6,T40,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T8
1	Covered	T4,T5,T39

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T16,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T4
1	Covered	T6,T42,T65

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T15,T16,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T8,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T4,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T8,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T15,T16,T4
Phase1St	198	Covered	T15,T16,T4
Phase2St	215	Covered	T15,T16,T4
Phase3St	233	Covered	T15,T16,T4
TerminalSt	249	Covered	T15,T16,T4
TimeoutSt	159	Covered	T3,T6,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T15,T16,T4
IdleSt->TimeoutSt	159	Covered	T3,T6,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T19,T20,T95
Phase0St->Phase1St	198	Covered	T15,T16,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T72,T96
Phase1St->Phase2St	215	Covered	T15,T16,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T95,T97,T98
Phase2St->Phase3St	233	Covered	T15,T16,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T27,T72,T97
Phase3St->TerminalSt	249	Covered	T15,T16,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T8,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T6,T18
TimeoutSt->Phase0St	172	Covered	T18,T23,T62

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T23,T62
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T91
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T15,T16,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T15,T16,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T72,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T15,T16,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T15,T16,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T95,T97,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T15,T16,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T15,T16,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T27,T72,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T15,T16,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T15,T4,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T8,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T16,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655319166	243	0	0
CheckAccumTrig0_A	655319166	454	0	0
CheckAccumTrig1_A	655319166	16	0	0
CheckClr_A	655319166	191	0	0
CheckEn_A	655084264	302847664	0	0
CheckPhase0_A	655319166	512	0	0
CheckPhase1_A	655319166	503	0	0
CheckPhase2_A	655319166	495	0	0
CheckPhase3_A	655319166	485	0	0
CheckTimeout0_A	655319166	1450	0	0
CheckTimeoutSt1_A	655319166	150797	0	0
CheckTimeoutSt2_A	655319166	1379	0	0
CheckTimeoutStTrig_A	655319166	54	0	0
ErrorStAllEscAsserted_A	655319166	1176	0	0
ErrorStIsTerminal_A	655319166	966	0	0
EscStateOut_A	655082827	655014024	0	0
u_state_regs_A	655319166	655160807	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	243	0	0
T10	31155	59	0	0
T11	0	33	0	0
T12	0	37	0	0
T22	373599	0	0	0
T29	0	74	0	0
T30	0	40	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	454	0	0
T4	121762	4	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	2	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	16	0	0
T23	359305	2	0	0
T24	826266	0	0	0
T27	758842	0	0	0
T62	83883	0	0	0
T69	920666	0	0	0
T70	15736	0	0	0
T71	100663	0	0	0
T77	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	275634	0	0	0
T106	184483	0	0	0
T107	67746	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	191	0	0
T4	121762	1	0	0
T5	220795	0	0	0
T6	299132	3	0	0
T7	44339	0	0	0
T8	225566	1	0	0
T9	827166	0	0	0
T17	81885	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T23	0	3	0	0
T25	0	1	0	0
T38	0	1	0	0
T39	28801	1	0	0
T40	21425	0	0	0
T41	24589	0	0	0
T43	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655084264	302847664	0	0
T1	740828	740759	0	0
T2	111018	2042	0	0
T3	26071	18980	0	0
T4	121762	295954	0	0
T5	220795	2130	0	0
T6	299132	225821	0	0
T8	225566	8616	0	0
T15	29958	592	0	0
T16	166097	12906	0	0
T17	81885	81824	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	512	0	0
T4	121762	4	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	2	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	503	0	0
T4	121762	4	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	2	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	495	0	0
T4	121762	4	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	2	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	485	0	0
T4	121762	4	0	0
T5	220795	1	0	0
T6	299132	4	0	0
T8	225566	2	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	1	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1450	0	0
T3	26071	1	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	1	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	2	0	0
T19	0	4	0	0
T20	0	1	0	0
T23	0	4	0	0
T24	0	164	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T62	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	150797	0	0
T3	26071	205	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	203	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	249	0	0
T19	0	479	0	0
T20	0	137	0	0
T23	0	252	0	0
T24	0	9698	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T62	0	111	0	0
T65	0	260	0	0
T68	0	120	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1379	0	0
T3	26071	1	0	0
T4	121762	0	0	0
T5	220795	0	0	0
T6	299132	1	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T23	0	2	0	0
T24	0	163	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T65	0	1	0	0
T68	0	1	0	0
T69	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	54	0	0
T18	58985	1	0	0
T24	0	1	0	0
T26	32685	0	0	0
T42	281135	0	0	0
T43	180264	0	0	0
T59	4486	0	0	0
T60	14444	0	0	0
T61	483164	0	0	0
T62	0	1	0	0
T63	52542	0	0	0
T64	16641	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	5	0	0
T77	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	28797	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1176	0	0
T10	31155	357	0	0
T11	0	154	0	0
T12	0	174	0	0
T22	373599	0	0	0
T29	0	335	0	0
T30	0	156	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	966	0	0
T10	31155	297	0	0
T11	0	124	0	0
T12	0	144	0	0
T22	373599	0	0	0
T29	0	275	0	0
T30	0	126	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655082827	655014024	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	655160807	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T4
1	0	1	Covered	T1,T15,T16
1	1	0	Covered	T3,T15,T8
1	1	1	Covered	T3,T15,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T15,T4
0	1	Covered	T3,T4,T20
1	0	Covered	T25,T21,T74

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T15,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T21,T74

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T15,T4
1	0	Not Covered
1	1	Covered	T3,T4,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T16,T4,T5
1	Covered	T3,T4,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T4,T6,T40

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T16,T4
1	Covered	T4,T5,T6

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T16,T4,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T16,T4,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T16,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T16,T4
Phase1St	198	Covered	T3,T16,T4
Phase2St	215	Covered	T3,T16,T4
Phase3St	233	Covered	T3,T16,T4
TerminalSt	249	Covered	T3,T16,T4
TimeoutSt	159	Covered	T3,T15,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T16,T4,T5
IdleSt->TimeoutSt	159	Covered	T3,T15,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T19,T66
Phase0St->Phase1St	198	Covered	T3,T16,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T6,T63,T20
Phase1St->Phase2St	215	Covered	T3,T16,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T6,T112,T97
Phase2St->Phase3St	233	Covered	T3,T16,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T19,T75,T96
Phase3St->TerminalSt	249	Covered	T3,T16,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T4,T8
TimeoutSt->Phase0St	172	Covered	T3,T4,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T15,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T4,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T66,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T16,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T16,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T63,T20
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T16,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T16,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T112,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T16,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T16,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T75,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T16,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T16,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T16,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	655319166	273	0	0
CheckAccumTrig0_A	655319166	546	0	0
CheckAccumTrig1_A	655319166	25	0	0
CheckClr_A	655319166	259	0	0
CheckEn_A	655084264	278983591	0	0
CheckPhase0_A	655319166	616	0	0
CheckPhase1_A	655319166	603	0	0
CheckPhase2_A	655319166	589	0	0
CheckPhase3_A	655319166	585	0	0
CheckTimeout0_A	655319166	2132	0	0
CheckTimeoutSt1_A	655319166	180841	0	0
CheckTimeoutSt2_A	655319166	2045	0	0
CheckTimeoutStTrig_A	655319166	60	0	0
ErrorStAllEscAsserted_A	655319166	1265	0	0
ErrorStIsTerminal_A	655319166	1055	0	0
EscStateOut_A	655082827	655014024	0	0
u_state_regs_A	655319166	655160807	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	273	0	0
T10	31155	80	0	0
T11	0	53	0	0
T12	0	42	0	0
T22	373599	0	0	0
T29	0	74	0	0
T30	0	24	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	546	0	0
T4	121762	9	0	0
T5	220795	1	0	0
T6	299132	13	0	0
T8	225566	0	0	0
T9	827166	0	0	0
T14	0	1	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T25	0	3	0	0
T39	28801	1	0	0
T40	21425	1	0	0
T41	24589	0	0	0
T42	0	1	0	0
T43	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	25	0	0
T13	197104	0	0	0
T14	458225	0	0	0
T18	58985	0	0	0
T21	77243	1	0	0
T25	44619	1	0	0
T26	32685	0	0	0
T42	281135	0	0	0
T43	180264	0	0	0
T59	4486	0	0	0
T60	14444	0	0	0
T74	0	1	0	0
T95	0	1	0	0
T99	0	2	0	0
T104	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	259	0	0
T3	26071	1	0	0
T4	121762	5	0	0
T5	220795	0	0	0
T6	299132	10	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	0	4	0	0
T38	0	1	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T63	0	2	0	0
T66	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655084264	278983591	0	0
T1	740828	31073	0	0
T2	111018	106803	0	0
T3	26071	18980	0	0
T4	121762	135407	0	0
T5	220795	9751	0	0
T6	299132	192529	0	0
T8	225566	225152	0	0
T15	29958	27698	0	0
T16	166097	663	0	0
T17	81885	81824	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	616	0	0
T3	26071	1	0	0
T4	121762	10	0	0
T5	220795	1	0	0
T6	299132	11	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	0	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	603	0	0
T3	26071	1	0	0
T4	121762	10	0	0
T5	220795	1	0	0
T6	299132	10	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	0	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	589	0	0
T3	26071	1	0	0
T4	121762	10	0	0
T5	220795	1	0	0
T6	299132	7	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	0	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	585	0	0
T3	26071	1	0	0
T4	121762	10	0	0
T5	220795	1	0	0
T6	299132	7	0	0
T8	225566	0	0	0
T14	0	1	0	0
T15	29958	0	0	0
T16	166097	1	0	0
T17	81885	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T39	28801	1	0	0
T40	21425	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	2132	0	0
T3	26071	1	0	0
T4	121762	2	0	0
T5	220795	0	0	0
T6	299132	2	0	0
T8	225566	1	0	0
T15	29958	1	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T20	0	5	0	0
T21	0	1	0	0
T25	0	2	0	0
T39	28801	0	0	0
T40	21425	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	180841	0	0
T3	26071	82	0	0
T4	121762	79	0	0
T5	220795	0	0	0
T6	299132	290	0	0
T8	225566	263	0	0
T15	29958	57	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	313	0	0
T19	0	124	0	0
T20	0	1014	0	0
T21	0	1	0	0
T25	0	254	0	0
T39	28801	0	0	0
T40	21425	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	2045	0	0
T4	121762	1	0	0
T5	220795	0	0	0
T6	299132	2	0	0
T8	225566	1	0	0
T9	827166	0	0	0
T15	29958	1	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T20	0	4	0	0
T25	0	1	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T65	0	35	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	60	0	0
T3	26071	1	0	0
T4	121762	1	0	0
T5	220795	0	0	0
T6	299132	0	0	0
T8	225566	0	0	0
T15	29958	0	0	0
T16	166097	0	0	0
T17	81885	0	0	0
T20	0	1	0	0
T39	28801	0	0	0
T40	21425	0	0	0
T66	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0
T77	0	3	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1265	0	0
T10	31155	361	0	0
T11	0	177	0	0
T12	0	193	0	0
T22	373599	0	0	0
T29	0	371	0	0
T30	0	163	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	1055	0	0
T10	31155	301	0	0
T11	0	147	0	0
T12	0	163	0	0
T22	373599	0	0	0
T29	0	311	0	0
T30	0	133	0	0
T31	124430	0	0	0
T32	144736	0	0	0
T33	193164	0	0	0
T34	876152	0	0	0
T35	306682	0	0	0
T36	63880	0	0	0
T37	423372	0	0	0
T38	36490	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655082827	655014024	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655319166	655160807	0	0
T1	740828	740760	0	0
T2	111018	111008	0	0
T3	26071	25991	0	0
T4	121762	121676	0	0
T5	220795	220788	0	0
T6	299132	299099	0	0
T8	225566	225559	0	0
T15	29958	29866	0	0
T16	166097	166000	0	0
T17	81885	81825	0	0