Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63063075	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30610426

1

T1

181649

T2

97

T3

1752

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14104483	1			T1	76585		T2	19		T3	746
values[0x0]	38706569	1			T1	246118		T2	163		T3	2368
values[0x1]	40862449	1			T1	245276		T2	148		T3	2362

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53743491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39930010

1

T1

229235

T2

119

T3

2190

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	301796	1			T1	2254		T17	1822		T5	48
valid_sources[0x01]	507611	1			T1	2135		T17	2133		T5	56
valid_sources[0x02]	756558	1			T1	2246		T17	1913		T5	60
valid_sources[0x03]	331727	1			T1	2230		T17	1895		T5	78
valid_sources[0x04]	314561	1			T1	2203		T17	1718		T5	61
valid_sources[0x05]	563281	1			T1	2302		T17	1985		T5	58
valid_sources[0x06]	317855	1			T1	2361		T17	1981		T5	49
valid_sources[0x07]	301402	1			T1	2263		T17	1918		T5	56
valid_sources[0x08]	303213	1			T1	2263		T2	1		T17	2163
valid_sources[0x09]	323534	1			T1	2237		T17	1873		T5	55
valid_sources[0x0a]	312149	1			T1	2226		T2	7		T17	1877
valid_sources[0x0b]	307401	1			T1	2174		T17	1985		T5	54
valid_sources[0x0c]	295007	1			T1	2182		T17	1820		T5	44
valid_sources[0x0d]	299945	1			T1	2116		T17	2096		T5	54
valid_sources[0x0e]	296239	1			T1	2270		T17	1992		T5	52
valid_sources[0x0f]	308524	1			T1	2230		T17	1743		T5	58
valid_sources[0x10]	302715	1			T1	2224		T17	1892		T5	53
valid_sources[0x11]	326812	1			T1	2154		T2	13		T17	2017
valid_sources[0x12]	555417	1			T1	2255		T17	1904		T5	55
valid_sources[0x13]	298692	1			T1	2162		T17	2066		T5	48
valid_sources[0x14]	299293	1			T1	2300		T17	2016		T5	56
valid_sources[0x15]	298042	1			T1	2270		T17	1873		T5	69
valid_sources[0x16]	582031	1			T1	2204		T2	4		T17	1949
valid_sources[0x17]	319807	1			T1	2341		T17	1984		T5	63
valid_sources[0x18]	304510	1			T1	2248		T17	1958		T5	52
valid_sources[0x19]	295019	1			T1	2147		T17	1849		T5	50
valid_sources[0x1a]	787949	1			T1	2184		T2	4		T4	486384
valid_sources[0x1b]	300326	1			T1	2220		T2	5		T17	1961
valid_sources[0x1c]	295828	1			T1	2255		T17	1909		T5	61
valid_sources[0x1d]	680366	1			T1	2299		T17	1837		T5	46
valid_sources[0x1e]	302955	1			T1	2252		T2	2		T17	1746
valid_sources[0x1f]	294180	1			T1	2256		T17	2000		T5	64
valid_sources[0x20]	302317	1			T1	2241		T17	1875		T5	68
valid_sources[0x21]	643898	1			T1	2168		T17	1736		T5	57
valid_sources[0x22]	302237	1			T1	2338		T2	4		T17	1813
valid_sources[0x23]	294947	1			T1	2239		T17	1907		T5	48
valid_sources[0x24]	296807	1			T1	2290		T2	2		T17	1749
valid_sources[0x25]	296289	1			T1	2184		T17	1959		T5	47
valid_sources[0x26]	293775	1			T1	2226		T17	1904		T5	61
valid_sources[0x27]	763590	1			T1	2156		T17	1964		T5	54
valid_sources[0x28]	579681	1			T1	2293		T17	1891		T5	46
valid_sources[0x29]	296238	1			T1	2245		T2	6		T17	1858
valid_sources[0x2a]	309363	1			T1	2217		T2	1		T17	1841
valid_sources[0x2b]	317026	1			T1	2219		T17	1954		T5	57
valid_sources[0x2c]	293351	1			T1	2192		T17	2035		T5	56
valid_sources[0x2d]	293309	1			T1	2133		T17	1973		T5	75
valid_sources[0x2e]	790210	1			T1	2226		T2	1		T17	1927
valid_sources[0x2f]	659401	1			T1	2264		T17	1834		T5	57
valid_sources[0x30]	321823	1			T1	2199		T17	1861		T5	70
valid_sources[0x31]	310973	1			T1	2250		T17	1810		T5	56
valid_sources[0x32]	306118	1			T1	2264		T17	1888		T5	53
valid_sources[0x33]	309792	1			T1	2309		T17	1891		T5	63
valid_sources[0x34]	308912	1			T1	2153		T17	1825		T5	53
valid_sources[0x35]	297903	1			T1	2192		T17	1787		T5	70
valid_sources[0x36]	300767	1			T1	2203		T17	1809		T5	57
valid_sources[0x37]	316277	1			T1	2275		T17	1995		T5	49
valid_sources[0x38]	300146	1			T1	2261		T17	1887		T5	55
valid_sources[0x39]	915558	1			T1	2381		T17	2095		T5	75
valid_sources[0x3a]	309554	1			T1	2208		T17	1914		T5	57
valid_sources[0x3b]	295539	1			T1	2259		T17	1936		T5	51
valid_sources[0x3c]	296593	1			T1	2180		T17	1853		T5	46
valid_sources[0x3d]	308865	1			T1	2194		T2	7		T17	1843
valid_sources[0x3e]	293251	1			T1	2086		T17	2085		T5	50
valid_sources[0x3f]	300184	1			T1	2194		T17	2134		T5	42
valid_sources[0x40]	305228	1			T1	2268		T17	1861		T5	57
valid_sources[0x41]	319758	1			T1	2219		T17	2071		T5	67
valid_sources[0x42]	830759	1			T1	2160		T2	5		T17	2075
valid_sources[0x43]	300356	1			T1	2191		T17	1888		T5	43
valid_sources[0x44]	304332	1			T1	2228		T17	1995		T5	59
valid_sources[0x45]	309109	1			T1	2219		T17	1764		T5	49
valid_sources[0x46]	301476	1			T1	2179		T17	2013		T5	61
valid_sources[0x47]	606255	1			T1	2299		T17	1917		T5	60
valid_sources[0x48]	297224	1			T1	2210		T2	2		T17	2001
valid_sources[0x49]	295175	1			T1	2207		T17	1972		T5	47
valid_sources[0x4a]	307545	1			T1	2237		T2	2		T17	1872
valid_sources[0x4b]	295306	1			T1	2197		T17	1884		T5	49
valid_sources[0x4c]	773318	1			T1	2204		T17	2014		T5	55
valid_sources[0x4d]	303674	1			T1	2276		T17	2044		T5	65
valid_sources[0x4e]	297304	1			T1	2248		T17	1750		T5	51
valid_sources[0x4f]	299513	1			T1	2207		T17	1811		T5	50
valid_sources[0x50]	298226	1			T1	2327		T2	17		T17	1884
valid_sources[0x51]	303058	1			T1	2153		T17	1912		T5	57
valid_sources[0x52]	304597	1			T1	2097		T17	1851		T5	44
valid_sources[0x53]	305284	1			T1	2167		T17	1826		T5	42
valid_sources[0x54]	307662	1			T1	2186		T17	1883		T5	50
valid_sources[0x55]	318192	1			T1	2151		T3	5476		T17	1895
valid_sources[0x56]	292518	1			T1	2285		T17	2157		T5	78
valid_sources[0x57]	300184	1			T1	2237		T17	1985		T5	34
valid_sources[0x58]	296718	1			T1	2204		T17	1969		T5	51
valid_sources[0x59]	307216	1			T1	2284		T17	1935		T5	53
valid_sources[0x5a]	293591	1			T1	2277		T2	20		T17	1910
valid_sources[0x5b]	298827	1			T1	2215		T2	7		T17	2057
valid_sources[0x5c]	300622	1			T1	2173		T2	10		T17	1648
valid_sources[0x5d]	299949	1			T1	2256		T17	2052		T5	59
valid_sources[0x5e]	303890	1			T1	2082		T17	1891		T5	55
valid_sources[0x5f]	296804	1			T1	2219		T17	2070		T5	64
valid_sources[0x60]	300489	1			T1	2198		T17	1771		T5	51
valid_sources[0x61]	296105	1			T1	2188		T17	1986		T5	40
valid_sources[0x62]	297067	1			T1	2124		T2	10		T17	1788
valid_sources[0x63]	293503	1			T1	2284		T17	1873		T5	40
valid_sources[0x64]	637242	1			T1	2213		T17	1921		T5	50
valid_sources[0x65]	298264	1			T1	2206		T17	1995		T5	67
valid_sources[0x66]	306616	1			T1	2186		T17	1933		T5	68
valid_sources[0x67]	299129	1			T1	2223		T17	1944		T5	37
valid_sources[0x68]	294409	1			T1	2102		T2	2		T17	1952
valid_sources[0x69]	300815	1			T1	2188		T17	1934		T5	53
valid_sources[0x6a]	307352	1			T1	2306		T17	1973		T5	44
valid_sources[0x6b]	338001	1			T1	2214		T17	1974		T5	50
valid_sources[0x6c]	304425	1			T1	2254		T17	1948		T5	46
valid_sources[0x6d]	293613	1			T1	2139		T17	1937		T5	60
valid_sources[0x6e]	290517	1			T1	2167		T17	1996		T5	61
valid_sources[0x6f]	527654	1			T1	2198		T17	1835		T5	38
valid_sources[0x70]	313201	1			T1	2198		T17	1921		T5	44
valid_sources[0x71]	307356	1			T1	2219		T17	1911		T5	45
valid_sources[0x72]	770559	1			T1	2195		T17	1986		T5	56
valid_sources[0x73]	338225	1			T1	2261		T17	1827		T5	39
valid_sources[0x74]	307958	1			T1	2222		T17	1994		T5	53
valid_sources[0x75]	298325	1			T1	2192		T17	2023		T5	41
valid_sources[0x76]	296667	1			T1	2160		T17	1956		T5	58
valid_sources[0x77]	304989	1			T1	2264		T17	1994		T5	42
valid_sources[0x78]	294062	1			T1	2352		T17	2001		T5	48
valid_sources[0x79]	298334	1			T1	2216		T17	2058		T5	56
valid_sources[0x7a]	304917	1			T1	2148		T17	1901		T5	46
valid_sources[0x7b]	299923	1			T1	2199		T17	2090		T5	53
valid_sources[0x7c]	300396	1			T1	2096		T17	1939		T5	55
valid_sources[0x7d]	303383	1			T1	2195		T2	2		T17	1871
valid_sources[0x7e]	337821	1			T1	2211		T17	1708		T5	55
valid_sources[0x7f]	309665	1			T1	2191		T17	2074		T5	58
valid_sources[0x80]	310092	1			T1	2255		T17	1842		T5	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7028824

1

T1

38264

T2

11

T3

377

values[0x0]

all_enables

biggest_size

14866354

1

T1

91982

T2

59

T3

859

values[0x1]

all_enables

biggest_size

8715248

1

T1

51403

T2

27

T3

516