Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T39,T193
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15160	0	0
DisabledNoTrigBkwd_A	2147483647	745157	0	0
DisabledNoTrigFwd_A	2147483647	1493469382	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15160	0	0
T2	3668	401	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T9	742480	0	0	0
T17	598302	0	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T30	0	1371	0	0
T39	0	579	0	0
T82	206770	0	0	0
T83	494495	0	0	0
T90	929384	0	0	0
T94	589397	0	0	0
T99	828264	0	0	0
T193	0	435	0	0
T194	0	1324	0	0
T195	0	1070	0	0
T196	4066	509	0	0
T197	6046	662	0	0
T198	0	863	0	0
T199	0	633	0	0
T200	0	1204	0	0
T201	0	466	0	0
T202	0	364	0	0
T203	0	284	0	0
T204	0	410	0	0
T205	0	862	0	0
T206	0	826	0	0
T207	0	1991	0	0
T208	0	324	0	0
T209	0	582	0	0
T210	530832	0	0	0
T211	185546	0	0	0
T212	117990	0	0	0
T213	19075	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	745157	0	0
T1	593684	6219	0	0
T2	14672	4	0	0
T3	84240	14	0	0
T4	2232360	2556	0	0
T5	514472	11	0	0
T8	0	460	0	0
T14	0	3479	0	0
T15	0	5874	0	0
T17	2393208	4150	0	0
T18	3580736	524	0	0
T19	86216	0	0	0
T20	302408	58	0	0
T21	87988	13	0	0
T37	0	1	0	0
T38	0	17	0	0
T39	0	5	0	0
T40	0	15	0	0
T41	0	95	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1493469382	0	0
T1	593684	827690	0	0
T2	14672	12420	0	0
T3	84240	44224	0	0
T4	2232360	1675080	0	0
T5	514472	399859	0	0
T17	2393208	1299161	0	0
T18	3580736	2390354	0	0
T19	86216	10143	0	0
T20	302408	197711	0	0
T21	87988	67391	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T30,T198
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674959995	3180	0	0
DisabledNoTrigBkwd_A	674959995	240909	0	0
DisabledNoTrigFwd_A	674959995	326764215	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	3180	0	0
T30	0	1371	0	0
T82	206770	0	0	0
T83	494495	0	0	0
T90	464692	0	0	0
T94	589397	0	0	0
T99	828264	0	0	0
T197	3023	662	0	0
T198	0	863	0	0
T203	0	284	0	0
T210	265416	0	0	0
T211	92773	0	0	0
T212	117990	0	0	0
T213	19075	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	240909	0	0
T1	148421	263	0	0
T2	3668	0	0	0
T3	21060	14	0	0
T4	558090	1	0	0
T5	128618	9	0	0
T14	0	3218	0	0
T15	0	1623	0	0
T17	598302	642	0	0
T18	895184	311	0	0
T19	21554	0	0	0
T20	75602	10	0	0
T21	21997	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	326764215	0	0
T1	148421	116269	0	0
T2	3668	3073	0	0
T3	21060	1626	0	0
T4	558090	556380	0	0
T5	128618	34170	0	0
T17	598302	153131	0	0
T18	895184	305482	0	0
T19	21554	1895	0	0
T20	75602	54838	0	0
T21	21997	1655	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T2,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T194,T206
1	1	Covered	T1,T2,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674959995	4866	0	0
DisabledNoTrigBkwd_A	674959995	146532	0	0
DisabledNoTrigFwd_A	674959995	400308464	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	4866	0	0
T2	3668	401	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T9	742480	0	0	0
T17	598302	0	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T194	0	1324	0	0
T206	0	826	0	0
T207	0	1991	0	0
T208	0	324	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	146532	0	0
T1	148421	2369	0	0
T2	3668	4	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	2	0	0
T14	0	15	0	0
T15	0	815	0	0
T17	598302	2559	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	5	0	0
T21	21997	0	0	0
T38	0	6	0	0
T40	0	11	0	0
T41	0	44	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	400308464	0	0
T1	148421	134637	0	0
T2	3668	3093	0	0
T3	21060	600	0	0
T4	558090	558081	0	0
T5	128618	116934	0	0
T17	598302	93852	0	0
T18	895184	852456	0	0
T19	21554	822	0	0
T20	75602	65185	0	0
T21	21997	21912	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T4,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T201,T202
1	1	Covered	T1,T4,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674959995	1921	0	0
DisabledNoTrigBkwd_A	674959995	181115	0	0
DisabledNoTrigFwd_A	674959995	400064677	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1921	0	0
T48	45439	0	0	0
T81	44952	0	0	0
T90	464692	0	0	0
T196	4066	509	0	0
T197	3023	0	0	0
T201	0	466	0	0
T202	0	364	0	0
T209	0	582	0	0
T210	265416	0	0	0
T211	92773	0	0	0
T214	12154	0	0	0
T215	641970	0	0	0
T216	92024	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	181115	0	0
T1	148421	1857	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T8	0	2	0	0
T14	0	229	0	0
T15	0	1792	0	0
T17	598302	200	0	0
T18	895184	183	0	0
T19	21554	0	0	0
T20	75602	2	0	0
T21	21997	0	0	0
T37	0	1	0	0
T38	0	11	0	0
T41	0	51	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	400064677	0	0
T1	148421	191523	0	0
T2	3668	3121	0	0
T3	21060	20999	0	0
T4	558090	557511	0	0
T5	128618	120144	0	0
T17	598302	527559	0	0
T18	895184	709841	0	0
T19	21554	5519	0	0
T20	75602	70292	0	0
T21	21997	21912	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T4,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T193,T195
1	1	Covered	T1,T4,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	674959995	5193	0	0
DisabledNoTrigBkwd_A	674959995	176601	0	0
DisabledNoTrigFwd_A	674959995	366332026	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	5193	0	0
T8	594160	0	0	0
T10	117073	0	0	0
T16	108913	0	0	0
T39	1321	579	0	0
T40	49352	0	0	0
T41	170864	0	0	0
T42	74022	0	0	0
T66	55427	0	0	0
T67	915704	0	0	0
T74	19537	0	0	0
T193	0	435	0	0
T195	0	1070	0	0
T199	0	633	0	0
T200	0	1204	0	0
T204	0	410	0	0
T205	0	862	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	176601	0	0
T1	148421	1730	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	2555	0	0
T5	128618	0	0	0
T8	0	458	0	0
T14	0	17	0	0
T15	0	1644	0	0
T17	598302	749	0	0
T18	895184	30	0	0
T19	21554	0	0	0
T20	75602	41	0	0
T21	21997	0	0	0
T39	0	5	0	0
T40	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	366332026	0	0
T1	148421	385261	0	0
T2	3668	3133	0	0
T3	21060	20999	0	0
T4	558090	3108	0	0
T5	128618	128611	0	0
T17	598302	524619	0	0
T18	895184	522575	0	0
T19	21554	1907	0	0
T20	75602	7396	0	0
T21	21997	21912	0	0