Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T22
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T17
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T17,T18
1	0	Covered	T3,T4,T18

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T18

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T23
1	1	Covered	T1,T17,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T3,T4
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T1,T17,T14
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T14,T15
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T1,T18,T15
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T4,T24,T25
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T3,T4
TimeoutSt->Phase0St	172	Covered	T1,T3,T4

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T14,T15
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T14,T15
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T18,T15
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T24,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	887	0	0
CheckAccumTrig0_A	2147483647	2360	0	0
CheckAccumTrig1_A	2147483647	108	0	0
CheckClr_A	2147483647	1083	0	0
CheckEn_A	2147483647	1138662048	0	0
CheckPhase0_A	2147483647	2696	0	0
CheckPhase1_A	2147483647	2653	0	0
CheckPhase2_A	2147483647	2598	0	0
CheckPhase3_A	2147483647	2568	0	0
CheckTimeout0_A	2147483647	4371	0	0
CheckTimeoutSt1_A	2147483647	464647	0	0
CheckTimeoutSt2_A	2147483647	3988	0	0
CheckTimeoutStTrig_A	2147483647	271	0	0
ErrorStAllEscAsserted_A	2147483647	4234	0	0
ErrorStIsTerminal_A	2147483647	3514	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	887	0	0
T11	94736	156	0	0
T12	0	156	0	0
T13	0	309	0	0
T26	0	124	0	0
T27	0	142	0	0
T28	1448604	0	0	0
T29	179700	0	0	0
T30	20356	0	0	0
T31	2110908	0	0	0
T32	1656504	0	0	0
T33	146956	0	0	0
T34	438060	0	0	0
T35	2129892	0	0	0
T36	358336	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2360	0	0
T1	593684	21	0	0
T2	14672	1	0	0
T3	84240	0	0	0
T4	2232360	4	0	0
T5	514472	2	0	0
T8	0	2	0	0
T10	0	2	0	0
T14	0	17	0	0
T15	0	27	0	0
T17	2393208	9	0	0
T18	3580736	9	0	0
T19	86216	0	0	0
T20	302408	4	0	0
T21	87988	1	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	108	0	0
T3	21060	4	0	0
T4	558090	1	0	0
T5	128618	0	0	0
T6	37396	0	0	0
T9	1484960	0	0	0
T14	0	1	0	0
T17	598302	0	0	0
T18	1790368	2	0	0
T19	43108	0	0	0
T20	151204	0	0	0
T21	43994	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	77320	1	0	0
T46	137445	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	120886	0	0	0
T58	53080	0	0	0
T59	750156	0	0	0
T60	710555	0	0	0
T61	241207	0	0	0
T62	18128	0	0	0
T63	60821	0	0	0
T64	39985	0	0	0
T65	12611	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1083	0	0
T1	445263	10	0	0
T2	11004	0	0	0
T3	84240	4	0	0
T4	2232360	4	0	0
T5	514472	0	0	0
T9	742480	0	0	0
T10	0	1	0	0
T14	0	5	0	0
T15	0	11	0	0
T17	2393208	6	0	0
T18	3580736	8	0	0
T19	86216	0	0	0
T20	302408	1	0	0
T21	87988	0	0	0
T24	0	2	0	0
T38	0	3	0	0
T40	0	2	0	0
T42	0	5	0	0
T43	0	15	0	0
T57	60443	0	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	3	0	0
T71	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138662048	0	0
T1	593684	809883	0	0
T2	14672	12420	0	0
T3	84240	44222	0	0
T4	2232360	1675079	0	0
T5	514472	285003	0	0
T17	2393208	1299159	0	0
T18	3580736	1979002	0	0
T19	86216	10143	0	0
T20	302408	106343	0	0
T21	87988	67388	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2696	0	0
T1	593684	22	0	0
T2	14672	1	0	0
T3	84240	4	0	0
T4	2232360	5	0	0
T5	514472	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	17	0	0
T15	0	23	0	0
T17	2393208	13	0	0
T18	3580736	17	0	0
T19	86216	0	0	0
T20	302408	4	0	0
T21	87988	1	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T73	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2653	0	0
T1	593684	22	0	0
T2	14672	1	0	0
T3	84240	4	0	0
T4	2232360	4	0	0
T5	514472	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	15	0	0
T15	0	20	0	0
T17	2393208	13	0	0
T18	3580736	15	0	0
T19	86216	0	0	0
T20	302408	4	0	0
T21	87988	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T73	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2598	0	0
T1	593684	21	0	0
T2	14672	1	0	0
T3	84240	4	0	0
T4	2232360	3	0	0
T5	514472	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	15	0	0
T15	0	18	0	0
T17	2393208	13	0	0
T18	3580736	12	0	0
T19	86216	0	0	0
T20	302408	4	0	0
T21	87988	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T73	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2568	0	0
T1	593684	21	0	0
T2	14672	1	0	0
T3	84240	4	0	0
T4	2232360	2	0	0
T5	514472	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T14	0	15	0	0
T15	0	18	0	0
T17	2393208	13	0	0
T18	3580736	12	0	0
T19	86216	0	0	0
T20	302408	4	0	0
T21	87988	1	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T73	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4371	0	0
T1	593684	58	0	0
T2	14672	0	0	0
T3	84240	6	0	0
T4	2232360	3	0	0
T5	514472	0	0	0
T7	0	1	0	0
T14	0	24	0	0
T15	0	66	0	0
T16	0	2	0	0
T17	2393208	11	0	0
T18	3580736	30	0	0
T19	86216	19	0	0
T20	302408	0	0	0
T21	87988	0	0	0
T25	0	12	0	0
T37	0	1	0	0
T40	0	1	0	0
T43	0	8	0	0
T57	0	14	0	0
T66	0	5	0	0
T68	0	1	0	0
T70	0	6	0	0
T73	0	588	0	0
T74	0	1	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	464647	0	0
T1	593684	1906	0	0
T2	14672	0	0	0
T3	84240	283	0	0
T4	2232360	181	0	0
T5	514472	0	0	0
T7	0	70	0	0
T14	0	2712	0	0
T15	0	11614	0	0
T16	0	89	0	0
T17	2393208	1909	0	0
T18	3580736	4270	0	0
T19	86216	1852	0	0
T20	302408	0	0	0
T21	87988	0	0	0
T25	0	3578	0	0
T37	0	2	0	0
T40	0	149	0	0
T43	0	1248	0	0
T57	0	2634	0	0
T66	0	864	0	0
T68	0	904	0	0
T70	0	4370	0	0
T73	0	75893	0	0
T74	0	173	0	0
T75	0	76	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3988	0	0
T1	593684	56	0	0
T2	14672	0	0	0
T3	84240	2	0	0
T4	2232360	2	0	0
T5	514472	0	0	0
T14	0	23	0	0
T15	0	66	0	0
T16	0	2	0	0
T17	2393208	6	0	0
T18	3580736	22	0	0
T19	86216	19	0	0
T20	302408	0	0	0
T21	87988	0	0	0
T25	0	11	0	0
T40	0	1	0	0
T43	0	6	0	0
T57	0	14	0	0
T66	0	5	0	0
T68	0	1	0	0
T70	0	4	0	0
T73	0	586	0	0
T74	0	1	0	0
T75	0	4	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	271	0	0
T1	148421	1	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	257236	0	0	0
T6	112188	0	0	0
T7	134172	1	0	0
T9	2227440	0	0	0
T14	272404	0	0	0
T17	1196604	5	0	0
T18	3580736	2	0	0
T19	86216	0	0	0
T20	302408	0	0	0
T21	87988	0	0	0
T25	0	4	0	0
T43	0	6	0	0
T47	0	2	0	0
T57	181329	0	0	0
T66	0	1	0	0
T68	0	1	0	0
T70	0	5	0	0
T72	0	1	0	0
T73	793434	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4234	0	0
T11	94736	713	0	0
T12	0	716	0	0
T13	0	1409	0	0
T26	0	676	0	0
T27	0	720	0	0
T28	1448604	0	0	0
T29	179700	0	0	0
T30	20356	0	0	0
T31	2110908	0	0	0
T32	1656504	0	0	0
T33	146956	0	0	0
T34	438060	0	0	0
T35	2129892	0	0	0
T36	358336	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3514	0	0
T11	94736	593	0	0
T12	0	596	0	0
T13	0	1169	0	0
T26	0	556	0	0
T27	0	600	0	0
T28	1448604	0	0	0
T29	179700	0	0	0
T30	20356	0	0	0
T31	2110908	0	0	0
T32	1656504	0	0	0
T33	146956	0	0	0
T34	438060	0	0	0
T35	2129892	0	0	0
T36	358336	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	593684	593464	0	0
T2	14672	14332	0	0
T3	84240	83996	0	0
T4	2232360	2232324	0	0
T5	514472	514444	0	0
T17	2393208	2393172	0	0
T18	3580736	3578648	0	0
T19	86216	85944	0	0
T20	302408	302008	0	0
T21	87988	87648	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	593684	593464	0	0
T2	14672	14332	0	0
T3	84240	83996	0	0
T4	2232360	2232324	0	0
T5	514472	514444	0	0
T17	2393208	2393172	0	0
T18	3580736	3578648	0	0
T19	86216	85944	0	0
T20	302408	302008	0	0
T21	87988	87648	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T17,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T17,T18
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T18,T43,T25
1	0	Covered	T3,T4,T18

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T18

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T18,T43,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T17,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T18,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T3,T5,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T18,T14,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T17,T5
IdleSt->TimeoutSt	159	Covered	T1,T3,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T14,T25,T58
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T14,T42
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T43,T44,T64
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T47,T87
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T4
TimeoutSt->Phase0St	172	Covered	T3,T4,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T58,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T14,T42
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T43,T44,T64
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T47,T87
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T18,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674959995	261	0	0
CheckAccumTrig0_A	674959995	897	0	0
CheckAccumTrig1_A	674959995	46	0	0
CheckClr_A	674959995	428	0	0
CheckEn_A	674845748	229059465	0	0
CheckPhase0_A	674959995	985	0	0
CheckPhase1_A	674959995	973	0	0
CheckPhase2_A	674959995	951	0	0
CheckPhase3_A	674959995	934	0	0
CheckTimeout0_A	674959995	1167	0	0
CheckTimeoutSt1_A	674959995	114547	0	0
CheckTimeoutSt2_A	674959995	1056	0	0
CheckTimeoutStTrig_A	674959995	62	0	0
ErrorStAllEscAsserted_A	674959995	1079	0	0
ErrorStIsTerminal_A	674959995	899	0	0
EscStateOut_A	674844385	674772097	0	0
u_state_regs_A	674959995	674811777	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	261	0	0
T11	23684	45	0	0
T12	0	42	0	0
T13	0	89	0	0
T26	0	38	0	0
T27	0	47	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	897	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T10	0	2	0	0
T14	0	8	0	0
T15	0	4	0	0
T17	598302	1	0	0
T18	895184	6	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	46	0	0
T3	21060	4	0	0
T4	558090	1	0	0
T5	128618	0	0	0
T9	742480	0	0	0
T14	0	1	0	0
T17	598302	0	0	0
T18	895184	1	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	1	0	0
T37	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T57	60443	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	428	0	0
T3	21060	4	0	0
T4	558090	1	0	0
T5	128618	0	0	0
T9	742480	0	0	0
T10	0	1	0	0
T14	0	3	0	0
T17	598302	0	0	0
T18	895184	3	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T40	0	1	0	0
T42	0	5	0	0
T43	0	6	0	0
T57	60443	0	0	0
T68	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674845748	229059465	0	0
T1	148421	115678	0	0
T2	3668	3073	0	0
T3	21060	1626	0	0
T4	558090	556380	0	0
T5	128618	34170	0	0
T17	598302	153130	0	0
T18	895184	175890	0	0
T19	21554	1895	0	0
T20	75602	7346	0	0
T21	21997	1655	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	985	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	4	0	0
T4	558090	1	0	0
T5	128618	1	0	0
T14	0	8	0	0
T15	0	4	0	0
T17	598302	1	0	0
T18	895184	8	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	973	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	4	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	7	0	0
T15	0	4	0	0
T17	598302	1	0	0
T18	895184	8	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	1	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	951	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	4	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	7	0	0
T15	0	4	0	0
T17	598302	1	0	0
T18	895184	8	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	1	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	934	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	4	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	7	0	0
T15	0	4	0	0
T17	598302	1	0	0
T18	895184	8	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	1	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1167	0	0
T1	148421	2	0	0
T2	3668	0	0	0
T3	21060	6	0	0
T4	558090	3	0	0
T5	128618	0	0	0
T14	0	2	0	0
T15	0	6	0	0
T17	598302	0	0	0
T18	895184	2	0	0
T19	21554	2	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T57	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	114547	0	0
T1	148421	109	0	0
T2	3668	0	0	0
T3	21060	283	0	0
T4	558090	181	0	0
T5	128618	0	0	0
T14	0	195	0	0
T15	0	811	0	0
T17	598302	0	0	0
T18	895184	318	0	0
T19	21554	223	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T37	0	2	0	0
T40	0	149	0	0
T57	0	1316	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1056	0	0
T1	148421	2	0	0
T2	3668	0	0	0
T3	21060	2	0	0
T4	558090	2	0	0
T5	128618	0	0	0
T14	0	1	0	0
T15	0	6	0	0
T17	598302	0	0	0
T18	895184	0	0	0
T19	21554	2	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T40	0	1	0	0
T57	0	7	0	0
T66	0	1	0	0
T75	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	62	0	0
T6	37396	0	0	0
T7	67086	0	0	0
T9	742480	0	0	0
T14	136202	0	0	0
T18	895184	1	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	1	0	0
T43	0	2	0	0
T47	0	2	0	0
T57	60443	0	0	0
T72	0	1	0	0
T73	264478	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1079	0	0
T11	23684	196	0	0
T12	0	178	0	0
T13	0	360	0	0
T26	0	165	0	0
T27	0	180	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	899	0	0
T11	23684	166	0	0
T12	0	148	0	0
T13	0	300	0	0
T26	0	135	0	0
T27	0	150	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674844385	674772097	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	674811777	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T17
1	0	1	Covered	T1,T17,T18
1	1	0	Covered	T1,T17,T7
1	1	1	Covered	T1,T18,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T19
0	1	Covered	T18,T73,T68
1	0	Covered	T1,T43,T78

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T18,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T43,T78

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Not Covered
1	1	Covered	T18,T73,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T20,T73

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T20
1	Covered	T4,T17,T73

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T18,T15,T40

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T1,T15,T8

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T4,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T17
Phase1St	198	Covered	T1,T4,T17
Phase2St	215	Covered	T1,T4,T17
Phase3St	233	Covered	T1,T4,T17
TerminalSt	249	Covered	T1,T4,T17
TimeoutSt	159	Covered	T1,T18,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T4,T17
IdleSt->TimeoutSt	159	Covered	T1,T18,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T88,T89
Phase0St->Phase1St	198	Covered	T1,T4,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T18,T78,T83
Phase1St->Phase2St	215	Covered	T1,T4,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T4,T18,T90
Phase2St->Phase3St	233	Covered	T1,T4,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T83,T91
Phase3St->TerminalSt	249	Covered	T1,T4,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T18,T19
TimeoutSt->Phase0St	172	Covered	T1,T18,T73

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T73
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T88,T89,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T18,T78,T83
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T18,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T83,T91
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674959995	213	0	0
CheckAccumTrig0_A	674959995	530	0	0
CheckAccumTrig1_A	674959995	29	0	0
CheckClr_A	674959995	266	0	0
CheckEn_A	674845748	282614842	0	0
CheckPhase0_A	674959995	622	0	0
CheckPhase1_A	674959995	609	0	0
CheckPhase2_A	674959995	594	0	0
CheckPhase3_A	674959995	590	0	0
CheckTimeout0_A	674959995	1341	0	0
CheckTimeoutSt1_A	674959995	145322	0	0
CheckTimeoutSt2_A	674959995	1242	0	0
CheckTimeoutStTrig_A	674959995	69	0	0
ErrorStAllEscAsserted_A	674959995	1013	0	0
ErrorStIsTerminal_A	674959995	833	0	0
EscStateOut_A	674844385	674772097	0	0
u_state_regs_A	674959995	674811777	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	213	0	0
T11	23684	43	0	0
T12	0	32	0	0
T13	0	78	0	0
T26	0	29	0	0
T27	0	31	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	530	0	0
T1	148421	2	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	4	0	0
T5	128618	0	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	4	0	0
T17	598302	1	0	0
T18	895184	2	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	29	0	0
T1	148421	1	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T17	598302	0	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T62	0	1	0	0
T78	0	1	0	0
T85	0	1	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	266	0	0
T1	148421	1	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	3	0	0
T5	128618	0	0	0
T17	598302	0	0	0
T18	895184	4	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T24	0	2	0	0
T25	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T78	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674845748	282614842	0	0
T1	148421	372077	0	0
T2	3668	3133	0	0
T3	21060	20998	0	0
T4	558090	3108	0	0
T5	128618	128611	0	0
T17	598302	524619	0	0
T18	895184	274309	0	0
T19	21554	1907	0	0
T20	75602	7396	0	0
T21	21997	21911	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	622	0	0
T1	148421	3	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	4	0	0
T5	128618	0	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	3	0	0
T17	598302	1	0	0
T18	895184	6	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T39	0	1	0	0
T73	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	609	0	0
T1	148421	3	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	4	0	0
T5	128618	0	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	3	0	0
T17	598302	1	0	0
T18	895184	4	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T39	0	1	0	0
T73	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	594	0	0
T1	148421	3	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	3	0	0
T5	128618	0	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	3	0	0
T17	598302	1	0	0
T18	895184	2	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T39	0	1	0	0
T73	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	590	0	0
T1	148421	3	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	2	0	0
T5	128618	0	0	0
T8	0	1	0	0
T14	0	2	0	0
T15	0	3	0	0
T17	598302	1	0	0
T18	895184	2	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T39	0	1	0	0
T73	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1341	0	0
T1	148421	17	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	4	0	0
T15	0	60	0	0
T17	598302	0	0	0
T18	895184	25	0	0
T19	21554	7	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T57	0	7	0	0
T66	0	1	0	0
T68	0	1	0	0
T73	0	291	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	145322	0	0
T1	148421	505	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	415	0	0
T15	0	10803	0	0
T17	598302	0	0	0
T18	895184	3770	0	0
T19	21554	649	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T57	0	1318	0	0
T66	0	179	0	0
T68	0	904	0	0
T73	0	36805	0	0
T76	0	99	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1242	0	0
T1	148421	16	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	4	0	0
T15	0	60	0	0
T17	598302	0	0	0
T18	895184	21	0	0
T19	21554	7	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T57	0	7	0	0
T66	0	1	0	0
T70	0	1	0	0
T73	0	289	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	69	0	0
T6	37396	0	0	0
T7	67086	0	0	0
T9	742480	0	0	0
T14	136202	0	0	0
T18	895184	4	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T57	60443	0	0	0
T68	0	1	0	0
T70	0	1	0	0
T73	264478	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T97	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1013	0	0
T11	23684	147	0	0
T12	0	185	0	0
T13	0	323	0	0
T26	0	166	0	0
T27	0	192	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	833	0	0
T11	23684	117	0	0
T12	0	155	0	0
T13	0	263	0	0
T26	0	136	0	0
T27	0	162	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674844385	674772097	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	674811777	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T1,T2,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T18
1	0	1	Covered	T1,T2,T17
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T17,T70,T43
1	0	Covered	T45,T46,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T45,T46,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Not Covered
1	1	Covered	T17,T70,T43

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T5
1	Covered	T1,T2,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T17,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T5,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T17,T14,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T17
Phase1St	198	Covered	T1,T2,T17
Phase2St	215	Covered	T1,T2,T17
Phase3St	233	Covered	T1,T2,T17
TerminalSt	249	Covered	T1,T2,T17
TimeoutSt	159	Covered	T1,T17,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T17
IdleSt->TimeoutSt	159	Covered	T1,T17,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T17,T15
Phase0St->Phase1St	198	Covered	T1,T2,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T14,T15,T43
Phase1St->Phase2St	215	Covered	T1,T2,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T1,T15,T98
Phase2St->Phase3St	233	Covered	T1,T2,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T99,T49,T100
Phase3St->TerminalSt	249	Covered	T1,T2,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T17,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T18
TimeoutSt->Phase0St	172	Covered	T17,T70,T43

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T70,T43
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T15,T43
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T17,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T15,T43
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T17,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T15,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T17,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T99,T49,T100
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T17,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T17,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674959995	213	0	0
CheckAccumTrig0_A	674959995	469	0	0
CheckAccumTrig1_A	674959995	15	0	0
CheckClr_A	674959995	190	0	0
CheckEn_A	674845748	315349995	0	0
CheckPhase0_A	674959995	524	0	0
CheckPhase1_A	674959995	512	0	0
CheckPhase2_A	674959995	504	0	0
CheckPhase3_A	674959995	500	0	0
CheckTimeout0_A	674959995	1243	0	0
CheckTimeoutSt1_A	674959995	124806	0	0
CheckTimeoutSt2_A	674959995	1176	0	0
CheckTimeoutStTrig_A	674959995	52	0	0
ErrorStAllEscAsserted_A	674959995	1124	0	0
ErrorStIsTerminal_A	674959995	944	0	0
EscStateOut_A	674844385	674772097	0	0
u_state_regs_A	674959995	674811777	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	213	0	0
T11	23684	44	0	0
T12	0	33	0	0
T13	0	71	0	0
T26	0	32	0	0
T27	0	33	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	469	0	0
T1	148421	12	0	0
T2	3668	1	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	3	0	0
T15	0	14	0	0
T17	598302	5	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	15	0	0
T45	77320	1	0	0
T46	137445	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	53080	0	0	0
T59	750156	0	0	0
T60	710555	0	0	0
T61	241207	0	0	0
T62	18128	0	0	0
T63	60821	0	0	0
T64	39985	0	0	0
T65	12611	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	190	0	0
T1	148421	8	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	1	0	0
T15	0	10	0	0
T17	598302	2	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T38	0	2	0	0
T43	0	7	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674845748	315349995	0	0
T1	148421	130607	0	0
T2	3668	3093	0	0
T3	21060	600	0	0
T4	558090	558080	0	0
T5	128618	2079	0	0
T17	598302	93851	0	0
T18	895184	852449	0	0
T19	21554	822	0	0
T20	75602	21310	0	0
T21	21997	21911	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	524	0	0
T1	148421	11	0	0
T2	3668	1	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	3	0	0
T15	0	12	0	0
T17	598302	6	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	512	0	0
T1	148421	11	0	0
T2	3668	1	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	2	0	0
T15	0	9	0	0
T17	598302	6	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	504	0	0
T1	148421	10	0	0
T2	3668	1	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	2	0	0
T15	0	7	0	0
T17	598302	6	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	500	0	0
T1	148421	10	0	0
T2	3668	1	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	1	0	0
T14	0	2	0	0
T15	0	7	0	0
T17	598302	6	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1243	0	0
T1	148421	22	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	8	0	0
T17	598302	5	0	0
T18	895184	1	0	0
T19	21554	5	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	12	0	0
T43	0	8	0	0
T70	0	6	0	0
T73	0	296	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	124806	0	0
T1	148421	740	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	787	0	0
T17	598302	1042	0	0
T18	895184	35	0	0
T19	21554	511	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	3578	0	0
T43	0	1248	0	0
T70	0	4370	0	0
T73	0	38903	0	0
T75	0	76	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1176	0	0
T1	148421	22	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	8	0	0
T17	598302	3	0	0
T18	895184	1	0	0
T19	21554	5	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	11	0	0
T43	0	6	0	0
T70	0	3	0	0
T73	0	296	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	52	0	0
T5	128618	0	0	0
T6	37396	0	0	0
T9	742480	0	0	0
T17	598302	2	0	0
T18	895184	0	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	1	0	0
T43	0	2	0	0
T57	60443	0	0	0
T70	0	3	0	0
T73	264478	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T86	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1124	0	0
T11	23684	207	0	0
T12	0	176	0	0
T13	0	380	0	0
T26	0	188	0	0
T27	0	173	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	944	0	0
T11	23684	177	0	0
T12	0	146	0	0
T13	0	320	0	0
T26	0	158	0	0
T27	0	143	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674844385	674772097	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	674811777	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T17,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T17
1	0	1	Covered	T1,T18,T14
1	1	0	Covered	T1,T4,T17
1	1	1	Covered	T1,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T1,T17,T18
1	0	Covered	T18,T25,T47

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T25,T47

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T23
1	1	Covered	T1,T17,T18

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T18,T20,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T15,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T17,T18,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T17,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T18,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T17,T18
Phase1St	198	Covered	T1,T17,T18
Phase2St	215	Covered	T1,T17,T18
Phase3St	233	Covered	T1,T17,T18
TerminalSt	249	Covered	T1,T17,T18
TimeoutSt	159	Covered	T1,T17,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T17,T18
IdleSt->TimeoutSt	159	Covered	T1,T17,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T97,T98
Phase0St->Phase1St	198	Covered	T1,T17,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T101,T49,T98
Phase1St->Phase2St	215	Covered	T1,T17,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T18,T102,T103
Phase2St->Phase3St	233	Covered	T1,T17,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T104,T98
Phase3St->TerminalSt	249	Covered	T1,T17,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T17,T18
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T19
TimeoutSt->Phase0St	172	Covered	T1,T17,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T98,T105,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T17,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T17,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T101,T98,T107
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T17,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T17,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T18,T102,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T17,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T104,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T17,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T17,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T17,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	674959995	200	0	0
CheckAccumTrig0_A	674959995	464	0	0
CheckAccumTrig1_A	674959995	18	0	0
CheckClr_A	674959995	199	0	0
CheckEn_A	674845748	311637746	0	0
CheckPhase0_A	674959995	565	0	0
CheckPhase1_A	674959995	559	0	0
CheckPhase2_A	674959995	549	0	0
CheckPhase3_A	674959995	544	0	0
CheckTimeout0_A	674959995	620	0	0
CheckTimeoutSt1_A	674959995	79972	0	0
CheckTimeoutSt2_A	674959995	514	0	0
CheckTimeoutStTrig_A	674959995	88	0	0
ErrorStAllEscAsserted_A	674959995	1018	0	0
ErrorStIsTerminal_A	674959995	838	0	0
EscStateOut_A	674844385	674772097	0	0
u_state_regs_A	674959995	674811777	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	200	0	0
T11	23684	24	0	0
T12	0	49	0	0
T13	0	71	0	0
T26	0	25	0	0
T27	0	31	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	464	0	0
T1	148421	3	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T8	0	1	0	0
T14	0	4	0	0
T15	0	5	0	0
T17	598302	2	0	0
T18	895184	1	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	18	0	0
T6	37396	0	0	0
T7	67086	0	0	0
T9	742480	0	0	0
T14	136202	0	0	0
T18	895184	1	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	1	0	0
T47	0	1	0	0
T50	0	1	0	0
T57	60443	0	0	0
T73	264478	0	0	0
T96	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	199	0	0
T1	148421	1	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	598302	4	0	0
T18	895184	1	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T38	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674845748	311637746	0	0
T1	148421	191521	0	0
T2	3668	3121	0	0
T3	21060	20998	0	0
T4	558090	557511	0	0
T5	128618	120143	0	0
T17	598302	527559	0	0
T18	895184	676354	0	0
T19	21554	5519	0	0
T20	75602	70291	0	0
T21	21997	21911	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	565	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	0	4	0	0
T15	0	4	0	0
T17	598302	5	0	0
T18	895184	3	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	559	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	0	4	0	0
T15	0	4	0	0
T17	598302	5	0	0
T18	895184	3	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	549	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	0	4	0	0
T15	0	4	0	0
T17	598302	5	0	0
T18	895184	2	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	544	0	0
T1	148421	4	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	0	4	0	0
T15	0	4	0	0
T17	598302	5	0	0
T18	895184	2	0	0
T19	21554	0	0	0
T20	75602	1	0	0
T21	21997	0	0	0
T37	0	1	0	0
T38	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	620	0	0
T1	148421	17	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	1	0	0
T14	0	10	0	0
T16	0	2	0	0
T17	598302	6	0	0
T18	895184	2	0	0
T19	21554	5	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T66	0	4	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	79972	0	0
T1	148421	552	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	70	0	0
T14	0	1315	0	0
T16	0	89	0	0
T17	598302	867	0	0
T18	895184	147	0	0
T19	21554	469	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T66	0	685	0	0
T73	0	185	0	0
T74	0	173	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	514	0	0
T1	148421	16	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T14	0	10	0	0
T16	0	2	0	0
T17	598302	3	0	0
T18	895184	0	0	0
T19	21554	5	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T66	0	3	0	0
T68	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	88	0	0
T1	148421	1	0	0
T2	3668	0	0	0
T3	21060	0	0	0
T4	558090	0	0	0
T5	128618	0	0	0
T7	0	1	0	0
T17	598302	3	0	0
T18	895184	1	0	0
T19	21554	0	0	0
T20	75602	0	0	0
T21	21997	0	0	0
T25	0	2	0	0
T43	0	2	0	0
T66	0	1	0	0
T68	0	1	0	0
T70	0	2	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	1018	0	0
T11	23684	163	0	0
T12	0	177	0	0
T13	0	346	0	0
T26	0	157	0	0
T27	0	175	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	838	0	0
T11	23684	133	0	0
T12	0	147	0	0
T13	0	286	0	0
T26	0	127	0	0
T27	0	145	0	0
T28	362151	0	0	0
T29	44925	0	0	0
T30	5089	0	0	0
T31	527727	0	0	0
T32	414126	0	0	0
T33	36739	0	0	0
T34	109515	0	0	0
T35	532473	0	0	0
T36	89584	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674844385	674772097	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	674959995	674811777	0	0
T1	148421	148366	0	0
T2	3668	3583	0	0
T3	21060	20999	0	0
T4	558090	558081	0	0
T5	128618	128611	0	0
T17	598302	598293	0	0
T18	895184	894662	0	0
T19	21554	21486	0	0
T20	75602	75502	0	0
T21	21997	21912	0	0