Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.77 100.00 96.31 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T17 Yes T7,T8,T17 INPUT
ping_ok_o Yes Yes T7,T8,T17 Yes T7,T8,T17 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T17 Yes T8,T18,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T23 Yes T7,T8,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T80 Yes T8,T18,T80 INPUT
ping_ok_o Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
integ_fail_o Yes Yes T4,T14,T5 Yes T4,T14,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T80 Yes T8,T18,T47 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T47 Yes T8,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T18,T22 Yes T7,T18,T22 INPUT
ping_ok_o Yes Yes T7,T18,T22 Yes T7,T18,T22 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T18,T22 Yes T18,T23,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T23,T145 Yes T7,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T17,T18 Yes T8,T17,T18 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T17,T18 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T22 Yes T8,T18,T22 INPUT
ping_ok_o Yes Yes T8,T18,T22 Yes T8,T18,T22 OUTPUT
integ_fail_o Yes Yes T7,T8,T80 Yes T7,T8,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T22 Yes T8,T18,T80 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T80 Yes T8,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T8,T17 Yes T6,T8,T17 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T1,T8,T17 Yes T1,T8,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T8,T17 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T6,T8,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T30,T16 Yes T18,T30,T16 INPUT
ping_ok_o Yes Yes T18,T30,T16 Yes T18,T30,T16 OUTPUT
integ_fail_o Yes Yes T4,T8,T80 Yes T4,T8,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T30,T16 Yes T18,T16,T146 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T16,T146 Yes T18,T30,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T80 Yes T8,T18,T80 INPUT
ping_ok_o Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
integ_fail_o Yes Yes T1,T4,T7 Yes T1,T4,T7 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T19,T80 Yes T18,T19,T80 INPUT
ping_ok_o Yes Yes T18,T19,T80 Yes T18,T19,T80 OUTPUT
integ_fail_o Yes Yes T7,T17,T33 Yes T7,T17,T33 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T19,T80 Yes T18,T80,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T80,T145 Yes T18,T19,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T17,T18,T23 Yes T17,T18,T23 INPUT
ping_ok_o Yes Yes T17,T18,T23 Yes T17,T18,T23 OUTPUT
integ_fail_o Yes Yes T4,T5,T8 Yes T4,T5,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T17,T18,T23 Yes T17,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T17,T18,T145 Yes T17,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T80 Yes T8,T18,T80 INPUT
ping_ok_o Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
integ_fail_o Yes Yes T1,T5,T72 Yes T1,T5,T72 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T80 Yes T8,T18,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T16 Yes T8,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T8,T17 Yes T6,T8,T17 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T14,T7,T72 Yes T14,T7,T72 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T8,T17 Yes T6,T8,T18 OUTPUT
alert_rx_o.ping_p Yes Yes T6,T8,T18 Yes T6,T8,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T22 Yes T8,T18,T22 INPUT
ping_ok_o Yes Yes T8,T18,T22 Yes T8,T18,T22 OUTPUT
integ_fail_o Yes Yes T5,T7,T17 Yes T5,T7,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T22 Yes T8,T18,T33 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T33 Yes T8,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T80 Yes T8,T18,T80 INPUT
ping_ok_o Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T19 Yes T8,T18,T19 INPUT
ping_ok_o Yes Yes T8,T18,T19 Yes T8,T18,T19 OUTPUT
integ_fail_o Yes Yes T4,T8,T17 Yes T4,T8,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T19 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T18,T19 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T19 Yes T8,T18,T19 INPUT
ping_ok_o Yes Yes T8,T18,T19 Yes T8,T18,T19 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T19 Yes T8,T18,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T16 Yes T8,T18,T19 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T19 Yes T8,T18,T19 INPUT
ping_ok_o Yes Yes T8,T18,T19 Yes T8,T18,T19 OUTPUT
integ_fail_o Yes Yes T1,T14,T5 Yes T1,T14,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T19 Yes T8,T18,T71 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T71 Yes T8,T18,T19 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T21 Yes T8,T18,T21 INPUT
ping_ok_o Yes Yes T8,T18,T21 Yes T8,T18,T21 OUTPUT
integ_fail_o Yes Yes T1,T7,T8 Yes T1,T7,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T16 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T18,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T4,T5,T8 Yes T4,T5,T8 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T104 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T104 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T8,T17 Yes T6,T8,T17 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T1,T4,T7 Yes T1,T4,T7 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T8,T17 Yes T8,T18,T80 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T80 Yes T6,T8,T17 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T7,T8,T80 Yes T7,T8,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T80 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T80 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T17,T18 Yes T8,T17,T18 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T1,T5,T8 Yes T1,T5,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T17,T18 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T17,T18 Yes T8,T17,T18 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T1,T4,T80 Yes T1,T4,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T17,T18 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T4,T14,T7 Yes T4,T14,T7 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T16 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T20 Yes T8,T18,T20 INPUT
ping_ok_o Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
integ_fail_o Yes Yes T8,T80,T16 Yes T8,T80,T16 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T20 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T18,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T19,T80 Yes T18,T19,T80 INPUT
ping_ok_o Yes Yes T18,T19,T80 Yes T18,T19,T80 OUTPUT
integ_fail_o Yes Yes T4,T5,T7 Yes T4,T5,T7 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T19,T80 Yes T18,T145,T147 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T147 Yes T18,T19,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T23,T80 Yes T18,T23,T80 INPUT
ping_ok_o Yes Yes T18,T23,T80 Yes T18,T23,T80 OUTPUT
integ_fail_o Yes Yes T1,T5,T7 Yes T1,T5,T7 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T23,T80 Yes T18,T23,T80 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T23,T80 Yes T18,T23,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T1,T8,T17 Yes T1,T8,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T21 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T80,T69 Yes T18,T80,T69 INPUT
ping_ok_o Yes Yes T18,T80,T16 Yes T18,T80,T16 OUTPUT
integ_fail_o Yes Yes T14,T5,T72 Yes T14,T5,T72 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T80,T69 Yes T18,T145,T147 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T147 Yes T18,T80,T69 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T70,T71 Yes T18,T70,T71 INPUT
ping_ok_o Yes Yes T18,T70,T71 Yes T18,T70,T71 OUTPUT
integ_fail_o Yes Yes T4,T5,T80 Yes T4,T5,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T70,T71 Yes T18,T70,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T70,T145 Yes T18,T70,T71 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T18,T23 Yes T6,T18,T23 INPUT
ping_ok_o Yes Yes T18,T23,T145 Yes T18,T23,T145 OUTPUT
integ_fail_o Yes Yes T1,T14,T80 Yes T1,T14,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T18,T23 Yes T18,T23,T111 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T23,T111 Yes T6,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T23 Yes T8,T18,T23 INPUT
ping_ok_o Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
integ_fail_o Yes Yes T4,T17,T33 Yes T4,T17,T33 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T5,T18,T23 Yes T5,T18,T23 INPUT
ping_ok_o Yes Yes T5,T18,T23 Yes T5,T18,T23 OUTPUT
integ_fail_o Yes Yes T4,T8,T33 Yes T4,T8,T33 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T18,T23 Yes T5,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T18,T145 Yes T5,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T18,T80 Yes T6,T18,T80 INPUT
ping_ok_o Yes Yes T18,T80,T71 Yes T18,T80,T71 OUTPUT
integ_fail_o Yes Yes T1,T30,T16 Yes T1,T30,T16 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T18,T80 Yes T18,T80,T71 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T80,T71 Yes T6,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T5,T7,T17 Yes T5,T7,T17 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T70 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T70 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T30 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T20,T21 Yes T18,T20,T21 INPUT
ping_ok_o Yes Yes T18,T21,T30 Yes T18,T21,T30 OUTPUT
integ_fail_o Yes Yes T5,T7,T33 Yes T5,T7,T33 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T20,T69 Yes T18,T145,T147 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T147 Yes T18,T20,T69 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T17,T18,T23 Yes T17,T18,T23 INPUT
ping_ok_o Yes Yes T17,T18,T23 Yes T17,T18,T23 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T17,T18,T23 Yes T18,T23,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T23,T145 Yes T17,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T17,T18,T22 Yes T17,T18,T22 INPUT
ping_ok_o Yes Yes T17,T18,T22 Yes T17,T18,T22 OUTPUT
integ_fail_o Yes Yes T1,T5,T8 Yes T1,T5,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T17,T18,T22 Yes T17,T18,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T17,T18,T23 Yes T17,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T18,T80 Yes T7,T18,T80 INPUT
ping_ok_o Yes Yes T7,T18,T80 Yes T7,T18,T80 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T18,T80 Yes T18,T69,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T69,T16 Yes T7,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T17,T18,T20 Yes T17,T18,T20 INPUT
ping_ok_o Yes Yes T17,T18,T23 Yes T17,T18,T23 OUTPUT
integ_fail_o Yes Yes T14,T5,T17 Yes T14,T5,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T17,T18,T20 Yes T18,T70,T30 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T70,T30 Yes T17,T18,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T17,T18 Yes T8,T17,T18 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T4,T7,T17 Yes T4,T7,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T17,T18 Yes T8,T18,T72 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T72 Yes T8,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T7,T18 Yes T6,T7,T18 INPUT
ping_ok_o Yes Yes T7,T18,T80 Yes T7,T18,T80 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T7,T18 Yes T18,T80,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T80,T145 Yes T6,T7,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T18,T19 Yes T7,T18,T19 INPUT
ping_ok_o Yes Yes T7,T18,T19 Yes T7,T18,T19 OUTPUT
integ_fail_o Yes Yes T4,T33,T72 Yes T4,T33,T72 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T18,T19 Yes T18,T80,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T80,T145 Yes T7,T18,T19 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T18,T22 Yes T7,T18,T22 INPUT
ping_ok_o Yes Yes T7,T18,T22 Yes T7,T18,T22 OUTPUT
integ_fail_o Yes Yes T4,T14,T5 Yes T4,T14,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T18,T22 Yes T18,T22,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T22,T16 Yes T7,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T7,T8,T18 Yes T7,T8,T18 INPUT
ping_ok_o Yes Yes T7,T8,T18 Yes T7,T8,T18 OUTPUT
integ_fail_o Yes Yes T1,T72,T30 Yes T1,T72,T30 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T8,T18 Yes T8,T18,T70 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T70 Yes T7,T8,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T23 Yes T8,T18,T23 INPUT
ping_ok_o Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T80,T16 Yes T18,T80,T16 INPUT
ping_ok_o Yes Yes T18,T80,T16 Yes T18,T80,T16 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T80,T16 Yes T18,T145,T78 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T78 Yes T18,T80,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T80 Yes T8,T18,T80 INPUT
ping_ok_o Yes Yes T8,T18,T80 Yes T8,T18,T80 OUTPUT
integ_fail_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T80 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T18,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T22,T80 Yes T18,T22,T80 INPUT
ping_ok_o Yes Yes T18,T22,T80 Yes T18,T22,T80 OUTPUT
integ_fail_o Yes Yes T1,T14,T5 Yes T1,T14,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T22,T80 Yes T18,T80,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T80,T16 Yes T18,T22,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T17,T18,T22 Yes T17,T18,T22 INPUT
ping_ok_o Yes Yes T17,T18,T22 Yes T17,T18,T22 OUTPUT
integ_fail_o Yes Yes T14,T7,T8 Yes T14,T7,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T17,T18,T22 Yes T17,T18,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T17,T18,T23 Yes T17,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T17,T18 Yes T6,T17,T18 INPUT
ping_ok_o Yes Yes T17,T18,T47 Yes T17,T18,T47 OUTPUT
integ_fail_o Yes Yes T7,T8,T17 Yes T7,T8,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T17,T18 Yes T18,T30,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T30,T145 Yes T6,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T80,T146 Yes T18,T80,T146 INPUT
ping_ok_o Yes Yes T18,T80,T146 Yes T18,T80,T146 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T80,T148 Yes T18,T145,T147 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T147 Yes T18,T80,T148 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T17,T18 Yes T8,T17,T18 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T17,T18 Yes T8,T18,T47 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T47 Yes T8,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T33,T16 Yes T18,T33,T16 INPUT
ping_ok_o Yes Yes T18,T33,T16 Yes T18,T33,T16 OUTPUT
integ_fail_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T33,T16 Yes T18,T16,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T16,T145 Yes T18,T33,T16 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T7,T18 Yes T6,T7,T18 INPUT
ping_ok_o Yes Yes T7,T18,T47 Yes T7,T18,T47 OUTPUT
integ_fail_o Yes Yes T5,T7,T8 Yes T5,T7,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T7,T18 Yes T18,T47,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T47,T145 Yes T6,T7,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T22,T80 Yes T18,T22,T80 INPUT
ping_ok_o Yes Yes T18,T22,T80 Yes T18,T22,T80 OUTPUT
integ_fail_o Yes Yes T4,T7,T8 Yes T4,T7,T8 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T22,T80 Yes T18,T145,T147 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T147 Yes T18,T22,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T6,T18,T22 Yes T6,T18,T22 INPUT
ping_ok_o Yes Yes T18,T22,T80 Yes T18,T22,T80 OUTPUT
integ_fail_o Yes Yes T1,T4,T14 Yes T1,T4,T14 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T18,T22 Yes T18,T30,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T30,T16 Yes T6,T18,T22 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T22,T80 Yes T18,T22,T80 INPUT
ping_ok_o Yes Yes T18,T22,T80 Yes T18,T22,T80 OUTPUT
integ_fail_o Yes Yes T1,T8,T17 Yes T1,T8,T17 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T22,T80 Yes T18,T80,T16 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T80,T16 Yes T18,T22,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T18,T23 Yes T8,T18,T23 INPUT
ping_ok_o Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
integ_fail_o Yes Yes T80,T75,T87 Yes T80,T75,T87 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T23 Yes T8,T18,T23 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T8,T17,T18 Yes T8,T17,T18 INPUT
ping_ok_o Yes Yes T8,T17,T18 Yes T8,T17,T18 OUTPUT
integ_fail_o Yes Yes T4,T14,T17 Yes T4,T14,T17 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T17,T18 Yes T8,T18,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T18,T145 Yes T8,T17,T18 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T73,T104 Yes T18,T73,T104 INPUT
ping_ok_o Yes Yes T18,T104,T145 Yes T18,T104,T145 OUTPUT
integ_fail_o Yes Yes T4,T17,T80 Yes T4,T17,T80 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T73,T145 Yes T18,T145,T53 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T145,T53 Yes T18,T73,T145 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T4,T5 Yes T1,T2,T12 INPUT
ping_req_i Yes Yes T18,T20,T80 Yes T18,T20,T80 INPUT
ping_ok_o Yes Yes T18,T80,T70 Yes T18,T80,T70 OUTPUT
integ_fail_o Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
alert_o Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T12 Yes T1,T3,T12 OUTPUT
alert_rx_o.ping_n Yes Yes T18,T20,T80 Yes T18,T16,T145 OUTPUT
alert_rx_o.ping_p Yes Yes T18,T16,T145 Yes T18,T20,T80 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT

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