Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	63025676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30620338

1

T1

2453

T2

642

T3

93623

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14140647	1			T1	1096		T2	398		T3	37205
values[0x0]	38701489	1			T1	3201		T2	807		T3	129153
values[0x1]	40803878	1			T1	3261		T2	845		T3	128837

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53730921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39915093

1

T1

3087

T2

841

T3

118464

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	286191	1			T1	13		T2	10		T3	1135
valid_sources[0x01]	278713	1			T1	13		T2	6		T3	1145
valid_sources[0x02]	277152	1			T1	2		T2	5		T3	1181
valid_sources[0x03]	285734	1			T1	74		T2	12		T3	1157
valid_sources[0x04]	282652	1			T1	7		T2	4		T3	1104
valid_sources[0x05]	772671	1			T1	64		T2	12		T3	1197
valid_sources[0x06]	279140	1			T1	14		T2	1		T3	1222
valid_sources[0x07]	497383	1			T2	7		T3	1170		T4	1373
valid_sources[0x08]	279951	1			T2	6		T3	1145		T4	1442
valid_sources[0x09]	277736	1			T1	8		T2	9		T3	1190
valid_sources[0x0a]	271080	1			T2	8		T3	1120		T4	1457
valid_sources[0x0b]	280110	1			T1	66		T2	8		T3	1171
valid_sources[0x0c]	279357	1			T1	34		T2	17		T3	1118
valid_sources[0x0d]	275450	1			T1	15		T2	11		T3	1220
valid_sources[0x0e]	277039	1			T1	30		T2	10		T3	1157
valid_sources[0x0f]	273670	1			T1	109		T2	5		T3	1095
valid_sources[0x10]	308017	1			T1	31		T2	5		T3	1162
valid_sources[0x11]	587055	1			T2	8		T3	1109		T4	1542
valid_sources[0x12]	308935	1			T1	48		T2	3		T3	1169
valid_sources[0x13]	273116	1			T1	7		T2	5		T3	1128
valid_sources[0x14]	278045	1			T1	53		T2	8		T3	1181
valid_sources[0x15]	275277	1			T1	45		T2	12		T3	1090
valid_sources[0x16]	277667	1			T1	18		T2	7		T3	1116
valid_sources[0x17]	279774	1			T1	10		T2	9		T3	1152
valid_sources[0x18]	284797	1			T1	67		T2	9		T3	1133
valid_sources[0x19]	272422	1			T1	22		T2	9		T3	1162
valid_sources[0x1a]	276957	1			T1	19		T2	5		T3	1217
valid_sources[0x1b]	278539	1			T1	12		T2	8		T3	1127
valid_sources[0x1c]	284480	1			T1	7		T2	6		T3	1099
valid_sources[0x1d]	273630	1			T1	31		T2	7		T3	1187
valid_sources[0x1e]	277607	1			T1	4		T2	12		T3	1116
valid_sources[0x1f]	280254	1			T1	50		T2	14		T3	1079
valid_sources[0x20]	284391	1			T1	53		T2	11		T3	1210
valid_sources[0x21]	282363	1			T1	52		T2	11		T3	1129
valid_sources[0x22]	278491	1			T1	19		T2	10		T3	1219
valid_sources[0x23]	277725	1			T1	4		T2	5		T3	1157
valid_sources[0x24]	598806	1			T1	8		T2	14		T3	1160
valid_sources[0x25]	594071	1			T2	8		T3	1183		T4	1421
valid_sources[0x26]	280751	1			T1	16		T2	4		T3	1102
valid_sources[0x27]	277225	1			T2	7		T3	1248		T4	1401
valid_sources[0x28]	284207	1			T2	7		T3	1184		T4	1431
valid_sources[0x29]	280123	1			T1	22		T2	6		T3	1162
valid_sources[0x2a]	271409	1			T1	40		T2	10		T3	1120
valid_sources[0x2b]	292616	1			T1	71		T2	6		T3	1129
valid_sources[0x2c]	498959	1			T1	16		T2	6		T3	1123
valid_sources[0x2d]	281159	1			T1	112		T2	7		T3	1102
valid_sources[0x2e]	280459	1			T1	5		T2	12		T3	1185
valid_sources[0x2f]	278142	1			T1	15		T2	4		T3	1164
valid_sources[0x30]	699669	1			T2	13		T3	1191		T4	1472
valid_sources[0x31]	281932	1			T1	36		T2	4		T3	1115
valid_sources[0x32]	284945	1			T1	15		T2	8		T3	1172
valid_sources[0x33]	280303	1			T1	3		T2	10		T3	1154
valid_sources[0x34]	271772	1			T1	35		T2	6		T3	1143
valid_sources[0x35]	273622	1			T1	34		T2	11		T3	1167
valid_sources[0x36]	274278	1			T1	26		T2	12		T3	1187
valid_sources[0x37]	277438	1			T1	66		T2	16		T3	1142
valid_sources[0x38]	647381	1			T1	60		T2	9		T3	1157
valid_sources[0x39]	275678	1			T1	1		T2	7		T3	1195
valid_sources[0x3a]	859750	1			T1	44		T2	4		T3	1147
valid_sources[0x3b]	273219	1			T1	42		T2	8		T3	1163
valid_sources[0x3c]	289793	1			T1	56		T2	7		T3	1169
valid_sources[0x3d]	684280	1			T1	3		T2	8		T3	1152
valid_sources[0x3e]	477000	1			T1	38		T2	11		T3	1164
valid_sources[0x3f]	277280	1			T1	48		T2	10		T3	1184
valid_sources[0x40]	291402	1			T1	31		T2	6		T3	1142
valid_sources[0x41]	275590	1			T1	20		T2	4		T3	1181
valid_sources[0x42]	591116	1			T1	40		T2	2		T3	1103
valid_sources[0x43]	283704	1			T1	49		T2	10		T3	1153
valid_sources[0x44]	709806	1			T2	6		T3	1044		T4	1463
valid_sources[0x45]	281176	1			T2	10		T3	1131		T4	1422
valid_sources[0x46]	278703	1			T1	29		T2	11		T3	1146
valid_sources[0x47]	274000	1			T1	15		T2	9		T3	1113
valid_sources[0x48]	274417	1			T1	73		T2	8		T3	1168
valid_sources[0x49]	284971	1			T1	74		T2	8		T3	1211
valid_sources[0x4a]	281633	1			T1	90		T2	11		T3	1215
valid_sources[0x4b]	279102	1			T1	30		T2	10		T3	1134
valid_sources[0x4c]	414759	1			T1	10		T2	5		T3	1140
valid_sources[0x4d]	285953	1			T1	67		T2	4		T3	1143
valid_sources[0x4e]	274387	1			T1	14		T2	13		T3	1138
valid_sources[0x4f]	272570	1			T1	16		T2	5		T3	1123
valid_sources[0x50]	784429	1			T1	5		T2	5		T3	1191
valid_sources[0x51]	283496	1			T1	25		T2	4		T3	1150
valid_sources[0x52]	1020877	1			T1	36		T2	4		T3	1175
valid_sources[0x53]	270225	1			T1	45		T2	5		T3	1156
valid_sources[0x54]	276199	1			T1	42		T2	12		T3	1115
valid_sources[0x55]	280810	1			T1	16		T2	4		T3	1211
valid_sources[0x56]	272074	1			T1	28		T2	3		T3	1148
valid_sources[0x57]	562533	1			T1	73		T2	3		T3	1167
valid_sources[0x58]	280397	1			T1	83		T2	5		T3	1190
valid_sources[0x59]	953469	1			T1	14		T2	7		T3	1109
valid_sources[0x5a]	634409	1			T2	12		T3	1147		T4	1498
valid_sources[0x5b]	275414	1			T1	32		T2	7		T3	1147
valid_sources[0x5c]	281784	1			T1	7		T2	14		T3	1070
valid_sources[0x5d]	271177	1			T1	93		T2	6		T3	1204
valid_sources[0x5e]	278785	1			T1	45		T2	16		T3	1119
valid_sources[0x5f]	274952	1			T1	61		T2	6		T3	1193
valid_sources[0x60]	273716	1			T1	71		T2	5		T3	1221
valid_sources[0x61]	296367	1			T1	22		T2	9		T3	1133
valid_sources[0x62]	293718	1			T1	15		T2	12		T3	1156
valid_sources[0x63]	282572	1			T1	27		T2	10		T3	1091
valid_sources[0x64]	273424	1			T1	20		T2	10		T3	1128
valid_sources[0x65]	283373	1			T2	11		T3	1160		T4	1413
valid_sources[0x66]	267926	1			T1	72		T2	5		T3	1190
valid_sources[0x67]	316102	1			T1	17		T2	8		T3	1148
valid_sources[0x68]	277490	1			T1	57		T2	14		T3	1191
valid_sources[0x69]	318821	1			T1	12		T2	4		T3	1168
valid_sources[0x6a]	277009	1			T1	18		T2	7		T3	1261
valid_sources[0x6b]	281918	1			T1	84		T2	10		T3	1233
valid_sources[0x6c]	289845	1			T1	16		T2	9		T3	1156
valid_sources[0x6d]	279328	1			T2	7		T3	1173		T4	1445
valid_sources[0x6e]	272481	1			T1	7		T2	10		T3	1119
valid_sources[0x6f]	279476	1			T1	14		T2	10		T3	1156
valid_sources[0x70]	272920	1			T1	22		T2	13		T3	1155
valid_sources[0x71]	731473	1			T2	8		T3	1149		T4	1389
valid_sources[0x72]	279703	1			T1	33		T2	7		T3	1171
valid_sources[0x73]	726860	1			T1	6		T2	7		T3	1147
valid_sources[0x74]	280633	1			T1	46		T2	9		T3	1162
valid_sources[0x75]	493219	1			T1	14		T2	3		T3	1161
valid_sources[0x76]	661170	1			T1	2		T2	6		T3	1131
valid_sources[0x77]	273677	1			T1	30		T2	20		T3	1127
valid_sources[0x78]	281640	1			T1	19		T2	11		T3	1164
valid_sources[0x79]	285272	1			T1	10		T2	3		T3	1137
valid_sources[0x7a]	1102848	1			T1	10		T2	15		T3	1176
valid_sources[0x7b]	587069	1			T1	22		T2	11		T3	1146
valid_sources[0x7c]	290897	1			T1	42		T2	6		T3	1146
valid_sources[0x7d]	275181	1			T1	37		T2	4		T3	1156
valid_sources[0x7e]	274415	1			T1	59		T2	7		T3	1148
valid_sources[0x7f]	288985	1			T1	3		T2	15		T3	1171
valid_sources[0x80]	275388	1			T2	4		T3	1212		T4	1382

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7060622

1

T1

561

T2

184

T3

18529

values[0x0]

all_enables

biggest_size

14856880

1

T1

1193

T2

279

T3

48192

values[0x1]

all_enables

biggest_size

8702836

1

T1

699

T2

179

T3

26902