Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T191,T192
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16469	0	0
DisabledNoTrigBkwd_A	2147483647	759961	0	0
DisabledNoTrigFwd_A	2147483647	1619072239	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16469	0	0
T7	481823	0	0	0
T8	677982	0	0	0
T12	291968	0	0	0
T23	17526	0	0	0
T31	39774	0	0	0
T37	1162	412	0	0
T38	14653	0	0	0
T39	29232	0	0	0
T70	23412	0	0	0
T84	77837	0	0	0
T95	194010	0	0	0
T97	22634	0	0	0
T179	0	1100	0	0
T191	0	413	0	0
T192	0	1416	0	0
T193	3106	545	0	0
T194	9858	1222	0	0
T195	0	1647	0	0
T196	0	811	0	0
T197	0	293	0	0
T198	0	189	0	0
T199	0	723	0	0
T200	0	1260	0	0
T201	0	459	0	0
T202	0	623	0	0
T203	0	808	0	0
T204	0	474	0	0
T205	0	622	0	0
T206	0	1713	0	0
T207	0	976	0	0
T208	0	763	0	0
T209	446556	0	0	0
T210	568441	0	0	0
T211	101829	0	0	0
T212	36458	0	0	0
T213	7620	0	0	0
T214	395941	0	0	0
T215	589992	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	759961	0	0
T1	314396	21	0	0
T2	95608	7	0	0
T3	3473424	5225	0	0
T4	653628	697	0	0
T5	165820	0	0	0
T6	465952	1705	0	0
T7	0	1	0	0
T10	500344	0	0	0
T12	0	3552	0	0
T13	0	6	0	0
T14	0	615	0	0
T16	9352	0	0	0
T17	17540	282	0	0
T18	113400	28	0	0
T19	0	34	0	0
T20	0	2	0	0
T22	0	14	0	0
T24	0	2	0	0
T31	0	32	0	0
T36	0	131	0	0
T37	0	10	0	0
T38	0	16	0	0
T39	0	2	0	0
T60	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1619072239	0	0
T1	314396	197423	0	0
T2	95608	53773	0	0
T3	3473424	879232	0	0
T4	653628	333875	0	0
T5	165820	64028	0	0
T6	465952	350503	0	0
T10	500344	398928	0	0
T16	9352	7818	0	0
T17	17540	10692	0	0
T18	113400	95251	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T205
1	1	Covered	T1,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	710213091	1844	0	0
DisabledNoTrigBkwd_A	710213091	214606	0	0
DisabledNoTrigFwd_A	710213091	370835945	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1844	0	0
T84	77837	0	0	0
T97	11317	0	0	0
T194	4929	1222	0	0
T205	0	622	0	0
T209	223278	0	0	0
T210	568441	0	0	0
T211	101829	0	0	0
T212	36458	0	0	0
T213	7620	0	0	0
T214	395941	0	0	0
T215	589992	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	214606	0	0
T1	78599	9	0	0
T2	23902	0	0	0
T3	868356	1660	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	3	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	3	0	0
T18	28350	28	0	0
T19	0	2	0	0
T20	0	2	0	0
T31	0	19	0	0
T36	0	131	0	0
T38	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	370835945	0	0
T1	78599	54072	0	0
T2	23902	23829	0	0
T3	868356	1431	0	0
T4	163407	163398	0	0
T5	41455	16007	0	0
T6	116488	115928	0	0
T10	125086	99732	0	0
T16	2338	2258	0	0
T17	4385	602	0	0
T18	28350	10441	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T191,T192
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	710213091	4319	0	0
DisabledNoTrigBkwd_A	710213091	144221	0	0
DisabledNoTrigFwd_A	710213091	412145554	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	4319	0	0
T7	481823	0	0	0
T8	677982	0	0	0
T12	291968	0	0	0
T23	17526	0	0	0
T31	39774	0	0	0
T37	1162	412	0	0
T38	14653	0	0	0
T39	29232	0	0	0
T70	23412	0	0	0
T95	194010	0	0	0
T191	0	413	0	0
T192	0	1416	0	0
T196	0	811	0	0
T201	0	459	0	0
T203	0	808	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	144221	0	0
T1	78599	2	0	0
T2	23902	2	0	0
T3	868356	1981	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	1702	0	0
T10	125086	0	0	0
T12	0	886	0	0
T16	2338	0	0	0
T17	4385	279	0	0
T18	28350	0	0	0
T19	0	16	0	0
T22	0	7	0	0
T37	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	412145554	0	0
T1	78599	62058	0	0
T2	23902	3047	0	0
T3	868356	7065	0	0
T4	163407	3839	0	0
T5	41455	16007	0	0
T6	116488	1613	0	0
T10	125086	99732	0	0
T16	2338	1649	0	0
T17	4385	1476	0	0
T18	28350	28270	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T195,T179
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	710213091	7063	0	0
DisabledNoTrigBkwd_A	710213091	186539	0	0
DisabledNoTrigFwd_A	710213091	408066747	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	7063	0	0
T94	470768	0	0	0
T97	11317	0	0	0
T179	0	1100	0	0
T193	3106	545	0	0
T194	4929	0	0	0
T195	0	1647	0	0
T198	0	189	0	0
T199	0	723	0	0
T200	0	1260	0	0
T202	0	623	0	0
T207	0	976	0	0
T209	223278	0	0	0
T216	137131	0	0	0
T217	60341	0	0	0
T218	2979	0	0	0
T219	228474	0	0	0
T220	406308	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	186539	0	0
T1	78599	8	0	0
T2	23902	5	0	0
T3	868356	1584	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1194	0	0
T13	0	5	0	0
T14	0	615	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	4	0	0
T38	0	7	0	0
T39	0	2	0	0
T60	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	408066747	0	0
T1	78599	62569	0	0
T2	23902	3068	0	0
T3	868356	2447	0	0
T4	163407	162791	0	0
T5	41455	16007	0	0
T6	116488	116481	0	0
T10	125086	99732	0	0
T16	2338	1653	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T204,T206
1	1	Covered	T1,T4,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	710213091	3243	0	0
DisabledNoTrigBkwd_A	710213091	214595	0	0
DisabledNoTrigFwd_A	710213091	428023993	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	3243	0	0
T197	961	293	0	0
T204	0	474	0	0
T206	0	1713	0	0
T208	0	763	0	0
T221	464517	0	0	0
T222	27650	0	0	0
T223	122284	0	0	0
T224	526831	0	0	0
T225	14078	0	0	0
T226	352208	0	0	0
T227	8119	0	0	0
T228	242397	0	0	0
T229	216083	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	214595	0	0
T1	78599	2	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	696	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T7	0	1	0	0
T10	125086	0	0	0
T12	0	1472	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	12	0	0
T22	0	7	0	0
T24	0	2	0	0
T31	0	13	0	0
T38	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	428023993	0	0
T1	78599	18724	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	3847	0	0
T5	41455	16007	0	0
T6	116488	116481	0	0
T10	125086	99732	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0