Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T16,T19
1	1	1	Covered	T1,T16,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T22
0	1	Covered	T23,T24,T25
1	0	Covered	T13,T24,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T22
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T13,T24,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T22
1	0	Covered	T25,T27,T28
1	1	Covered	T23,T24,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T16,T22

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T16,T22
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T15,T29,T30
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T3,T12,T24
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T24,T15
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T31,T32
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T6
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T16,T22
TimeoutSt->Phase0St	172	Covered	T23,T13,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T13,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T29,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T12,T24
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T24,T15
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T31,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1322	0	0
CheckAccumTrig0_A	2147483647	2196	0	0
CheckAccumTrig1_A	2147483647	119	0	0
CheckClr_A	2147483647	1001	0	0
CheckEn_A	2147483647	1238414824	0	0
CheckPhase0_A	2147483647	2478	0	0
CheckPhase1_A	2147483647	2431	0	0
CheckPhase2_A	2147483647	2379	0	0
CheckPhase3_A	2147483647	2325	0	0
CheckTimeout0_A	2147483647	3201	0	0
CheckTimeoutSt1_A	2147483647	413639	0	0
CheckTimeoutSt2_A	2147483647	2875	0	0
CheckTimeoutStTrig_A	2147483647	206	0	0
ErrorStAllEscAsserted_A	2147483647	6351	0	0
ErrorStIsTerminal_A	2147483647	5271	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1322	0	0
T5	165820	278	0	0
T6	465952	0	0	0
T10	500344	334	0	0
T11	0	284	0	0
T12	1167872	0	0	0
T18	113400	0	0	0
T19	62612	0	0	0
T20	168628	0	0	0
T22	102332	0	0	0
T34	0	296	0	0
T35	0	130	0	0
T36	963028	0	0	0
T37	4648	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196	0	0
T1	314396	6	0	0
T2	95608	2	0	0
T3	3473424	5	0	0
T4	653628	2	0	0
T5	165820	0	0	0
T6	465952	2	0	0
T7	0	1	0	0
T10	500344	0	0	0
T12	0	6	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	9352	0	0	0
T17	17540	2	0	0
T18	113400	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T22	0	3	0	0
T24	0	1	0	0
T31	0	6	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119	0	0
T9	219504	0	0	0
T13	137686	1	0	0
T14	226870	0	0	0
T15	1925230	0	0	0
T21	122728	0	0	0
T24	187528	2	0	0
T25	150398	0	0	0
T26	666706	1	0	0
T29	0	1	0	0
T41	813175	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	194136	0	0	0
T59	27920	0	0	0
T60	35052	0	0	0
T61	21526	0	0	0
T62	27450	0	0	0
T63	88987	0	0	0
T64	38490	0	0	0
T65	6273	0	0	0
T66	44522	0	0	0
T67	157188	0	0	0
T68	18992	0	0	0
T69	21196	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1001	0	0
T1	157198	1	0	0
T2	71706	2	0	0
T3	3473424	2	0	0
T4	653628	0	0	0
T5	165820	0	0	0
T6	465952	1	0	0
T9	0	1	0	0
T10	500344	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T15	0	6	0	0
T16	9352	0	0	0
T17	17540	0	0	0
T18	113400	0	0	0
T19	31306	2	0	0
T20	42157	0	0	0
T24	0	5	0	0
T26	0	4	0	0
T30	0	1	0	0
T31	0	6	0	0
T32	0	3	0	0
T38	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T66	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1238414824	0	0
T1	314396	43306	0	0
T2	95608	53771	0	0
T3	3473424	876153	0	0
T4	653628	333875	0	0
T5	2292	1940	0	0
T6	465952	350503	0	0
T10	3412	3104	0	0
T16	9352	7816	0	0
T17	17540	9820	0	0
T18	113400	90467	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2478	0	0
T1	314396	6	0	0
T2	95608	2	0	0
T3	3473424	5	0	0
T4	653628	2	0	0
T5	165820	0	0	0
T6	465952	2	0	0
T7	0	1	0	0
T10	500344	0	0	0
T12	0	6	0	0
T13	0	3	0	0
T14	0	1	0	0
T16	9352	0	0	0
T17	17540	2	0	0
T18	113400	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T31	0	6	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2431	0	0
T1	314396	6	0	0
T2	95608	2	0	0
T3	3473424	3	0	0
T4	653628	2	0	0
T5	165820	0	0	0
T6	465952	2	0	0
T7	0	1	0	0
T10	500344	0	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	1	0	0
T16	9352	0	0	0
T17	17540	2	0	0
T18	113400	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T31	0	6	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2379	0	0
T1	314396	6	0	0
T2	95608	2	0	0
T3	3473424	3	0	0
T4	653628	2	0	0
T5	165820	0	0	0
T6	465952	2	0	0
T9	0	1	0	0
T10	500344	0	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	1	0	0
T16	9352	0	0	0
T17	17540	2	0	0
T18	113400	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T31	0	6	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2325	0	0
T1	314396	5	0	0
T2	95608	2	0	0
T3	3473424	3	0	0
T4	653628	2	0	0
T5	165820	0	0	0
T6	465952	2	0	0
T9	0	1	0	0
T10	500344	0	0	0
T12	0	4	0	0
T13	0	3	0	0
T14	0	1	0	0
T16	9352	0	0	0
T17	17540	2	0	0
T18	113400	1	0	0
T19	0	5	0	0
T20	0	1	0	0
T22	0	3	0	0
T23	0	1	0	0
T24	0	1	0	0
T31	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3201	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	82910	0	0	0
T6	232976	0	0	0
T9	109752	0	0	0
T10	250172	0	0	0
T13	137686	2	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T16	4676	1	0	0
T17	8770	0	0	0
T18	56700	0	0	0
T19	15653	0	0	0
T21	61364	1	0	0
T22	0	1	0	0
T23	17526	6	0	0
T24	93764	10	0	0
T25	0	6	0	0
T26	0	14	0	0
T32	0	3	0	0
T33	0	17	0	0
T41	0	1	0	0
T42	0	1	0	0
T58	97068	0	0	0
T60	0	2	0	0
T63	0	7	0	0
T66	0	1	0	0
T70	23412	2	0	0
T71	21952	2	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	413639	0	0
T1	78599	162	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	82910	0	0	0
T6	232976	0	0	0
T9	109752	0	0	0
T10	250172	0	0	0
T13	137686	57	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T16	4676	61	0	0
T17	8770	0	0	0
T18	56700	0	0	0
T19	15653	0	0	0
T21	61364	222	0	0
T22	0	174	0	0
T23	17526	628	0	0
T24	93764	2459	0	0
T25	0	932	0	0
T26	0	2530	0	0
T32	0	434	0	0
T33	0	1030	0	0
T41	0	30	0	0
T42	0	1	0	0
T58	97068	0	0	0
T60	0	44	0	0
T63	0	1202	0	0
T66	0	4	0	0
T70	23412	236	0	0
T71	21952	300	0	0
T73	0	452	0	0
T74	0	277	0	0
T75	0	779	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2875	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	82910	0	0	0
T6	232976	0	0	0
T9	109752	0	0	0
T10	250172	0	0	0
T13	137686	1	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T16	4676	1	0	0
T17	8770	0	0	0
T18	56700	0	0	0
T19	15653	0	0	0
T21	61364	1	0	0
T22	0	1	0	0
T23	17526	5	0	0
T24	93764	4	0	0
T25	0	4	0	0
T26	0	13	0	0
T30	0	4	0	0
T32	0	3	0	0
T33	0	30	0	0
T41	0	1	0	0
T58	97068	0	0	0
T60	0	1	0	0
T63	0	7	0	0
T70	23412	2	0	0
T71	21952	2	0	0
T73	0	2	0	0
T74	0	4	0	0
T76	0	1	0	0
T77	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	206	0	0
T9	219504	0	0	0
T14	226870	0	0	0
T15	1925230	0	0	0
T21	122728	0	0	0
T23	17526	1	0	0
T24	187528	4	0	0
T25	75199	2	0	0
T26	0	1	0	0
T29	232525	2	0	0
T30	947184	0	0	0
T33	0	4	0	0
T42	131632	0	0	0
T44	0	1	0	0
T46	0	5	0	0
T49	0	2	0	0
T58	194136	0	0	0
T59	13960	0	0	0
T60	17526	1	0	0
T61	21526	0	0	0
T74	27366	0	0	0
T75	0	2	0	0
T77	0	3	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	4	0	0
T81	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	917216	0	0	0
T88	449208	0	0	0
T89	7442	0	0	0
T90	8591	0	0	0
T91	38174	0	0	0
T92	41931	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6351	0	0
T5	165820	1434	0	0
T6	465952	0	0	0
T10	500344	1472	0	0
T11	0	1335	0	0
T12	1167872	0	0	0
T18	113400	0	0	0
T19	62612	0	0	0
T20	168628	0	0	0
T22	102332	0	0	0
T34	0	1403	0	0
T35	0	707	0	0
T36	963028	0	0	0
T37	4648	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5271	0	0
T5	165820	1194	0	0
T6	465952	0	0	0
T10	500344	1232	0	0
T11	0	1095	0	0
T12	1167872	0	0	0
T18	113400	0	0	0
T19	62612	0	0	0
T20	168628	0	0	0
T22	102332	0	0	0
T34	0	1163	0	0
T35	0	587	0	0
T36	963028	0	0	0
T37	4648	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	314396	314164	0	0
T2	95608	95316	0	0
T3	3473424	3473156	0	0
T4	653628	653592	0	0
T5	348	0	0	0
T6	465952	465924	0	0
T10	1384	1080	0	0
T16	9352	9032	0	0
T17	17540	17228	0	0
T18	113400	113080	0	0
T19	0	62304	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	314396	314164	0	0
T2	95608	95316	0	0
T3	3473424	3473156	0	0
T4	653628	653592	0	0
T5	165820	64028	0	0
T6	465952	465924	0	0
T10	500344	398928	0	0
T16	9352	9032	0	0
T17	17540	17228	0	0
T18	113400	113080	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T19
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T16,T31,T13
1	1	1	Covered	T23,T24,T25

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T25
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T42,T45

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T23,T24,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T42,T45

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T25
1	0	Not Covered
1	1	Covered	T24,T25,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T2,T4,T37

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T12,T31

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T19,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T3,T17

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T23,T24,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T23,T24,T25
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T15,T30,T88
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T12,T24,T15
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T24,T15
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T93,T80,T94
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T23,T24,T25
TimeoutSt->Phase0St	172	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T15,T79,T94
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T24,T15
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T24,T15
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T93,T80,T94
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	710213091	337	0	0
CheckAccumTrig0_A	710213091	479	0	0
CheckAccumTrig1_A	710213091	18	0	0
CheckClr_A	710213091	185	0	0
CheckEn_A	709862634	323056327	0	0
CheckPhase0_A	710213091	531	0	0
CheckPhase1_A	710213091	523	0	0
CheckPhase2_A	710213091	510	0	0
CheckPhase3_A	710213091	504	0	0
CheckTimeout0_A	710213091	710	0	0
CheckTimeoutSt1_A	710213091	119815	0	0
CheckTimeoutSt2_A	710213091	645	0	0
CheckTimeoutStTrig_A	710213091	47	0	0
ErrorStAllEscAsserted_A	710213091	1566	0	0
ErrorStIsTerminal_A	710213091	1296	0	0
EscStateOut_A	709861016	709792939	0	0
u_state_regs_A	710213091	710029849	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	337	0	0
T5	41455	68	0	0
T6	116488	0	0	0
T10	125086	67	0	0
T11	0	87	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	75	0	0
T35	0	40	0	0
T36	240757	0	0	0
T37	1162	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	479	0	0
T1	78599	2	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T12	0	2	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T37	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	18	0	0
T9	109752	0	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T24	93764	2	0	0
T25	75199	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	97068	0	0	0
T59	13960	0	0	0
T60	17526	0	0	0
T61	21526	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	185	0	0
T1	78599	1	0	0
T2	23902	1	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	0	6	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T24	0	5	0	0
T26	0	1	0	0
T31	0	2	0	0
T32	0	3	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709862634	323056327	0	0
T1	78599	2707	0	0
T2	23902	3047	0	0
T3	868356	3987	0	0
T4	163407	3839	0	0
T5	573	485	0	0
T6	116488	1613	0	0
T10	853	776	0	0
T16	2338	1649	0	0
T17	4385	606	0	0
T18	28350	28269	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	531	0	0
T1	78599	2	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T12	0	2	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T37	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	523	0	0
T1	78599	2	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T12	0	1	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T37	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	510	0	0
T1	78599	2	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T12	0	1	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T37	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	504	0	0
T1	78599	2	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T12	0	1	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	1	0	0
T37	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	710	0	0
T9	109752	0	0	0
T13	137686	0	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T23	17526	2	0	0
T24	93764	10	0	0
T25	0	2	0	0
T26	0	7	0	0
T33	0	17	0	0
T41	0	1	0	0
T42	0	1	0	0
T58	97068	0	0	0
T63	0	7	0	0
T70	23412	0	0	0
T71	21952	0	0	0
T74	0	4	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	119815	0	0
T9	109752	0	0	0
T13	137686	0	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T23	17526	236	0	0
T24	93764	2459	0	0
T25	0	244	0	0
T26	0	1222	0	0
T33	0	1030	0	0
T41	0	30	0	0
T42	0	1	0	0
T58	97068	0	0	0
T63	0	1202	0	0
T70	23412	0	0	0
T71	21952	0	0	0
T74	0	277	0	0
T75	0	779	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	645	0	0
T9	109752	0	0	0
T13	137686	0	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T23	17526	2	0	0
T24	93764	4	0	0
T25	0	1	0	0
T26	0	6	0	0
T33	0	16	0	0
T41	0	1	0	0
T58	97068	0	0	0
T63	0	7	0	0
T70	23412	0	0	0
T71	21952	0	0	0
T74	0	4	0	0
T76	0	1	0	0
T77	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	47	0	0
T9	109752	0	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T24	93764	4	0	0
T25	75199	1	0	0
T26	0	1	0	0
T33	0	1	0	0
T46	0	2	0	0
T58	97068	0	0	0
T59	13960	0	0	0
T60	17526	0	0	0
T61	21526	0	0	0
T75	0	1	0	0
T77	0	2	0	0
T79	0	1	0	0
T80	0	2	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1566	0	0
T5	41455	328	0	0
T6	116488	0	0	0
T10	125086	390	0	0
T11	0	338	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	352	0	0
T35	0	158	0	0
T36	240757	0	0	0
T37	1162	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1296	0	0
T5	41455	268	0	0
T6	116488	0	0	0
T10	125086	330	0	0
T11	0	278	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	292	0	0
T35	0	128	0	0
T36	240757	0	0	0
T37	1162	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709861016	709792939	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	87	0	0	0
T6	116488	116481	0	0
T10	346	270	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0
T19	0	15576	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	710029849	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	41455	16007	0	0
T6	116488	116481	0	0
T10	125086	99732	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T20
1	0	1	Covered	T6,T95,T38
1	1	0	Covered	T16,T19,T22
1	1	1	Covered	T1,T23,T70

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T70
0	1	Covered	T29,T33,T80
1	0	Covered	T26,T41,T29

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T23,T70
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T41,T29

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T70
1	0	Covered	T25
1	1	Covered	T29,T33,T80

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T32,T73,T26

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T3,T19,T36

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T6,T18
1	Covered	T1,T17,T31

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T19
1	Covered	T3,T6,T18

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T17,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T3,T19,T36

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T3,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T3,T6,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T1,T23,T70

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T17
IdleSt->TimeoutSt	159	Covered	T1,T23,T70
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T88,T96
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T32,T97
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T41,T29
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T32,T29
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T6,T19,T38
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T23,T70
TimeoutSt->Phase0St	172	Covered	T26,T41,T29

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T70
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T41,T29
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T70
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T70
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T96,T44
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T32,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T41,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T32,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T19,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	710213091	282	0	0
CheckAccumTrig0_A	710213091	802	0	0
CheckAccumTrig1_A	710213091	49	0	0
CheckClr_A	710213091	429	0	0
CheckEn_A	709862634	271929342	0	0
CheckPhase0_A	710213091	898	0	0
CheckPhase1_A	710213091	879	0	0
CheckPhase2_A	710213091	857	0	0
CheckPhase3_A	710213091	829	0	0
CheckTimeout0_A	710213091	1158	0	0
CheckTimeoutSt1_A	710213091	140727	0	0
CheckTimeoutSt2_A	710213091	1048	0	0
CheckTimeoutStTrig_A	710213091	61	0	0
ErrorStAllEscAsserted_A	710213091	1574	0	0
ErrorStIsTerminal_A	710213091	1304	0	0
EscStateOut_A	709861016	709792939	0	0
u_state_regs_A	710213091	710029849	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	282	0	0
T5	41455	68	0	0
T6	116488	0	0	0
T10	125086	83	0	0
T11	0	38	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	64	0	0
T35	0	29	0	0
T36	240757	0	0	0
T37	1162	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	802	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	2	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	5	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	49	0	0
T26	666706	1	0	0
T29	0	1	0	0
T41	813175	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T62	27450	0	0	0
T63	88987	0	0	0
T64	38490	0	0	0
T65	6273	0	0	0
T66	44522	0	0	0
T67	157188	0	0	0
T68	18992	0	0	0
T69	21196	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	429	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T9	0	1	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	15653	1	0	0
T20	42157	0	0	0
T31	0	4	0	0
T38	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709862634	271929342	0	0
T1	78599	13567	0	0
T2	23902	23828	0	0
T3	868356	1431	0	0
T4	163407	163398	0	0
T5	573	485	0	0
T6	116488	115928	0	0
T10	853	776	0	0
T16	2338	2257	0	0
T17	4385	602	0	0
T18	28350	5660	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	898	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	2	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	5	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	879	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	5	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	857	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	5	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	829	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	1	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	1	0	0
T18	28350	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T31	0	4	0	0
T36	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1158	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T21	0	1	0	0
T23	0	3	0	0
T25	0	2	0	0
T32	0	1	0	0
T60	0	1	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	140727	0	0
T1	78599	162	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	56	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T21	0	222	0	0
T23	0	327	0	0
T25	0	389	0	0
T32	0	223	0	0
T60	0	15	0	0
T70	0	236	0	0
T71	0	300	0	0
T73	0	452	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1048	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T21	0	1	0	0
T23	0	3	0	0
T25	0	2	0	0
T32	0	1	0	0
T60	0	1	0	0
T70	0	2	0	0
T71	0	2	0	0
T73	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	61	0	0
T29	232525	2	0	0
T30	947184	0	0	0
T33	0	2	0	0
T42	131632	0	0	0
T44	0	1	0	0
T46	0	3	0	0
T49	0	2	0	0
T74	27366	0	0	0
T77	0	1	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T85	0	1	0	0
T87	917216	0	0	0
T88	449208	0	0	0
T89	7442	0	0	0
T90	8591	0	0	0
T91	38174	0	0	0
T92	41931	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1574	0	0
T5	41455	359	0	0
T6	116488	0	0	0
T10	125086	348	0	0
T11	0	318	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	366	0	0
T35	0	183	0	0
T36	240757	0	0	0
T37	1162	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1304	0	0
T5	41455	299	0	0
T6	116488	0	0	0
T10	125086	288	0	0
T11	0	258	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	306	0	0
T35	0	153	0	0
T36	240757	0	0	0
T37	1162	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709861016	709792939	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	87	0	0	0
T6	116488	116481	0	0
T10	346	270	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0
T19	0	15576	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	710029849	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	41455	16007	0	0
T6	116488	116481	0	0
T10	125086	99732	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T19,T22
1	0	1	Covered	T3,T4,T36
1	1	0	Covered	T16,T19,T12
1	1	1	Covered	T16,T22,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T16,T22,T23
0	1	Covered	T23,T25,T60
1	0	Covered	T13,T66,T98

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T16,T22,T23
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T66,T98

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T23
1	0	Covered	T27
1	1	Covered	T23,T25,T60

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T3,T19,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T40,T32

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T19,T12
1	Covered	T1,T2,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T39,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T3,T19,T38

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T3,T38,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T16,T22,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T16,T22,T23
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T88,T33,T77
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T99,T100
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T77,T99,T48
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T101,T102
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T19,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T16,T22,T25
TimeoutSt->Phase0St	172	Covered	T23,T13,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T13,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T23
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T22,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T33,T77,T44
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T99,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T77,T99,T48
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T101,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T19,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	710213091	355	0	0
CheckAccumTrig0_A	710213091	465	0	0
CheckAccumTrig1_A	710213091	25	0	0
CheckClr_A	710213091	191	0	0
CheckEn_A	709862634	309777568	0	0
CheckPhase0_A	710213091	531	0	0
CheckPhase1_A	710213091	522	0	0
CheckPhase2_A	710213091	513	0	0
CheckPhase3_A	710213091	507	0	0
CheckTimeout0_A	710213091	679	0	0
CheckTimeoutSt1_A	710213091	86334	0	0
CheckTimeoutSt2_A	710213091	605	0	0
CheckTimeoutStTrig_A	710213091	49	0	0
ErrorStAllEscAsserted_A	710213091	1664	0	0
ErrorStIsTerminal_A	710213091	1394	0	0
EscStateOut_A	709861016	709792939	0	0
u_state_regs_A	710213091	710029849	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	355	0	0
T5	41455	63	0	0
T6	116488	0	0	0
T10	125086	80	0	0
T11	0	90	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	82	0	0
T35	0	40	0	0
T36	240757	0	0	0
T37	1162	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	465	0	0
T1	78599	1	0	0
T2	23902	1	0	0
T3	868356	2	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	25	0	0
T9	109752	0	0	0
T13	137686	1	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T24	93764	0	0	0
T25	75199	0	0	0
T49	0	1	0	0
T53	0	2	0	0
T58	97068	0	0	0
T59	13960	0	0	0
T60	17526	0	0	0
T66	0	1	0	0
T98	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	191	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	15653	1	0	0
T26	0	3	0	0
T30	0	1	0	0
T33	0	12	0	0
T38	0	1	0	0
T66	0	1	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709862634	309777568	0	0
T1	78599	8308	0	0
T2	23902	3068	0	0
T3	868356	2447	0	0
T4	163407	162791	0	0
T5	573	485	0	0
T6	116488	116481	0	0
T10	853	776	0	0
T16	2338	1653	0	0
T17	4385	4306	0	0
T18	28350	28269	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	531	0	0
T1	78599	1	0	0
T2	23902	1	0	0
T3	868356	2	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	2	0	0
T23	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	522	0	0
T1	78599	1	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	2	0	0
T23	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	513	0	0
T1	78599	1	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	2	0	0
T23	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	507	0	0
T1	78599	1	0	0
T2	23902	1	0	0
T3	868356	1	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	2	0	0
T23	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	679	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	1	0	0
T16	2338	1	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	1	0	0
T23	0	1	0	0
T25	0	2	0	0
T26	0	7	0	0
T30	0	4	0	0
T32	0	2	0	0
T36	240757	0	0	0
T60	0	1	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	86334	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	1	0	0
T16	2338	61	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	174	0	0
T23	0	65	0	0
T25	0	299	0	0
T26	0	1308	0	0
T30	0	1017	0	0
T32	0	211	0	0
T36	240757	0	0	0
T60	0	29	0	0
T66	0	4	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	605	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T16	2338	1	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	1	0	0
T25	0	1	0	0
T26	0	7	0	0
T30	0	4	0	0
T32	0	2	0	0
T33	0	14	0	0
T36	240757	0	0	0
T88	0	1	0	0
T92	0	1	0	0
T96	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	49	0	0
T9	109752	0	0	0
T13	137686	0	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T23	17526	1	0	0
T24	93764	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T58	97068	0	0	0
T60	0	1	0	0
T70	23412	0	0	0
T71	21952	0	0	0
T75	0	1	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1664	0	0
T5	41455	390	0	0
T6	116488	0	0	0
T10	125086	387	0	0
T11	0	343	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	343	0	0
T35	0	201	0	0
T36	240757	0	0	0
T37	1162	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1394	0	0
T5	41455	330	0	0
T6	116488	0	0	0
T10	125086	327	0	0
T11	0	283	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	283	0	0
T35	0	171	0	0
T36	240757	0	0	0
T37	1162	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709861016	709792939	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	87	0	0	0
T6	116488	116481	0	0
T10	346	270	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0
T19	0	15576	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	710029849	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	41455	16007	0	0
T6	116488	116481	0	0
T10	125086	99732	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T4,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T22,T31
1	0	1	Covered	T4,T12,T95
1	1	0	Covered	T1,T16,T22
1	1	1	Covered	T1,T23,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T13
0	1	Covered	T60,T26,T29
1	0	Covered	T13,T32,T108

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T23,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T13,T32,T108

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T13
1	0	Covered	T28
1	1	Covered	T60,T26,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T22,T24,T60

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T7,T38,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T7
1	Covered	T1,T4,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T19
1	Covered	T1,T38,T26

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T5,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T4,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T22,T38

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T4,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T11
1	0	Covered	T1,T4,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T19
Phase1St	198	Covered	T1,T4,T19
Phase2St	215	Covered	T1,T4,T19
Phase3St	233	Covered	T1,T4,T19
TerminalSt	249	Covered	T1,T4,T19
TimeoutSt	159	Covered	T1,T23,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T10,T11
IdleSt->Phase0St	152	Covered	T1,T4,T19
IdleSt->TimeoutSt	159	Covered	T1,T23,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T96,T109,T110
Phase0St->Phase1St	198	Covered	T1,T4,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T12,T73,T80
Phase1St->Phase2St	215	Covered	T1,T4,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T7,T73,T74
Phase2St->Phase3St	233	Covered	T1,T4,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T68,T33
Phase3St->TerminalSt	249	Covered	T1,T4,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T22,T12,T38
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T23,T25
TimeoutSt->Phase0St	172	Covered	T13,T60,T32

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T60,T32
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T23,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T96,T109,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T73,T80
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T73,T74
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T68,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T22,T12,T38
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	710213091	348	0	0
CheckAccumTrig0_A	710213091	450	0	0
CheckAccumTrig1_A	710213091	27	0	0
CheckClr_A	710213091	196	0	0
CheckEn_A	709862634	333651587	0	0
CheckPhase0_A	710213091	518	0	0
CheckPhase1_A	710213091	507	0	0
CheckPhase2_A	710213091	499	0	0
CheckPhase3_A	710213091	485	0	0
CheckTimeout0_A	710213091	654	0	0
CheckTimeoutSt1_A	710213091	66763	0	0
CheckTimeoutSt2_A	710213091	577	0	0
CheckTimeoutStTrig_A	710213091	49	0	0
ErrorStAllEscAsserted_A	710213091	1547	0	0
ErrorStIsTerminal_A	710213091	1277	0	0
EscStateOut_A	709861016	709792939	0	0
u_state_regs_A	710213091	710029849	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	348	0	0
T5	41455	79	0	0
T6	116488	0	0	0
T10	125086	104	0	0
T11	0	69	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	75	0	0
T35	0	21	0	0
T36	240757	0	0	0
T37	1162	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	450	0	0
T1	78599	2	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	125086	0	0	0
T12	0	3	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	0	1	0	0
T31	0	1	0	0
T38	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	27	0	0
T9	109752	0	0	0
T13	137686	1	0	0
T14	113435	0	0	0
T15	962615	0	0	0
T21	61364	0	0	0
T24	93764	0	0	0
T25	75199	0	0	0
T32	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T58	97068	0	0	0
T59	13960	0	0	0
T60	17526	0	0	0
T74	0	1	0	0
T77	0	1	0	0
T98	0	1	0	0
T108	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	196	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T7	0	1	0	0
T10	125086	0	0	0
T12	0	2	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T22	0	2	0	0
T26	0	4	0	0
T38	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T73	0	5	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709862634	333651587	0	0
T1	78599	18724	0	0
T2	23902	23828	0	0
T3	868356	868288	0	0
T4	163407	3847	0	0
T5	573	485	0	0
T6	116488	116481	0	0
T10	853	776	0	0
T16	2338	2257	0	0
T17	4385	4306	0	0
T18	28350	28269	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	518	0	0
T1	78599	2	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T7	0	1	0	0
T10	125086	0	0	0
T12	0	3	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	0	1	0	0
T31	0	1	0	0
T38	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	507	0	0
T1	78599	2	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T7	0	1	0	0
T10	125086	0	0	0
T12	0	2	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	0	1	0	0
T31	0	1	0	0
T38	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	499	0	0
T1	78599	2	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T9	0	1	0	0
T10	125086	0	0	0
T12	0	2	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	0	1	0	0
T31	0	1	0	0
T38	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	485	0	0
T1	78599	1	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	1	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T9	0	1	0	0
T10	125086	0	0	0
T12	0	2	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	0	1	0	0
T31	0	1	0	0
T38	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	654	0	0
T1	78599	5	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	1	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T23	0	2	0	0
T25	0	1	0	0
T26	0	4	0	0
T32	0	1	0	0
T60	0	1	0	0
T63	0	6	0	0
T108	0	1	0	0
T111	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	66763	0	0
T1	78599	464	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T13	0	4	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T23	0	224	0	0
T25	0	198	0	0
T26	0	335	0	0
T29	0	804	0	0
T60	0	361	0	0
T63	0	1020	0	0
T108	0	2	0	0
T111	0	197	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	577	0	0
T1	78599	5	0	0
T2	23902	0	0	0
T3	868356	0	0	0
T4	163407	0	0	0
T5	41455	0	0	0
T6	116488	0	0	0
T10	125086	0	0	0
T16	2338	0	0	0
T17	4385	0	0	0
T18	28350	0	0	0
T23	0	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T30	0	3	0	0
T33	0	5	0	0
T63	0	6	0	0
T74	0	1	0	0
T78	0	2	0	0
T111	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	49	0	0
T26	666706	3	0	0
T29	0	1	0	0
T32	471861	0	0	0
T33	0	1	0	0
T40	179334	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T60	17526	1	0	0
T61	21526	0	0	0
T62	27450	0	0	0
T63	88987	0	0	0
T64	38490	0	0	0
T73	412393	0	0	0
T80	0	2	0	0
T92	0	1	0	0
T100	0	1	0	0
T112	120102	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1547	0	0
T5	41455	357	0	0
T6	116488	0	0	0
T10	125086	347	0	0
T11	0	336	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	342	0	0
T35	0	165	0	0
T36	240757	0	0	0
T37	1162	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	1277	0	0
T5	41455	297	0	0
T6	116488	0	0	0
T10	125086	287	0	0
T11	0	276	0	0
T12	291968	0	0	0
T18	28350	0	0	0
T19	15653	0	0	0
T20	42157	0	0	0
T22	25583	0	0	0
T34	0	282	0	0
T35	0	135	0	0
T36	240757	0	0	0
T37	1162	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	709861016	709792939	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	87	0	0	0
T6	116488	116481	0	0
T10	346	270	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0
T19	0	15576	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	710213091	710029849	0	0
T1	78599	78541	0	0
T2	23902	23829	0	0
T3	868356	868289	0	0
T4	163407	163398	0	0
T5	41455	16007	0	0
T6	116488	116481	0	0
T10	125086	99732	0	0
T16	2338	2258	0	0
T17	4385	4307	0	0
T18	28350	28270	0	0