Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T233,T234,T235
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13834	0	0
DisabledNoTrigBkwd_A	2147483647	868782	0	0
DisabledNoTrigFwd_A	2147483647	1460224134	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13834	0	0
T26	581446	0	0	0
T76	16471	0	0	0
T82	42834	0	0	0
T116	222428	0	0	0
T127	553541	0	0	0
T137	444484	0	0	0
T210	0	606	0	0
T223	58071	0	0	0
T229	66724	0	0	0
T233	1560	653	0	0
T234	1000	245	0	0
T235	2737	394	0	0
T236	0	725	0	0
T237	0	618	0	0
T238	0	473	0	0
T239	0	1074	0	0
T240	0	412	0	0
T241	0	1751	0	0
T242	4794	940	0	0
T243	0	717	0	0
T244	0	587	0	0
T245	0	1302	0	0
T246	0	487	0	0
T247	0	562	0	0
T248	0	385	0	0
T249	0	339	0	0
T250	0	664	0	0
T251	0	900	0	0
T252	148786	0	0	0
T253	377491	0	0	0
T254	435824	0	0	0
T255	34160	0	0	0
T256	28618	0	0	0
T257	28998	0	0	0
T258	380494	0	0	0
T259	810703	0	0	0
T260	468482	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	868782	0	0
T1	796412	1096	0	0
T2	1439108	702	0	0
T3	397256	0	0	0
T4	525156	6192	0	0
T5	519156	0	0	0
T6	118596	0	0	0
T7	0	36	0	0
T8	0	441	0	0
T9	0	2	0	0
T10	0	2	0	0
T15	0	95	0	0
T17	0	3457	0	0
T18	0	801	0	0
T19	176896	2	0	0
T20	660232	1102	0	0
T21	64900	0	0	0
T22	396508	0	0	0
T46	0	62	0	0
T47	0	9	0	0
T48	0	1	0	0
T49	0	350	0	0
T50	0	106	0	0
T51	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1460224134	0	0
T1	796412	606353	0	0
T2	1439108	714563	0	0
T3	397256	396912	0	0
T4	525156	723266	0	0
T5	519156	8926	0	0
T6	118596	62800	0	0
T19	176896	137756	0	0
T20	660232	571575	0	0
T21	64900	50525	0	0
T22	396508	300193	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T233,T238,T240
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	690202553	2025	0	0
DisabledNoTrigBkwd_A	690202553	225567	0	0
DisabledNoTrigFwd_A	690202553	348791182	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	2025	0	0
T26	581446	0	0	0
T76	16471	0	0	0
T82	42834	0	0	0
T127	553541	0	0	0
T137	444484	0	0	0
T223	58071	0	0	0
T229	66724	0	0	0
T233	1560	653	0	0
T234	1000	0	0	0
T238	0	473	0	0
T240	0	412	0	0
T246	0	487	0	0
T252	148786	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	225567	0	0
T1	199103	1083	0	0
T2	359777	401	0	0
T3	99314	0	0	0
T4	131289	73	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	2	0	0
T9	0	2	0	0
T15	0	38	0	0
T19	44224	2	0	0
T20	165058	329	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T46	0	62	0	0
T48	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	348791182	0	0
T1	199103	13476	0	0
T2	359777	38641	0	0
T3	99314	99228	0	0
T4	131289	123347	0	0
T5	129789	2209	0	0
T6	29649	3384	0	0
T19	44224	5360	0	0
T20	165058	134440	0	0
T21	16225	2072	0	0
T22	99127	3013	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T242,T243,T248
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	690202553	3045	0	0
DisabledNoTrigBkwd_A	690202553	217936	0	0
DisabledNoTrigFwd_A	690202553	355339044	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	3045	0	0
T116	222428	0	0	0
T242	4794	940	0	0
T243	0	717	0	0
T248	0	385	0	0
T249	0	339	0	0
T250	0	664	0	0
T253	377491	0	0	0
T254	435824	0	0	0
T255	34160	0	0	0
T256	28618	0	0	0
T257	28998	0	0	0
T258	380494	0	0	0
T259	810703	0	0	0
T260	468482	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	217936	0	0
T1	199103	3	0	0
T2	359777	235	0	0
T3	99314	0	0	0
T4	131289	1495	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	32	0	0
T17	0	1527	0	0
T18	0	2	0	0
T19	44224	0	0	0
T20	165058	352	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	4	0	0
T49	0	25	0	0
T51	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	355339044	0	0
T1	199103	198066	0	0
T2	359777	31280	0	0
T3	99314	99228	0	0
T4	131289	203954	0	0
T5	129789	2225	0	0
T6	29649	28122	0	0
T19	44224	44132	0	0
T20	165058	152380	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T235,T237,T251
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	690202553	1912	0	0
DisabledNoTrigBkwd_A	690202553	194972	0	0
DisabledNoTrigFwd_A	690202553	404909533	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1912	0	0
T53	378464	0	0	0
T54	292761	0	0	0
T86	56366	0	0	0
T235	2737	394	0	0
T237	0	618	0	0
T251	0	900	0	0
T261	35804	0	0	0
T262	22263	0	0	0
T263	270430	0	0	0
T264	79164	0	0	0
T265	986681	0	0	0
T266	710664	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	194972	0	0
T1	199103	8	0	0
T2	359777	37	0	0
T3	99314	0	0	0
T4	131289	3434	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	34	0	0
T10	0	2	0	0
T15	0	1	0	0
T19	44224	0	0	0
T20	165058	235	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	5	0	0
T49	0	314	0	0
T50	0	104	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	404909533	0	0
T1	199103	196291	0	0
T2	359777	316622	0	0
T3	99314	99228	0	0
T4	131289	198799	0	0
T5	129789	2239	0	0
T6	29649	27898	0	0
T19	44224	44132	0	0
T20	165058	148226	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T234,T210,T236
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	690202553	6852	0	0
DisabledNoTrigBkwd_A	690202553	230307	0	0
DisabledNoTrigFwd_A	690202553	351184375	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	6852	0	0
T26	581446	0	0	0
T77	94235	0	0	0
T82	42834	0	0	0
T127	553541	0	0	0
T137	444484	0	0	0
T210	0	606	0	0
T223	58071	0	0	0
T229	66724	0	0	0
T234	1000	245	0	0
T236	0	725	0	0
T239	0	1074	0	0
T241	0	1751	0	0
T244	0	587	0	0
T245	0	1302	0	0
T247	0	562	0	0
T252	148786	0	0	0
T267	23725	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	230307	0	0
T1	199103	2	0	0
T2	359777	29	0	0
T3	99314	0	0	0
T4	131289	1190	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T8	0	441	0	0
T15	0	24	0	0
T17	0	1930	0	0
T18	0	799	0	0
T19	44224	0	0	0
T20	165058	186	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T49	0	11	0	0
T50	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	351184375	0	0
T1	199103	198520	0	0
T2	359777	328020	0	0
T3	99314	99228	0	0
T4	131289	197166	0	0
T5	129789	2253	0	0
T6	29649	3396	0	0
T19	44224	44132	0	0
T20	165058	136529	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0