Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Not Covered
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T6,T4,T22
1	0	Covered	T4,T17,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T17,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T25
1	1	Covered	T6,T4,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T4,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T6
Phase1St	198	Covered	T1,T2,T6
Phase2St	215	Covered	T1,T2,T6
Phase3St	233	Covered	T1,T2,T6
TerminalSt	249	Covered	T1,T2,T6
TimeoutSt	159	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T2,T6
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T26,T27,T28
Phase0St->Phase1St	198	Covered	T1,T2,T6
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T29,T30
Phase1St->Phase2St	215	Covered	T1,T2,T6
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T20,T31,T32
Phase2St->Phase3St	233	Covered	T1,T2,T6
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T33,T34
Phase3St->TerminalSt	249	Covered	T1,T2,T6
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T6
TimeoutSt->Phase0St	172	Covered	T6,T4,T22

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T29,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T33,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1127	0	0
CheckAccumTrig0_A	2147483647	2358	0	0
CheckAccumTrig1_A	2147483647	120	0	0
CheckClr_A	2147483647	1082	0	0
CheckEn_A	2147483647	1112215274	0	0
CheckPhase0_A	2147483647	2656	0	0
CheckPhase1_A	2147483647	2606	0	0
CheckPhase2_A	2147483647	2553	0	0
CheckPhase3_A	2147483647	2504	0	0
CheckTimeout0_A	2147483647	4263	0	0
CheckTimeoutSt1_A	2147483647	509888	0	0
CheckTimeoutSt2_A	2147483647	3921	0	0
CheckTimeoutStTrig_A	2147483647	219	0	0
ErrorStAllEscAsserted_A	2147483647	5776	0	0
ErrorStIsTerminal_A	2147483647	4816	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1127	0	0
T12	263264	131	0	0
T13	0	244	0	0
T14	0	318	0	0
T35	0	143	0	0
T36	0	291	0	0
T37	322920	0	0	0
T38	1548648	0	0	0
T39	637384	0	0	0
T40	1994412	0	0	0
T41	1091876	0	0	0
T42	263788	0	0	0
T43	2986240	0	0	0
T44	286408	0	0	0
T45	422812	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2358	0	0
T1	796412	6	0	0
T2	1439108	12	0	0
T3	397256	0	0	0
T4	525156	15	0	0
T5	519156	0	0	0
T6	118596	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T15	0	5	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	176896	1	0	0
T20	660232	25	0	0
T21	64900	0	0	0
T22	396508	0	0	0
T46	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120	0	0
T4	131289	1	0	0
T5	129789	0	0	0
T11	125330	0	0	0
T17	610618	1	0	0
T18	674265	0	0	0
T19	44224	0	0	0
T20	165058	0	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T23	0	4	0	0
T24	0	1	0	0
T34	0	1	0	0
T41	0	1	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T48	1781	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	26347	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	38514	0	0	0
T68	5066	0	0	0
T69	5853	0	0	0
T70	23932	0	0	0
T71	1353	0	0	0
T72	44916	0	0	0
T73	70229	0	0	0
T74	81716	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1082	0	0
T1	597309	3	0	0
T2	1079331	3	0	0
T3	297942	0	0	0
T4	525156	6	0	0
T5	519156	0	0	0
T6	88947	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	176896	0	0	0
T20	660232	5	0	0
T21	64900	0	0	0
T22	396508	0	0	0
T29	0	2	0	0
T30	0	2	0	0
T46	94968	7	0	0
T47	47190	1	0	0
T48	1781	0	0	0
T49	0	2	0	0
T67	38514	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	6	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1112215274	0	0
T1	796412	411630	0	0
T2	1439108	685656	0	0
T3	397256	396908	0	0
T4	525156	719495	0	0
T5	519156	8922	0	0
T6	118596	62798	0	0
T19	176896	134365	0	0
T20	660232	568243	0	0
T21	64900	50522	0	0
T22	396508	300190	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2656	0	0
T1	796412	6	0	0
T2	1439108	12	0	0
T3	397256	0	0	0
T4	525156	17	0	0
T5	519156	0	0	0
T6	118596	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	1	0	0
T15	0	4	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	176896	1	0	0
T20	660232	25	0	0
T21	64900	0	0	0
T22	396508	1	0	0
T46	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T1	796412	6	0	0
T2	1439108	12	0	0
T3	397256	0	0	0
T4	525156	16	0	0
T5	519156	0	0	0
T6	118596	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	1	0	0
T15	0	4	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	176896	1	0	0
T20	660232	25	0	0
T21	64900	0	0	0
T22	396508	1	0	0
T46	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2553	0	0
T1	796412	6	0	0
T2	1439108	12	0	0
T3	397256	0	0	0
T4	525156	16	0	0
T5	519156	0	0	0
T6	118596	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	1	0	0
T15	0	4	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	176896	1	0	0
T20	660232	24	0	0
T21	64900	0	0	0
T22	396508	1	0	0
T46	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2504	0	0
T1	796412	5	0	0
T2	1439108	12	0	0
T3	397256	0	0	0
T4	525156	16	0	0
T5	519156	0	0	0
T6	118596	1	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	1	0	0
T15	0	4	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	176896	1	0	0
T20	660232	24	0	0
T21	64900	0	0	0
T22	396508	1	0	0
T46	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4263	0	0
T1	199103	1	0	0
T2	1079331	13	0	0
T3	297942	0	0	0
T4	525156	15	0	0
T5	519156	0	0	0
T6	118596	8	0	0
T7	0	2	0	0
T16	0	1	0	0
T17	0	6	0	0
T19	176896	0	0	0
T20	660232	20	0	0
T21	64900	1	0	0
T22	396508	1	0	0
T26	0	19	0	0
T29	0	1	0	0
T30	0	7	0	0
T46	284904	0	0	0
T47	47190	0	0	0
T49	0	4	0	0
T67	38514	0	0	0
T71	0	1	0	0
T76	0	5	0	0
T79	0	6	0	0
T81	0	4	0	0
T82	0	1	0	0
T83	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	509888	0	0
T1	199103	25	0	0
T2	1079331	825	0	0
T3	297942	0	0	0
T4	525156	874	0	0
T5	519156	0	0	0
T6	118596	1104	0	0
T7	0	258	0	0
T16	0	145	0	0
T17	0	750	0	0
T19	176896	0	0	0
T20	660232	2831	0	0
T21	64900	143	0	0
T22	396508	4	0	0
T26	0	4123	0	0
T29	0	926	0	0
T30	0	590	0	0
T46	284904	0	0	0
T47	47190	0	0	0
T49	0	868	0	0
T67	38514	0	0	0
T71	0	78	0	0
T76	0	1045	0	0
T79	0	855	0	0
T81	0	403	0	0
T82	0	211	0	0
T83	0	846	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3921	0	0
T1	199103	1	0	0
T2	1079331	13	0	0
T3	297942	0	0	0
T4	525156	13	0	0
T5	519156	0	0	0
T6	118596	7	0	0
T7	0	2	0	0
T16	0	1	0	0
T17	0	5	0	0
T19	176896	0	0	0
T20	660232	20	0	0
T21	64900	1	0	0
T22	396508	0	0	0
T26	0	21	0	0
T30	0	20	0	0
T46	284904	0	0	0
T47	47190	0	0	0
T49	0	2	0	0
T67	38514	0	0	0
T71	0	1	0	0
T76	0	4	0	0
T79	0	3	0	0
T81	0	4	0	0
T82	0	1	0	0
T83	0	11	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	219	0	0
T4	262578	1	0	0
T5	259578	0	0	0
T6	29649	1	0	0
T8	523739	0	0	0
T16	486092	0	0	0
T17	610618	0	0	0
T18	674265	0	0	0
T19	88448	0	0	0
T20	330116	0	0	0
T21	32450	0	0	0
T22	198254	1	0	0
T23	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T46	189936	0	0	0
T47	94380	0	0	0
T48	1781	0	0	0
T49	23258	2	0	0
T50	472642	0	0	0
T52	0	2	0	0
T54	0	1	0	0
T67	77028	0	0	0
T68	5066	0	0	0
T69	5853	0	0	0
T70	23932	0	0	0
T75	2395	0	0	0
T76	0	1	0	0
T79	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	6	0	0
T90	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5776	0	0
T12	263264	735	0	0
T13	0	1426	0	0
T14	0	1484	0	0
T35	0	710	0	0
T36	0	1421	0	0
T37	322920	0	0	0
T38	1548648	0	0	0
T39	637384	0	0	0
T40	1994412	0	0	0
T41	1091876	0	0	0
T42	263788	0	0	0
T43	2986240	0	0	0
T44	286408	0	0	0
T45	422812	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4816	0	0
T12	263264	615	0	0
T13	0	1186	0	0
T14	0	1244	0	0
T35	0	590	0	0
T36	0	1181	0	0
T37	322920	0	0	0
T38	1548648	0	0	0
T39	637384	0	0	0
T40	1994412	0	0	0
T41	1091876	0	0	0
T42	263788	0	0	0
T43	2986240	0	0	0
T44	286408	0	0	0
T45	422812	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	796412	796384	0	0
T2	1439108	1437060	0	0
T3	397256	396912	0	0
T4	525156	524860	0	0
T5	519156	518556	0	0
T6	118596	118244	0	0
T19	176896	176528	0	0
T20	660232	659912	0	0
T21	64900	64604	0	0
T22	396508	396240	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	796412	796384	0	0
T2	1439108	1437060	0	0
T3	397256	396912	0	0
T4	525156	524860	0	0
T5	519156	518556	0	0
T6	118596	118244	0	0
T19	176896	176528	0	0
T20	660232	659912	0	0
T21	64900	64604	0	0
T22	396508	396240	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T3,T6,T4
1	1	1	Covered	T2,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T20
0	1	Covered	T4,T49,T76
1	0	Covered	T55,T23,T61

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T4,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T55,T23,T61

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T20
1	0	Not Covered
1	1	Covered	T4,T49,T76

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T47,T7,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T20
1	Covered	T1,T20,T49

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T20,T10

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T20
1	Covered	T2,T4,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T20,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T4,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T2,T4,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T2,T4,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T89,T90
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T95,T94
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T96,T97
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T98,T52
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T4,T20
TimeoutSt->Phase0St	172	Covered	T4,T49,T76

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T49,T76
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T89,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T95,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T96,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T98,T52
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T47,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	690202553	283	0	0
CheckAccumTrig0_A	690202553	473	0	0
CheckAccumTrig1_A	690202553	18	0	0
CheckClr_A	690202553	201	0	0
CheckEn_A	689906150	318344347	0	0
CheckPhase0_A	690202553	539	0	0
CheckPhase1_A	690202553	527	0	0
CheckPhase2_A	690202553	524	0	0
CheckPhase3_A	690202553	512	0	0
CheckTimeout0_A	690202553	1513	0	0
CheckTimeoutSt1_A	690202553	177445	0	0
CheckTimeoutSt2_A	690202553	1444	0	0
CheckTimeoutStTrig_A	690202553	51	0	0
ErrorStAllEscAsserted_A	690202553	1460	0	0
ErrorStIsTerminal_A	690202553	1220	0	0
EscStateOut_A	689904891	689835172	0	0
u_state_regs_A	690202553	690030765	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	283	0	0
T12	65816	35	0	0
T13	0	51	0	0
T14	0	92	0	0
T35	0	35	0	0
T36	0	70	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	473	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T19	44224	0	0	0
T20	165058	4	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	18	0	0
T23	0	2	0	0
T55	26347	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T87	92769	0	0	0
T88	104431	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	2	0	0
T104	0	1	0	0
T105	107659	0	0	0
T106	274661	0	0	0
T107	17308	0	0	0
T108	25887	0	0	0
T109	166549	0	0	0
T110	6124	0	0	0
T111	61941	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	201	0	0
T4	131289	1	0	0
T5	129789	0	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	0	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T24	0	4	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T34	0	1	0	0
T46	94968	0	0	0
T47	47190	1	0	0
T48	1781	0	0	0
T67	38514	0	0	0
T79	0	2	0	0
T81	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689906150	318344347	0	0
T1	199103	2081	0	0
T2	359777	312810	0	0
T3	99314	99227	0	0
T4	131289	198793	0	0
T5	129789	2238	0	0
T6	29649	27897	0	0
T19	44224	44131	0	0
T20	165058	146838	0	0
T21	16225	16150	0	0
T22	99127	99059	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	539	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T15	0	1	0	0
T19	44224	0	0	0
T20	165058	4	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	527	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T15	0	1	0	0
T19	44224	0	0	0
T20	165058	4	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	524	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T15	0	1	0	0
T19	44224	0	0	0
T20	165058	4	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	512	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T15	0	1	0	0
T19	44224	0	0	0
T20	165058	4	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1513	0	0
T2	359777	4	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T16	0	1	0	0
T17	0	5	0	0
T19	44224	0	0	0
T20	165058	2	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	4	0	0
T46	94968	0	0	0
T49	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0
T81	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	177445	0	0
T2	359777	248	0	0
T3	99314	0	0	0
T4	131289	192	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T16	0	145	0	0
T17	0	750	0	0
T19	44224	0	0	0
T20	165058	517	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	864	0	0
T46	94968	0	0	0
T49	0	235	0	0
T76	0	590	0	0
T79	0	219	0	0
T81	0	403	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1444	0	0
T2	359777	4	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T16	0	1	0	0
T17	0	5	0	0
T19	44224	0	0	0
T20	165058	2	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	4	0	0
T30	0	7	0	0
T46	94968	0	0	0
T79	0	1	0	0
T81	0	4	0	0
T83	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	51	0	0
T4	131289	1	0	0
T5	129789	0	0	0
T19	44224	0	0	0
T20	165058	0	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T48	1781	0	0	0
T49	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T67	38514	0	0	0
T76	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1460	0	0
T12	65816	194	0	0
T13	0	342	0	0
T14	0	375	0	0
T35	0	183	0	0
T36	0	366	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1220	0	0
T12	65816	164	0	0
T13	0	282	0	0
T14	0	315	0	0
T35	0	153	0	0
T36	0	306	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689904891	689835172	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	690030765	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T6,T4
1	0	1	Covered	T2,T20,T67
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T6,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T20
0	1	Covered	T79,T30,T54
1	0	Covered	T30,T113,T99

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T6,T4,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T30,T113,T99

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T20
1	0	Not Covered
1	1	Covered	T79,T30,T54

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T20
1	Covered	T2,T20,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T20
1	Covered	T1,T4,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T15,T50,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T20,T73

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T20,T15,T49

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T20,T15,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T20,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T6,T4,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T6,T4,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T114,T115,T116
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T117,T29,T30
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T51,T109,T23
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T51,T30,T118
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T6,T4,T20
TimeoutSt->Phase0St	172	Covered	T79,T30,T113

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T79,T30,T113
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T114,T115,T116
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T117,T29,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T51,T109,T23
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T51,T30,T118
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	690202553	269	0	0
CheckAccumTrig0_A	690202553	543	0	0
CheckAccumTrig1_A	690202553	20	0	0
CheckClr_A	690202553	233	0	0
CheckEn_A	689906150	277580484	0	0
CheckPhase0_A	690202553	611	0	0
CheckPhase1_A	690202553	599	0	0
CheckPhase2_A	690202553	592	0	0
CheckPhase3_A	690202553	582	0	0
CheckTimeout0_A	690202553	814	0	0
CheckTimeoutSt1_A	690202553	106982	0	0
CheckTimeoutSt2_A	690202553	737	0	0
CheckTimeoutStTrig_A	690202553	56	0	0
ErrorStAllEscAsserted_A	690202553	1428	0	0
ErrorStIsTerminal_A	690202553	1188	0	0
EscStateOut_A	689904891	689835172	0	0
u_state_regs_A	690202553	690030765	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	269	0	0
T12	65816	26	0	0
T13	0	60	0	0
T14	0	78	0	0
T35	0	38	0	0
T36	0	67	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	543	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T8	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	20	0	0
T24	82338	0	0	0
T27	596575	0	0	0
T30	119672	2	0	0
T33	6781	0	0	0
T34	138956	0	0	0
T83	74903	0	0	0
T84	5865	0	0	0
T96	0	2	0	0
T99	0	1	0	0
T103	0	1	0	0
T113	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	3	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	678334	0	0	0
T125	24023	0	0	0
T126	489204	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	233	0	0
T1	199103	1	0	0
T2	359777	0	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	1	0	0
T19	44224	0	0	0
T20	165058	1	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	3	0	0
T51	0	4	0	0
T73	0	5	0	0
T76	0	2	0	0
T117	0	1	0	0
T127	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689906150	277580484	0	0
T1	199103	198264	0	0
T2	359777	317287	0	0
T3	99314	99227	0	0
T4	131289	196188	0	0
T5	129789	2252	0	0
T6	29649	3396	0	0
T19	44224	44131	0	0
T20	165058	136399	0	0
T21	16225	16150	0	0
T22	99127	99059	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	611	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T8	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	599	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T8	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	592	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T8	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	582	0	0
T1	199103	1	0	0
T2	359777	1	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T8	0	1	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	814	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	5	0	0
T7	0	1	0	0
T19	44224	0	0	0
T20	165058	3	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	14	0	0
T30	0	7	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T49	0	1	0	0
T67	38514	0	0	0
T76	0	1	0	0
T79	0	3	0	0
T83	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	106982	0	0
T4	131289	321	0	0
T5	129789	0	0	0
T6	29649	709	0	0
T7	0	182	0	0
T19	44224	0	0	0
T20	165058	941	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	3115	0	0
T30	0	218	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T49	0	440	0	0
T67	38514	0	0	0
T76	0	3	0	0
T79	0	171	0	0
T83	0	846	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	737	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	5	0	0
T7	0	1	0	0
T19	44224	0	0	0
T20	165058	3	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	14	0	0
T30	0	4	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T49	0	1	0	0
T67	38514	0	0	0
T76	0	1	0	0
T79	0	1	0	0
T83	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	56	0	0
T24	82338	0	0	0
T29	528337	0	0	0
T30	119672	1	0	0
T54	0	2	0	0
T59	0	1	0	0
T79	436938	2	0	0
T80	946399	0	0	0
T81	238247	0	0	0
T83	74903	0	0	0
T84	5865	0	0	0
T89	0	2	0	0
T94	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	12407	0	0	0
T133	493132	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1428	0	0
T12	65816	167	0	0
T13	0	374	0	0
T14	0	380	0	0
T35	0	159	0	0
T36	0	348	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1188	0	0
T12	65816	137	0	0
T13	0	314	0	0
T14	0	320	0	0
T35	0	129	0	0
T36	0	288	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689904891	689835172	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	690030765	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T2,T4,T20
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T6,T22,T29
1	0	Covered	T4,T24,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T24,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Not Covered
1	1	Covered	T6,T22,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T6,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T4,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T2,T4,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T2,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T6
Phase1St	198	Covered	T1,T2,T6
Phase2St	215	Covered	T1,T2,T6
Phase3St	233	Covered	T1,T2,T6
TerminalSt	249	Covered	T1,T2,T6
TimeoutSt	159	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T1,T2,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T26,T28,T134
Phase0St->Phase1St	198	Covered	T1,T2,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T30,T135
Phase1St->Phase2St	215	Covered	T1,T2,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T20,T136,T89
Phase2St->Phase3St	233	Covered	T1,T2,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T33,T110
Phase3St->TerminalSt	249	Covered	T1,T2,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T4,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T6
TimeoutSt->Phase0St	172	Covered	T6,T4,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T6,T4,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T28,T134
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T30,T135
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T20,T136,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T33,T110
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	690202553	274	0	0
CheckAccumTrig0_A	690202553	826	0	0
CheckAccumTrig1_A	690202553	50	0	0
CheckClr_A	690202553	419	0	0
CheckEn_A	689906150	262990694	0	0
CheckPhase0_A	690202553	916	0	0
CheckPhase1_A	690202553	896	0	0
CheckPhase2_A	690202553	868	0	0
CheckPhase3_A	690202553	848	0	0
CheckTimeout0_A	690202553	1281	0	0
CheckTimeoutSt1_A	690202553	152160	0	0
CheckTimeoutSt2_A	690202553	1170	0	0
CheckTimeoutStTrig_A	690202553	59	0	0
ErrorStAllEscAsserted_A	690202553	1455	0	0
ErrorStIsTerminal_A	690202553	1215	0	0
EscStateOut_A	689904891	689835172	0	0
u_state_regs_A	690202553	690030765	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	274	0	0
T12	65816	33	0	0
T13	0	55	0	0
T14	0	69	0	0
T35	0	28	0	0
T36	0	89	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	826	0	0
T1	199103	2	0	0
T2	359777	8	0	0
T3	99314	0	0	0
T4	131289	7	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T7	0	1	0	0
T9	0	1	0	0
T15	0	1	0	0
T19	44224	1	0	0
T20	165058	10	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T46	0	8	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	50	0	0
T4	131289	1	0	0
T5	129789	0	0	0
T19	44224	0	0	0
T20	165058	0	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T48	1781	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T60	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T67	38514	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	419	0	0
T1	199103	1	0	0
T2	359777	3	0	0
T3	99314	0	0	0
T4	131289	5	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	2	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T46	0	7	0	0
T68	0	1	0	0
T69	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689906150	262990694	0	0
T1	199103	13476	0	0
T2	359777	24281	0	0
T3	99314	99227	0	0
T4	131289	120567	0	0
T5	129789	2208	0	0
T6	29649	3384	0	0
T19	44224	1972	0	0
T20	165058	133611	0	0
T21	16225	2072	0	0
T22	99127	3013	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	916	0	0
T1	199103	2	0	0
T2	359777	8	0	0
T3	99314	0	0	0
T4	131289	8	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T7	0	1	0	0
T19	44224	1	0	0
T20	165058	10	0	0
T21	16225	0	0	0
T22	99127	1	0	0
T46	0	8	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	896	0	0
T1	199103	2	0	0
T2	359777	8	0	0
T3	99314	0	0	0
T4	131289	7	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T7	0	1	0	0
T19	44224	1	0	0
T20	165058	10	0	0
T21	16225	0	0	0
T22	99127	1	0	0
T46	0	8	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	868	0	0
T1	199103	2	0	0
T2	359777	8	0	0
T3	99314	0	0	0
T4	131289	7	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T7	0	1	0	0
T19	44224	1	0	0
T20	165058	9	0	0
T21	16225	0	0	0
T22	99127	1	0	0
T46	0	8	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	848	0	0
T1	199103	1	0	0
T2	359777	8	0	0
T3	99314	0	0	0
T4	131289	7	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T7	0	1	0	0
T19	44224	1	0	0
T20	165058	9	0	0
T21	16225	0	0	0
T22	99127	1	0	0
T46	0	8	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1281	0	0
T1	199103	1	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	4	0	0
T5	129789	0	0	0
T6	29649	2	0	0
T7	0	1	0	0
T19	44224	0	0	0
T20	165058	9	0	0
T21	16225	1	0	0
T22	99127	1	0	0
T76	0	3	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	152160	0	0
T1	199103	25	0	0
T2	359777	127	0	0
T3	99314	0	0	0
T4	131289	200	0	0
T5	129789	0	0	0
T6	29649	158	0	0
T7	0	76	0	0
T19	44224	0	0	0
T20	165058	567	0	0
T21	16225	143	0	0
T22	99127	4	0	0
T76	0	452	0	0
T82	0	211	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1170	0	0
T1	199103	1	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T7	0	1	0	0
T19	44224	0	0	0
T20	165058	9	0	0
T21	16225	1	0	0
T22	99127	0	0	0
T26	0	2	0	0
T76	0	3	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	59	0	0
T4	131289	0	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T19	44224	0	0	0
T20	165058	0	0	0
T21	16225	0	0	0
T22	99127	1	0	0
T29	0	1	0	0
T46	94968	0	0	0
T47	47190	0	0	0
T52	0	1	0	0
T67	38514	0	0	0
T88	0	1	0	0
T89	0	3	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1455	0	0
T12	65816	182	0	0
T13	0	347	0	0
T14	0	378	0	0
T35	0	188	0	0
T36	0	360	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1215	0	0
T12	65816	152	0	0
T13	0	287	0	0
T14	0	318	0	0
T35	0	158	0	0
T36	0	300	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689904891	689835172	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	690030765	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T6
1	0	1	Covered	T2,T4,T20
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T2,T6,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T4
0	1	Covered	T49,T79,T29
1	0	Covered	T17,T34,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T6,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T34,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T25
1	1	Covered	T49,T79,T29

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T20,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T20
1	Covered	T1,T2,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T47,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T20,T51,T137

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T4,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T4
Phase1St	198	Covered	T1,T2,T4
Phase2St	215	Covered	T1,T2,T4
Phase3St	233	Covered	T1,T2,T4
TerminalSt	249	Covered	T1,T2,T4
TimeoutSt	159	Covered	T2,T6,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T2,T4
IdleSt->TimeoutSt	159	Covered	T2,T6,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T134,T89,T63
Phase0St->Phase1St	198	Covered	T1,T2,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T136,T41,T138
Phase1St->Phase2St	215	Covered	T1,T2,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T89,T23
Phase2St->Phase3St	233	Covered	T1,T2,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T113,T136
Phase3St->TerminalSt	249	Covered	T1,T2,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T6,T4
TimeoutSt->Phase0St	172	Covered	T49,T17,T79

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T49,T17,T79
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T134,T89,T63
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T136,T41,T138
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T89,T23
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T113,T136
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T20,T49
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	690202553	301	0	0
CheckAccumTrig0_A	690202553	516	0	0
CheckAccumTrig1_A	690202553	32	0	0
CheckClr_A	690202553	229	0	0
CheckEn_A	689906150	253299749	0	0
CheckPhase0_A	690202553	590	0	0
CheckPhase1_A	690202553	584	0	0
CheckPhase2_A	690202553	569	0	0
CheckPhase3_A	690202553	562	0	0
CheckTimeout0_A	690202553	655	0	0
CheckTimeoutSt1_A	690202553	73301	0	0
CheckTimeoutSt2_A	690202553	570	0	0
CheckTimeoutStTrig_A	690202553	53	0	0
ErrorStAllEscAsserted_A	690202553	1433	0	0
ErrorStIsTerminal_A	690202553	1193	0	0
EscStateOut_A	689904891	689835172	0	0
u_state_regs_A	690202553	690030765	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	301	0	0
T12	65816	37	0	0
T13	0	78	0	0
T14	0	79	0	0
T35	0	42	0	0
T36	0	65	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	516	0	0
T1	199103	2	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	5	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	32	0	0
T11	125330	0	0	0
T17	610618	1	0	0
T18	674265	0	0	0
T23	0	1	0	0
T34	0	1	0	0
T41	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	5066	0	0	0
T69	5853	0	0	0
T70	23932	0	0	0
T71	1353	0	0	0
T72	44916	0	0	0
T73	70229	0	0	0
T74	81716	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	229	0	0
T1	199103	2	0	0
T2	359777	0	0	0
T3	99314	0	0	0
T4	131289	0	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T17	0	1	0	0
T19	44224	0	0	0
T20	165058	3	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T29	0	1	0	0
T49	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689906150	253299749	0	0
T1	199103	197809	0	0
T2	359777	31278	0	0
T3	99314	99227	0	0
T4	131289	203947	0	0
T5	129789	2224	0	0
T6	29649	28121	0	0
T19	44224	44131	0	0
T20	165058	151395	0	0
T21	16225	16150	0	0
T22	99127	99059	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	590	0	0
T1	199103	2	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	5	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	584	0	0
T1	199103	2	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	5	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	569	0	0
T1	199103	2	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	5	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	562	0	0
T1	199103	2	0	0
T2	359777	2	0	0
T3	99314	0	0	0
T4	131289	2	0	0
T5	129789	0	0	0
T6	29649	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	44224	0	0	0
T20	165058	5	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	655	0	0
T2	359777	7	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T17	0	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	1	0	0
T29	0	1	0	0
T46	94968	0	0	0
T49	0	2	0	0
T71	0	1	0	0
T79	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	73301	0	0
T2	359777	450	0	0
T3	99314	0	0	0
T4	131289	161	0	0
T5	129789	0	0	0
T6	29649	237	0	0
T19	44224	0	0	0
T20	165058	806	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	144	0	0
T29	0	926	0	0
T30	0	372	0	0
T46	94968	0	0	0
T49	0	193	0	0
T71	0	78	0	0
T79	0	465	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	570	0	0
T2	359777	7	0	0
T3	99314	0	0	0
T4	131289	3	0	0
T5	129789	0	0	0
T6	29649	1	0	0
T19	44224	0	0	0
T20	165058	6	0	0
T21	16225	0	0	0
T22	99127	0	0	0
T26	0	1	0	0
T30	0	9	0	0
T46	94968	0	0	0
T49	0	1	0	0
T71	0	1	0	0
T79	0	1	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	53	0	0
T8	523739	0	0	0
T16	486092	0	0	0
T17	610618	0	0	0
T18	674265	0	0	0
T23	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T49	23258	1	0	0
T50	472642	0	0	0
T68	5066	0	0	0
T69	5853	0	0	0
T70	23932	0	0	0
T75	2395	0	0	0
T79	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1433	0	0
T12	65816	192	0	0
T13	0	363	0	0
T14	0	351	0	0
T35	0	180	0	0
T36	0	347	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	1193	0	0
T12	65816	162	0	0
T13	0	303	0	0
T14	0	291	0	0
T35	0	150	0	0
T36	0	287	0	0
T37	80730	0	0	0
T38	387162	0	0	0
T39	159346	0	0	0
T40	498603	0	0	0
T41	272969	0	0	0
T42	65947	0	0	0
T43	746560	0	0	0
T44	71602	0	0	0
T45	105703	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	689904891	689835172	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	690202553	690030765	0	0
T1	199103	199096	0	0
T2	359777	359265	0	0
T3	99314	99228	0	0
T4	131289	131215	0	0
T5	129789	129639	0	0
T6	29649	29561	0	0
T19	44224	44132	0	0
T20	165058	164978	0	0
T21	16225	16151	0	0
T22	99127	99060	0	0