Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T206,T207
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13685	0	0
DisabledNoTrigBkwd_A	2147483647	821131	0	0
DisabledNoTrigFwd_A	2147483647	1533852836	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13685	0	0
T16	1548	754	0	0
T29	181657	0	0	0
T50	37589	0	0	0
T51	250265	0	0	0
T52	422877	0	0	0
T77	67987	0	0	0
T81	41217	0	0	0
T93	578448	0	0	0
T184	3642	1147	0	0
T185	168332	0	0	0
T186	222234	0	0	0
T187	104192	0	0	0
T188	10891	0	0	0
T189	276051	0	0	0
T206	0	977	0	0
T207	0	1236	0	0
T208	0	893	0	0
T209	3632	184	0	0
T210	0	1308	0	0
T211	0	538	0	0
T212	0	733	0	0
T213	0	233	0	0
T214	0	296	0	0
T215	0	690	0	0
T216	0	821	0	0
T217	0	526	0	0
T218	0	724	0	0
T219	0	466	0	0
T220	0	679	0	0
T221	0	398	0	0
T222	0	694	0	0
T223	0	388	0	0
T224	683099	0	0	0
T225	731931	0	0	0
T226	18348	0	0	0
T227	196238	0	0	0
T228	77440	0	0	0
T229	73938	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	821131	0	0
T1	3372288	5246	0	0
T2	19516	2	0	0
T3	265408	33	0	0
T4	1512824	4	0	0
T5	1248424	679	0	0
T6	0	1053	0	0
T7	0	1	0	0
T12	0	10968	0	0
T13	0	3746	0	0
T14	0	11753	0	0
T15	0	5	0	0
T16	6192	12	0	0
T17	132296	0	0	0
T18	106432	0	0	0
T19	2016188	375	0	0
T20	67992	97	0	0
T21	0	66	0	0
T44	0	33	0	0
T45	0	36	0	0
T46	0	90	0	0
T47	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1533852836	0	0
T1	3372288	1757247	0	0
T2	19516	16502	0	0
T3	265408	89358	0	0
T4	1512824	717173	0	0
T5	1248424	944352	0	0
T16	6192	2576	0	0
T17	132296	61050	0	0
T18	106432	46524	0	0
T19	2016188	995512	0	0
T20	67992	28137	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T19
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T209,T213,T220
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	688995679	1494	0	0
DisabledNoTrigBkwd_A	688995679	238995	0	0
DisabledNoTrigFwd_A	688995679	324873664	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	1494	0	0
T29	181657	0	0	0
T52	422877	0	0	0
T81	41217	0	0	0
T93	578448	0	0	0
T209	3632	184	0	0
T213	0	233	0	0
T220	0	679	0	0
T221	0	398	0	0
T225	731931	0	0	0
T226	18348	0	0	0
T227	196238	0	0	0
T228	77440	0	0	0
T229	73938	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	238995	0	0
T1	843072	1387	0	0
T2	4879	2	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	0	3026	0	0
T13	0	1865	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	81	0	0
T21	0	11	0	0
T44	0	28	0	0
T45	0	25	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	324873664	0	0
T1	843072	47244	0	0
T2	4879	2141	0	0
T3	66352	61902	0	0
T4	378206	332757	0	0
T5	312106	311305	0	0
T16	1548	638	0	0
T17	33074	2098	0	0
T18	26608	3057	0	0
T19	504047	481881	0	0
T20	16998	2397	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T4,T17
1	1	Covered	T1,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184
1	1	Covered	T1,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T19,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	688995679	1147	0	0
DisabledNoTrigBkwd_A	688995679	159207	0	0
DisabledNoTrigFwd_A	688995679	416096826	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	1147	0	0
T50	37589	0	0	0
T51	250265	0	0	0
T77	67987	0	0	0
T184	3642	1147	0	0
T185	168332	0	0	0
T186	222234	0	0	0
T187	104192	0	0	0
T188	10891	0	0	0
T189	276051	0	0	0
T224	683099	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	159207	0	0
T1	843072	3423	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	679	0	0
T12	0	2188	0	0
T13	0	6	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	171	0	0
T20	16998	9	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	64	0	0
T47	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	416096826	0	0
T1	843072	60179	0	0
T2	4879	4787	0	0
T3	66352	2516	0	0
T4	378206	378139	0	0
T5	312106	8853	0	0
T16	1548	642	0	0
T17	33074	23809	0	0
T18	26608	3072	0	0
T19	504047	16649	0	0
T20	16998	7889	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T206,T210
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	688995679	6026	0	0
DisabledNoTrigBkwd_A	688995679	203396	0	0
DisabledNoTrigFwd_A	688995679	407453138	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	6026	0	0
T5	312106	0	0	0
T6	966310	0	0	0
T8	959637	0	0	0
T12	138474	0	0	0
T16	1548	754	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T82	11188	0	0	0
T206	0	977	0	0
T210	0	1308	0	0
T211	0	538	0	0
T212	0	733	0	0
T217	0	526	0	0
T218	0	724	0	0
T219	0	466	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	203396	0	0
T1	843072	22	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	4	0	0
T5	312106	0	0	0
T6	0	1052	0	0
T12	0	5754	0	0
T13	0	1854	0	0
T14	0	14	0	0
T16	1548	12	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	28	0	0
T45	0	8	0	0
T46	0	26	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	407453138	0	0
T1	843072	818109	0	0
T2	4879	4787	0	0
T3	66352	11490	0	0
T4	378206	3128	0	0
T5	312106	312097	0	0
T16	1548	646	0	0
T17	33074	33001	0	0
T18	26608	13879	0	0
T19	504047	485463	0	0
T20	16998	16934	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T208,T214
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	688995679	5018	0	0
DisabledNoTrigBkwd_A	688995679	219533	0	0
DisabledNoTrigFwd_A	688995679	385429208	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	5018	0	0
T65	827088	0	0	0
T73	38201	0	0	0
T75	28910	0	0	0
T76	6376	0	0	0
T207	3678	1236	0	0
T208	0	893	0	0
T214	0	296	0	0
T215	0	690	0	0
T216	0	821	0	0
T222	0	694	0	0
T223	0	388	0	0
T230	29523	0	0	0
T231	44820	0	0	0
T232	138781	0	0	0
T233	70238	0	0	0
T234	2887	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	219533	0	0
T1	843072	414	0	0
T2	4879	0	0	0
T3	66352	33	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	21	0	0
T14	0	11739	0	0
T15	0	5	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	204	0	0
T20	16998	7	0	0
T21	0	27	0	0
T44	0	3	0	0
T45	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	385429208	0	0
T1	843072	831715	0	0
T2	4879	4787	0	0
T3	66352	13450	0	0
T4	378206	3149	0	0
T5	312106	312097	0	0
T16	1548	650	0	0
T17	33074	2142	0	0
T18	26608	26516	0	0
T19	504047	11519	0	0
T20	16998	917	0	0