Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T13,T7 Yes T1,T13,T7 INPUT
ping_ok_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
integ_fail_o Yes Yes T1,T2,T12 Yes T1,T2,T12 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T13,T7 Yes T1,T13,T7 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T13,T7 Yes T1,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T14,T60,T237 Yes T14,T60,T237 INPUT
ping_ok_o Yes Yes T14,T60,T237 Yes T14,T60,T237 OUTPUT
integ_fail_o Yes Yes T12,T21,T14 Yes T12,T21,T14 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T60,T237 Yes T60,T237,T231 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T231 Yes T14,T60,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T7,T14 Yes T1,T7,T14 INPUT
ping_ok_o Yes Yes T1,T14,T60 Yes T1,T14,T60 OUTPUT
integ_fail_o Yes Yes T14,T47,T238 Yes T14,T47,T238 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T7,T14 Yes T1,T7,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T7,T60 Yes T1,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T60,T25,T237 Yes T60,T25,T237 INPUT
ping_ok_o Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
integ_fail_o Yes Yes T1,T2,T12 Yes T1,T2,T12 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T13,T60 Yes T1,T13,T60 INPUT
ping_ok_o Yes Yes T1,T13,T60 Yes T1,T13,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T13,T60 Yes T1,T13,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T13,T60 Yes T1,T13,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T15 Yes T12,T13,T15 INPUT
ping_ok_o Yes Yes T12,T13,T15 Yes T12,T13,T15 OUTPUT
integ_fail_o Yes Yes T21,T25,T26 Yes T21,T25,T26 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T60 Yes T13,T60,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T25 Yes T12,T13,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T12,T14 Yes T8,T12,T14 INPUT
ping_ok_o Yes Yes T12,T14,T15 Yes T12,T14,T15 OUTPUT
integ_fail_o Yes Yes T1,T21,T47 Yes T1,T21,T47 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T12,T14 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T8,T12,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T7,T14,T15 Yes T7,T14,T15 INPUT
ping_ok_o Yes Yes T14,T60,T237 Yes T14,T60,T237 OUTPUT
integ_fail_o Yes Yes T1,T20,T47 Yes T1,T20,T47 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T14,T15 Yes T14,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T237 Yes T7,T14,T15 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T60,T25,T237 Yes T60,T25,T237 INPUT
ping_ok_o Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
integ_fail_o Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T13,T14 Yes T8,T13,T14 INPUT
ping_ok_o Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
integ_fail_o Yes Yes T14,T47,T25 Yes T14,T47,T25 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T13,T14 Yes T8,T60,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T8,T60,T25 Yes T8,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T6,T60,T47 Yes T6,T60,T47 INPUT
ping_ok_o Yes Yes T6,T60,T47 Yes T6,T60,T47 OUTPUT
integ_fail_o Yes Yes T20,T21,T14 Yes T20,T21,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T47,T237 Yes T60,T47,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T47,T237 Yes T60,T47,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T7,T60 Yes T8,T7,T60 INPUT
ping_ok_o Yes Yes T60,T68,T237 Yes T60,T68,T237 OUTPUT
integ_fail_o Yes Yes T1,T13,T14 Yes T1,T13,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T7,T60 Yes T60,T237,T63 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T63 Yes T8,T7,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T7 Yes T12,T13,T7 INPUT
ping_ok_o Yes Yes T12,T13,T60 Yes T12,T13,T60 OUTPUT
integ_fail_o Yes Yes T21,T47,T26 Yes T21,T47,T26 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T7 Yes T60,T25,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T68 Yes T12,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T14,T60 Yes T13,T14,T60 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T47,T238,T68 Yes T47,T238,T68 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T15,T60,T47 Yes T15,T60,T47 INPUT
ping_ok_o Yes Yes T15,T60,T47 Yes T15,T60,T47 OUTPUT
integ_fail_o Yes Yes T1,T68,T26 Yes T1,T68,T26 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T47,T83 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T60,T47,T83 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T8,T7 Yes T5,T8,T7 INPUT
ping_ok_o Yes Yes T5,T14,T15 Yes T5,T14,T15 OUTPUT
integ_fail_o Yes Yes T1,T2,T20 Yes T1,T2,T20 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T7,T14 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T8,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T8,T6 Yes T5,T8,T6 INPUT
ping_ok_o Yes Yes T5,T6,T60 Yes T5,T6,T60 OUTPUT
integ_fail_o Yes Yes T1,T14,T27 Yes T1,T14,T27 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T7,T60 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T8,T7,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T14,T60,T25 Yes T14,T60,T25 INPUT
ping_ok_o Yes Yes T14,T60,T25 Yes T14,T60,T25 OUTPUT
integ_fail_o Yes Yes T1,T20,T12 Yes T1,T20,T12 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T60,T25 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T14,T60,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T4,T5,T13 Yes T4,T5,T13 INPUT
ping_ok_o Yes Yes T5,T13,T14 Yes T5,T13,T14 OUTPUT
integ_fail_o Yes Yes T1,T20,T12 Yes T1,T20,T12 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T14 Yes T14,T60,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T25 Yes T4,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T13,T14 Yes T8,T13,T14 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T13,T14 Yes T13,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T237 Yes T8,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T12,T14 Yes T1,T12,T14 INPUT
ping_ok_o Yes Yes T1,T12,T14 Yes T1,T12,T14 OUTPUT
integ_fail_o Yes Yes T20,T12,T21 Yes T20,T12,T21 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T12,T14 Yes T1,T12,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T12,T60 Yes T1,T12,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T60,T237 Yes T12,T60,T237 INPUT
ping_ok_o Yes Yes T12,T60,T237 Yes T12,T60,T237 OUTPUT
integ_fail_o Yes Yes T12,T47,T238 Yes T12,T47,T238 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T60,T237 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T12,T60,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T14,T60 Yes T13,T14,T60 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T12,T21,T25 Yes T12,T21,T25 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T60,T61 Yes T5,T60,T61 INPUT
ping_ok_o Yes Yes T5,T60,T61 Yes T5,T60,T61 OUTPUT
integ_fail_o Yes Yes T12,T13,T21 Yes T12,T13,T21 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T60,T61 Yes T60,T61,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T61,T237 Yes T5,T60,T61 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T5,T13 Yes T1,T5,T13 INPUT
ping_ok_o Yes Yes T1,T5,T13 Yes T1,T5,T13 OUTPUT
integ_fail_o Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T5,T13 Yes T1,T5,T13 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T5,T13 Yes T1,T5,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T14,T60,T25 Yes T14,T60,T25 INPUT
ping_ok_o Yes Yes T14,T60,T25 Yes T14,T60,T25 OUTPUT
integ_fail_o Yes Yes T20,T12,T14 Yes T20,T12,T14 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T60,T25 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T14,T60,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T14 Yes T12,T13,T14 INPUT
ping_ok_o Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
integ_fail_o Yes Yes T12,T47,T25 Yes T12,T47,T25 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T14 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T12,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T13,T7 Yes T5,T13,T7 INPUT
ping_ok_o Yes Yes T13,T60,T25 Yes T13,T60,T25 OUTPUT
integ_fail_o Yes Yes T20,T25,T62 Yes T20,T25,T62 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T7 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T5,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T6,T15 Yes T5,T6,T15 INPUT
ping_ok_o Yes Yes T5,T6,T15 Yes T5,T6,T15 OUTPUT
integ_fail_o Yes Yes T1,T20,T12 Yes T1,T20,T12 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T83,T68 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T60,T83,T68 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T7,T60 Yes T13,T7,T60 INPUT
ping_ok_o Yes Yes T13,T60,T25 Yes T13,T60,T25 OUTPUT
integ_fail_o Yes Yes T14,T26,T70 Yes T14,T26,T70 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T7,T60 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T13,T7,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T14,T60 Yes T13,T14,T60 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T1,T20,T12 Yes T1,T20,T12 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T14,T60,T83 Yes T14,T60,T83 INPUT
ping_ok_o Yes Yes T14,T60,T61 Yes T14,T60,T61 OUTPUT
integ_fail_o Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T60,T83 Yes T60,T237,T64 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T64 Yes T14,T60,T83 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T7,T14 Yes T13,T7,T14 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T21 Yes T1,T12,T21 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T7,T14 Yes T14,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T237 Yes T13,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T13,T7 Yes T5,T13,T7 INPUT
ping_ok_o Yes Yes T5,T13,T14 Yes T5,T13,T14 OUTPUT
integ_fail_o Yes Yes T12,T21,T238 Yes T12,T21,T238 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T7,T14 Yes T7,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T60,T237 Yes T13,T7,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T12,T14 Yes T1,T12,T14 INPUT
ping_ok_o Yes Yes T1,T12,T14 Yes T1,T12,T14 OUTPUT
integ_fail_o Yes Yes T20,T14,T68 Yes T20,T14,T68 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T12,T14 Yes T1,T14,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T14,T60 Yes T1,T12,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T6,T13 Yes T1,T6,T13 INPUT
ping_ok_o Yes Yes T1,T6,T13 Yes T1,T6,T13 OUTPUT
integ_fail_o Yes Yes T1,T21,T68 Yes T1,T21,T68 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T13,T14 Yes T1,T60,T83 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T60,T83 Yes T1,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T60 Yes T12,T13,T60 INPUT
ping_ok_o Yes Yes T12,T13,T60 Yes T12,T13,T60 OUTPUT
integ_fail_o Yes Yes T1,T14,T25 Yes T1,T14,T25 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T60 Yes T13,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T237 Yes T12,T13,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T60,T68 Yes T13,T60,T68 INPUT
ping_ok_o Yes Yes T13,T60,T68 Yes T13,T60,T68 OUTPUT
integ_fail_o Yes Yes T14,T26,T70 Yes T14,T26,T70 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T60,T68 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T13,T60,T68 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T60 Yes T12,T13,T60 INPUT
ping_ok_o Yes Yes T12,T13,T60 Yes T12,T13,T60 OUTPUT
integ_fail_o Yes Yes T1,T13,T47 Yes T1,T13,T47 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T60 Yes T12,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T60,T237 Yes T12,T13,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T6,T12,T13 Yes T6,T12,T13 INPUT
ping_ok_o Yes Yes T6,T12,T13 Yes T6,T12,T13 OUTPUT
integ_fail_o Yes Yes T1,T20,T14 Yes T1,T20,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T7 Yes T13,T60,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T68 Yes T12,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T4,T13,T60 Yes T4,T13,T60 INPUT
ping_ok_o Yes Yes T13,T60,T25 Yes T13,T60,T25 OUTPUT
integ_fail_o Yes Yes T1,T14,T116 Yes T1,T14,T116 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T60 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T4,T13,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T8,T13 Yes T5,T8,T13 INPUT
ping_ok_o Yes Yes T13,T60,T25 Yes T13,T60,T25 OUTPUT
integ_fail_o Yes Yes T12,T68,T26 Yes T12,T68,T26 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T8,T13 Yes T5,T13,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T13,T60 Yes T5,T8,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T4,T13,T14 Yes T4,T13,T14 INPUT
ping_ok_o Yes Yes T13,T14,T15 Yes T13,T14,T15 OUTPUT
integ_fail_o Yes Yes T20,T12,T21 Yes T20,T12,T21 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T14 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T4,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T13,T14 Yes T1,T13,T14 INPUT
ping_ok_o Yes Yes T1,T13,T14 Yes T1,T13,T14 OUTPUT
integ_fail_o Yes Yes T20,T12,T14 Yes T20,T12,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T13,T14 Yes T1,T60,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T60,T25 Yes T1,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T6,T13 Yes T5,T6,T13 INPUT
ping_ok_o Yes Yes T5,T13,T14 Yes T5,T13,T14 OUTPUT
integ_fail_o Yes Yes T1,T14,T68 Yes T1,T14,T68 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T13,T7 Yes T7,T14,T60 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T14,T60 Yes T6,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T6,T60,T47 Yes T6,T60,T47 INPUT
ping_ok_o Yes Yes T6,T60,T47 Yes T6,T60,T47 OUTPUT
integ_fail_o Yes Yes T1,T21,T14 Yes T1,T21,T14 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T47,T68 Yes T60,T237,T231 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T231 Yes T60,T47,T68 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T14,T60 Yes T13,T14,T60 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T13,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T237 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T60,T25 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T4,T13,T7 Yes T4,T13,T7 INPUT
ping_ok_o Yes Yes T13,T60,T237 Yes T13,T60,T237 OUTPUT
integ_fail_o Yes Yes T20,T47,T25 Yes T20,T47,T25 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T7 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T4,T13,T7 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T13,T60 Yes T5,T13,T60 INPUT
ping_ok_o Yes Yes T5,T13,T60 Yes T5,T13,T60 OUTPUT
integ_fail_o Yes Yes T13,T68,T26 Yes T13,T68,T26 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T60,T47 Yes T60,T47,T68 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T47,T68 Yes T13,T60,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T12,T13 Yes T5,T12,T13 INPUT
ping_ok_o Yes Yes T5,T12,T13 Yes T5,T12,T13 OUTPUT
integ_fail_o Yes Yes T1,T12,T14 Yes T1,T12,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T14 Yes T60,T237,T63 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T63 Yes T12,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T6,T13,T14 Yes T6,T13,T14 INPUT
ping_ok_o Yes Yes T6,T13,T14 Yes T6,T13,T14 OUTPUT
integ_fail_o Yes Yes T12,T21,T116 Yes T12,T21,T116 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T5,T13,T60 Yes T5,T13,T60 INPUT
ping_ok_o Yes Yes T5,T13,T60 Yes T5,T13,T60 OUTPUT
integ_fail_o Yes Yes T20,T21,T14 Yes T20,T21,T14 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T60,T83 Yes T13,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T237 Yes T13,T60,T83 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T14,T60,T61 Yes T14,T60,T61 INPUT
ping_ok_o Yes Yes T14,T60,T61 Yes T14,T60,T61 OUTPUT
integ_fail_o Yes Yes T20,T13,T21 Yes T20,T13,T21 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T60,T61 Yes T14,T60,T61 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T61 Yes T14,T60,T61 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T14,T60 Yes T13,T14,T60 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T1,T21,T14 Yes T1,T21,T14 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T14,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T237 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T13,T14 Yes T8,T13,T14 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T13,T14 Yes T14,T60,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T25 Yes T8,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T60,T239,T237 Yes T60,T239,T237 INPUT
ping_ok_o Yes Yes T60,T237,T240 Yes T60,T237,T240 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T239,T237 Yes T60,T237,T26 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T26 Yes T60,T239,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T15,T60 Yes T13,T15,T60 INPUT
ping_ok_o Yes Yes T13,T15,T60 Yes T13,T15,T60 OUTPUT
integ_fail_o Yes Yes T20,T12,T13 Yes T20,T12,T13 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T60,T47 Yes T60,T47,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T47,T237 Yes T13,T60,T47 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T12,T13 Yes T8,T12,T13 INPUT
ping_ok_o Yes Yes T12,T13,T60 Yes T12,T13,T60 OUTPUT
integ_fail_o Yes Yes T12,T13,T21 Yes T12,T13,T21 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T12,T13 Yes T60,T237,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T27 Yes T8,T12,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T12,T13 Yes T8,T12,T13 INPUT
ping_ok_o Yes Yes T12,T13,T60 Yes T12,T13,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T12,T13 Yes T60,T25,T61 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T61 Yes T8,T12,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T14,T60,T237 Yes T14,T60,T237 INPUT
ping_ok_o Yes Yes T14,T60,T237 Yes T14,T60,T237 OUTPUT
integ_fail_o Yes Yes T14,T62,T68 Yes T14,T62,T68 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T60,T237 Yes T60,T237,T27 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T27 Yes T14,T60,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T1,T12,T60 Yes T1,T12,T60 INPUT
ping_ok_o Yes Yes T1,T12,T60 Yes T1,T12,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T1,T12,T60 Yes T1,T60,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T1,T60,T25 Yes T1,T12,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T60,T25,T237 Yes T60,T25,T237 INPUT
ping_ok_o Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
integ_fail_o Yes Yes T12,T13,T21 Yes T12,T13,T21 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T25,T237 Yes T60,T25,T237 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T14 Yes T12,T13,T14 INPUT
ping_ok_o Yes Yes T12,T13,T14 Yes T12,T13,T14 OUTPUT
integ_fail_o Yes Yes T20,T12,T47 Yes T20,T12,T47 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T14 Yes T60,T47,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T47,T237 Yes T12,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T8,T13,T14 Yes T8,T13,T14 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T25,T68,T26 Yes T25,T68,T26 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T8,T13,T14 Yes T60,T237,T116 OUTPUT
alert_rx_o.ping_p Yes Yes T60,T237,T116 Yes T8,T13,T14 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T16 Yes T1,T3,T16 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T13,T14,T60 Yes T13,T14,T60 INPUT
ping_ok_o Yes Yes T13,T14,T60 Yes T13,T14,T60 OUTPUT
integ_fail_o Yes Yes T12,T14,T25 Yes T12,T14,T25 OUTPUT
alert_o Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T16 Yes T1,T3,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T60 Yes T14,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T60,T237 Yes T13,T14,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T60,T25 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T6,T60 Yes T1,T2,T4 INPUT
ping_req_i Yes Yes T12,T13,T60 Yes T12,T13,T60 INPUT
ping_ok_o Yes Yes T12,T13,T60 Yes T12,T13,T60 OUTPUT
integ_fail_o Yes Yes T1,T12,T13 Yes T1,T12,T13 OUTPUT
alert_o Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T60 Yes T13,T60,T237 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T60,T237 Yes T12,T13,T60 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT

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