Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T1,T2,T17
1	1	1	Covered	T1,T2,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T17,T20,T21
1	0	Covered	T1,T12,T21

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T12,T21

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T22,T23,T24
1	1	Covered	T17,T20,T21

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T16,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T17,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T19,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T2,T17

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T2,T17
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T25,T26,T27
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T12,T26,T27
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T28,T29,T30
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T31,T32
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T4
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T17
TimeoutSt->Phase0St	172	Covered	T1,T17,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T26,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T29,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T31,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	901	0	0
CheckAccumTrig0_A	2147483647	2323	0	0
CheckAccumTrig1_A	2147483647	127	0	0
CheckClr_A	2147483647	1034	0	0
CheckEn_A	2147483647	1131374929	0	0
CheckPhase0_A	2147483647	2658	0	0
CheckPhase1_A	2147483647	2607	0	0
CheckPhase2_A	2147483647	2564	0	0
CheckPhase3_A	2147483647	2508	0	0
CheckTimeout0_A	2147483647	3323	0	0
CheckTimeoutSt1_A	2147483647	422162	0	0
CheckTimeoutSt2_A	2147483647	2944	0	0
CheckTimeoutStTrig_A	2147483647	243	0	0
ErrorStAllEscAsserted_A	2147483647	4364	0	0
ErrorStIsTerminal_A	2147483647	3644	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	901	0	0
T9	183948	314	0	0
T10	0	160	0	0
T11	0	156	0	0
T33	0	133	0	0
T34	0	138	0	0
T35	63832	0	0	0
T36	2220716	0	0	0
T37	2402888	0	0	0
T38	75484	0	0	0
T39	1271292	0	0	0
T40	90956	0	0	0
T41	247300	0	0	0
T42	234960	0	0	0
T43	364792	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2323	0	0
T1	3372288	13	0	0
T2	19516	1	0	0
T3	265408	1	0	0
T4	1512824	3	0	0
T5	1248424	1	0	0
T6	0	2	0	0
T7	0	1	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0
T15	0	2	0	0
T16	6192	1	0	0
T17	132296	0	0	0
T18	106432	0	0	0
T19	2016188	2	0	0
T20	67992	4	0	0
T21	0	1	0	0
T25	0	6	0	0
T44	0	6	0	0
T45	0	4	0	0
T46	0	4	0	0
T47	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	127	0	0
T1	1686144	2	0	0
T2	9758	0	0	0
T3	132704	0	0	0
T4	756412	0	0	0
T5	624212	0	0	0
T7	128670	0	0	0
T12	138474	1	0	0
T13	372074	0	0	0
T14	685116	0	0	0
T15	234752	0	0	0
T16	3096	0	0	0
T17	66148	0	0	0
T18	53216	0	0	0
T19	1008094	0	0	0
T20	33996	0	0	0
T21	72084	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T35	0	1	0	0
T44	76867	1	0	0
T45	81242	0	0	0
T46	302468	0	0	0
T47	993813	0	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	96132	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1034	0	0
T1	3372288	8	0	0
T2	19516	1	0	0
T3	265408	0	0	0
T4	1512824	3	0	0
T5	1248424	0	0	0
T6	0	1	0	0
T12	0	2	0	0
T16	6192	0	0	0
T17	132296	0	0	0
T18	106432	0	0	0
T19	2016188	0	0	0
T20	67992	2	0	0
T25	0	15	0	0
T28	0	2	0	0
T32	0	4	0	0
T35	0	1	0	0
T39	0	1	0	0
T44	0	5	0	0
T46	0	2	0	0
T47	0	1	0	0
T51	0	3	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1131374929	0	0
T1	3372288	1753817	0	0
T2	19516	16499	0	0
T3	265408	89357	0	0
T4	1512824	717171	0	0
T5	1248424	944352	0	0
T16	6192	2576	0	0
T17	132296	61048	0	0
T18	106432	46522	0	0
T19	2016188	995510	0	0
T20	67992	26780	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2658	0	0
T1	3372288	15	0	0
T2	19516	1	0	0
T3	265408	1	0	0
T4	1512824	3	0	0
T5	1248424	1	0	0
T6	0	2	0	0
T7	0	1	0	0
T12	0	5	0	0
T13	0	4	0	0
T14	0	4	0	0
T16	6192	1	0	0
T17	132296	2	0	0
T18	106432	0	0	0
T19	2016188	2	0	0
T20	67992	5	0	0
T21	0	6	0	0
T44	0	7	0	0
T45	0	3	0	0
T46	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2607	0	0
T1	3372288	15	0	0
T2	19516	1	0	0
T3	265408	1	0	0
T4	1512824	3	0	0
T5	1248424	1	0	0
T6	0	2	0	0
T7	0	1	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0
T16	6192	1	0	0
T17	132296	2	0	0
T18	106432	0	0	0
T19	2016188	2	0	0
T20	67992	5	0	0
T21	0	6	0	0
T44	0	7	0	0
T45	0	3	0	0
T46	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2564	0	0
T1	3372288	15	0	0
T2	19516	1	0	0
T3	265408	1	0	0
T4	1512824	3	0	0
T5	1248424	1	0	0
T6	0	2	0	0
T7	0	1	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0
T16	6192	1	0	0
T17	132296	2	0	0
T18	106432	0	0	0
T19	2016188	2	0	0
T20	67992	5	0	0
T21	0	6	0	0
T44	0	7	0	0
T45	0	3	0	0
T46	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2508	0	0
T1	3372288	14	0	0
T2	19516	1	0	0
T3	265408	1	0	0
T4	1512824	3	0	0
T5	1248424	1	0	0
T6	0	2	0	0
T7	0	1	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0
T16	6192	1	0	0
T17	132296	2	0	0
T18	106432	0	0	0
T19	2016188	2	0	0
T20	67992	5	0	0
T21	0	6	0	0
T44	0	7	0	0
T45	0	3	0	0
T46	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3323	0	0
T1	3372288	16	0	0
T2	19516	1	0	0
T3	265408	0	0	0
T4	1512824	0	0	0
T5	1248424	0	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T16	6192	0	0	0
T17	132296	3	0	0
T18	106432	2	0	0
T19	2016188	0	0	0
T20	67992	1	0	0
T21	0	7	0	0
T25	0	30	0	0
T26	0	5	0	0
T44	0	2	0	0
T45	0	3	0	0
T62	0	6	0	0
T67	0	10	0	0
T68	0	5	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	422162	0	0
T1	3372288	1855	0	0
T2	19516	58	0	0
T3	265408	0	0	0
T4	1512824	0	0	0
T5	1248424	0	0	0
T13	0	101	0	0
T14	0	173	0	0
T16	6192	0	0	0
T17	132296	205	0	0
T18	106432	400	0	0
T19	2016188	0	0	0
T20	67992	411	0	0
T21	0	1874	0	0
T25	0	4994	0	0
T26	0	657	0	0
T44	0	57	0	0
T45	0	551	0	0
T62	0	2024	0	0
T67	0	487	0	0
T68	0	193	0	0
T69	0	181	0	0
T70	0	838	0	0
T71	0	1	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2944	0	0
T1	3372288	14	0	0
T2	19516	1	0	0
T3	265408	0	0	0
T4	1512824	0	0	0
T5	1248424	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	6192	0	0	0
T17	132296	1	0	0
T18	106432	2	0	0
T19	2016188	0	0	0
T20	67992	0	0	0
T21	0	2	0	0
T25	0	16	0	0
T26	0	6	0	0
T27	0	2	0	0
T32	0	10	0	0
T44	0	1	0	0
T45	0	3	0	0
T62	0	3	0	0
T67	0	10	0	0
T68	0	4	0	0
T69	0	8	0	0
T71	0	6	0	0
T72	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	243	0	0
T5	624212	0	0	0
T6	2898930	0	0	0
T7	257340	0	0	0
T8	2878911	0	0	0
T12	415422	0	0	0
T13	1116222	0	0	0
T14	342558	0	0	0
T15	117376	0	0	0
T17	66148	2	0	0
T18	53216	0	0	0
T19	1008094	0	0	0
T20	50994	1	0	0
T21	144168	4	0	0
T25	0	13	0	0
T26	0	3	0	0
T32	0	6	0	0
T35	0	4	0	0
T38	0	1	0	0
T44	153734	0	0	0
T45	162484	0	0	0
T46	151234	0	0	0
T47	993813	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T60	48066	0	0	0
T62	0	4	0	0
T70	0	1	0	0
T71	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T79	0	5	0	0
T80	0	1	0	0
T81	0	3	0	0
T82	33564	0	0	0
T83	948208	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4364	0	0
T9	183948	1399	0	0
T10	0	737	0	0
T11	0	697	0	0
T33	0	807	0	0
T34	0	724	0	0
T35	63832	0	0	0
T36	2220716	0	0	0
T37	2402888	0	0	0
T38	75484	0	0	0
T39	1271292	0	0	0
T40	90956	0	0	0
T41	247300	0	0	0
T42	234960	0	0	0
T43	364792	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3644	0	0
T9	183948	1159	0	0
T10	0	617	0	0
T11	0	577	0	0
T33	0	687	0	0
T34	0	604	0	0
T35	63832	0	0	0
T36	2220716	0	0	0
T37	2402888	0	0	0
T38	75484	0	0	0
T39	1271292	0	0	0
T40	90956	0	0	0
T41	247300	0	0	0
T42	234960	0	0	0
T43	364792	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3372288	3370672	0	0
T2	19516	19148	0	0
T3	265408	265092	0	0
T4	1512824	1512556	0	0
T5	1248424	1248388	0	0
T16	6192	5952	0	0
T17	132296	132004	0	0
T18	106432	106064	0	0
T19	2016188	2015908	0	0
T20	67992	67736	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3372288	3370672	0	0
T2	19516	19148	0	0
T3	265408	265092	0	0
T4	1512824	1512556	0	0
T5	1248424	1248388	0	0
T16	6192	5952	0	0
T17	132296	132004	0	0
T18	106432	106064	0	0
T19	2016188	2015908	0	0
T20	67992	67736	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T17
1	0	1	Covered	T19,T6,T12
1	1	0	Covered	T1,T20,T44
1	1	1	Covered	T1,T2,T17

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T17
0	1	Covered	T17,T25,T62
1	0	Covered	T12,T21,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T21,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Not Covered
1	1	Covered	T17,T25,T62

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T6,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T20
1	Covered	T1,T17,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T20,T15,T47

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T20
1	Covered	T1,T2,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T6,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T17
Phase1St	198	Covered	T1,T2,T17
Phase2St	215	Covered	T1,T2,T17
Phase3St	233	Covered	T1,T2,T17
TerminalSt	249	Covered	T1,T2,T17
TimeoutSt	159	Covered	T1,T2,T17

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T20
IdleSt->TimeoutSt	159	Covered	T1,T2,T17
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T26,T27
Phase0St->Phase1St	198	Covered	T1,T2,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T27,T52
Phase1St->Phase2St	215	Covered	T1,T2,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T30,T84
Phase2St->Phase3St	233	Covered	T1,T2,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T65,T29
Phase3St->TerminalSt	249	Covered	T1,T2,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T2,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T18
TimeoutSt->Phase0St	172	Covered	T17,T12,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T12,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T17
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T26,T27,T52
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T30,T84
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T65,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	688995679	214	0	0
CheckAccumTrig0_A	688995679	832	0	0
CheckAccumTrig1_A	688995679	52	0	0
CheckClr_A	688995679	411	0	0
CheckEn_A	688846277	245378947	0	0
CheckPhase0_A	688995679	926	0	0
CheckPhase1_A	688995679	904	0	0
CheckPhase2_A	688995679	892	0	0
CheckPhase3_A	688995679	869	0	0
CheckTimeout0_A	688995679	883	0	0
CheckTimeoutSt1_A	688995679	110511	0	0
CheckTimeoutSt2_A	688995679	768	0	0
CheckTimeoutStTrig_A	688995679	60	0	0
ErrorStAllEscAsserted_A	688995679	1073	0	0
ErrorStIsTerminal_A	688995679	893	0	0
EscStateOut_A	688844635	688772694	0	0
u_state_regs_A	688995679	688846745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	214	0	0
T9	45987	79	0	0
T10	0	25	0	0
T11	0	37	0	0
T33	0	30	0	0
T34	0	43	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	832	0	0
T1	843072	6	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	3	0	0
T44	0	4	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	52	0	0
T7	128670	0	0	0
T12	138474	1	0	0
T13	372074	0	0	0
T14	342558	0	0	0
T15	117376	0	0	0
T21	72084	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	0	1	0	0
T35	0	1	0	0
T44	76867	1	0	0
T45	81242	0	0	0
T46	151234	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T60	48066	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	411	0	0
T1	843072	5	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	2	0	0
T25	0	6	0	0
T28	0	2	0	0
T44	0	4	0	0
T47	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688846277	245378947	0	0
T1	843072	47242	0	0
T2	4879	2141	0	0
T3	66352	61901	0	0
T4	378206	332756	0	0
T5	312106	311305	0	0
T16	1548	638	0	0
T17	33074	2098	0	0
T18	26608	3057	0	0
T19	504047	481880	0	0
T20	16998	2397	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	926	0	0
T1	843072	6	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	3	0	0
T21	0	1	0	0
T44	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	904	0	0
T1	843072	6	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	3	0	0
T21	0	1	0	0
T44	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	892	0	0
T1	843072	6	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	3	0	0
T21	0	1	0	0
T44	0	5	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	869	0	0
T1	843072	6	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	3	0	0
T21	0	1	0	0
T44	0	5	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	883	0	0
T1	843072	2	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T12	0	1	0	0
T14	0	1	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	1	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T25	0	11	0	0
T44	0	2	0	0
T45	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	110511	0	0
T1	843072	99	0	0
T2	4879	58	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T14	0	167	0	0
T16	1548	0	0	0
T17	33074	76	0	0
T18	26608	200	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T25	0	1838	0	0
T44	0	57	0	0
T45	0	321	0	0
T62	0	310	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	768	0	0
T1	843072	2	0	0
T2	4879	1	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T14	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	1	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T25	0	6	0	0
T26	0	4	0	0
T44	0	1	0	0
T45	0	2	0	0
T69	0	6	0	0
T72	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	60	0	0
T5	312106	0	0	0
T6	966310	0	0	0
T8	959637	0	0	0
T12	138474	0	0	0
T13	372074	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T25	0	4	0	0
T32	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T62	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T79	0	3	0	0
T82	11188	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	1073	0	0
T9	45987	340	0	0
T10	0	198	0	0
T11	0	172	0	0
T33	0	194	0	0
T34	0	169	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	893	0	0
T9	45987	280	0	0
T10	0	168	0	0
T11	0	142	0	0
T33	0	164	0	0
T34	0	139	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688844635	688772694	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	688846745	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T19,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T18
1	0	1	Covered	T3,T19,T5
1	1	0	Covered	T1,T17,T20
1	1	1	Covered	T1,T17,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T20,T21,T25
1	0	Covered	T1,T32,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T22
1	1	Covered	T20,T21,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T5
1	Covered	T1,T12,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T5
1	Covered	T1,T20,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T12
1	Covered	T19,T5,T25

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T5
1	Covered	T20,T25,T85

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T19,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T20,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T21,T45

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T19,T5
Phase1St	198	Covered	T1,T19,T5
Phase2St	215	Covered	T1,T19,T5
Phase3St	233	Covered	T1,T19,T5
TerminalSt	249	Covered	T1,T19,T5
TimeoutSt	159	Covered	T1,T17,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T19,T5
IdleSt->TimeoutSt	159	Covered	T1,T17,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T86,T87,T88
Phase0St->Phase1St	198	Covered	T1,T19,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T89,T59
Phase1St->Phase2St	215	Covered	T1,T19,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T90,T91
Phase2St->Phase3St	233	Covered	T1,T19,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T32,T92
Phase3St->TerminalSt	249	Covered	T1,T19,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T44,T46
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T17,T18
TimeoutSt->Phase0St	172	Covered	T1,T20,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T86,T87,T88
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T19,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T19,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T89,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T19,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T19,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T90,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T19,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T19,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T32,T92
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T19,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T19,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T44,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T19,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	688995679	207	0	0
CheckAccumTrig0_A	688995679	476	0	0
CheckAccumTrig1_A	688995679	20	0	0
CheckClr_A	688995679	169	0	0
CheckEn_A	688846277	314036106	0	0
CheckPhase0_A	688995679	545	0	0
CheckPhase1_A	688995679	539	0	0
CheckPhase2_A	688995679	529	0	0
CheckPhase3_A	688995679	522	0	0
CheckTimeout0_A	688995679	895	0	0
CheckTimeoutSt1_A	688995679	111071	0	0
CheckTimeoutSt2_A	688995679	818	0	0
CheckTimeoutStTrig_A	688995679	55	0	0
ErrorStAllEscAsserted_A	688995679	1081	0	0
ErrorStIsTerminal_A	688995679	901	0	0
EscStateOut_A	688844635	688772694	0	0
u_state_regs_A	688995679	688846745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	207	0	0
T9	45987	56	0	0
T10	0	42	0	0
T11	0	35	0	0
T33	0	40	0	0
T34	0	34	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	476	0	0
T1	843072	2	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	0	0	0
T25	0	6	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	20	0	0
T1	843072	1	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T32	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	169	0	0
T1	843072	2	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T25	0	5	0	0
T32	0	3	0	0
T35	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T46	0	2	0	0
T51	0	1	0	0
T62	0	1	0	0
T66	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688846277	314036106	0	0
T1	843072	60175	0	0
T2	4879	4786	0	0
T3	66352	2516	0	0
T4	378206	378138	0	0
T5	312106	8853	0	0
T16	1548	642	0	0
T17	33074	23808	0	0
T18	26608	3072	0	0
T19	504047	16649	0	0
T20	16998	6533	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	545	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	539	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	529	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	522	0	0
T1	843072	2	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	895	0	0
T1	843072	7	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	1	0	0
T19	504047	0	0	0
T20	16998	1	0	0
T21	0	1	0	0
T25	0	6	0	0
T26	0	3	0	0
T62	0	2	0	0
T68	0	2	0	0
T69	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	111071	0	0
T1	843072	273	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	129	0	0
T18	26608	200	0	0
T19	504047	0	0	0
T20	16998	411	0	0
T21	0	953	0	0
T25	0	851	0	0
T26	0	349	0	0
T62	0	311	0	0
T68	0	90	0	0
T69	0	57	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	818	0	0
T1	843072	6	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	1	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T25	0	3	0	0
T26	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T71	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	55	0	0
T6	966310	0	0	0
T7	128670	0	0	0
T8	959637	0	0	0
T12	138474	0	0	0
T13	372074	0	0	0
T20	16998	1	0	0
T21	72084	1	0	0
T25	0	3	0	0
T26	0	1	0	0
T32	0	2	0	0
T44	76867	0	0	0
T45	81242	0	0	0
T49	0	1	0	0
T62	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T82	11188	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	1081	0	0
T9	45987	356	0	0
T10	0	177	0	0
T11	0	187	0	0
T33	0	191	0	0
T34	0	170	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	901	0	0
T9	45987	296	0	0
T10	0	147	0	0
T11	0	157	0	0
T33	0	161	0	0
T34	0	140	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688844635	688772694	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	688846745	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T12
1	0	1	Covered	T3,T16,T19
1	1	0	Covered	T1,T17,T18
1	1	1	Covered	T1,T13,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T21
0	1	Covered	T21,T25,T62
1	0	Covered	T1,T32,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T13,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T21
1	0	Covered	T24
1	1	Covered	T21,T25,T62

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T16,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T1,T6,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T1,T21,T45

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T16,T6
1	Covered	T4,T46,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T16,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T16,T6,T46

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T16
Phase1St	198	Covered	T1,T4,T16
Phase2St	215	Covered	T1,T4,T16
Phase3St	233	Covered	T1,T4,T16
TerminalSt	249	Covered	T1,T4,T16
TimeoutSt	159	Covered	T1,T13,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T4,T16
IdleSt->TimeoutSt	159	Covered	T1,T13,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T93,T94
Phase0St->Phase1St	198	Covered	T1,T4,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T12,T95,T59
Phase1St->Phase2St	215	Covered	T1,T4,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T96,T97,T59
Phase2St->Phase3St	233	Covered	T1,T4,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T49,T66
Phase3St->TerminalSt	249	Covered	T1,T4,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T13,T45
TimeoutSt->Phase0St	172	Covered	T1,T21,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T13,T45
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T93,T94,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T95,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T96,T97,T59
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T66,T96
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	688995679	257	0	0
CheckAccumTrig0_A	688995679	518	0	0
CheckAccumTrig1_A	688995679	26	0	0
CheckClr_A	688995679	241	0	0
CheckEn_A	688846277	295180224	0	0
CheckPhase0_A	688995679	603	0	0
CheckPhase1_A	688995679	594	0	0
CheckPhase2_A	688995679	585	0	0
CheckPhase3_A	688995679	573	0	0
CheckTimeout0_A	688995679	814	0	0
CheckTimeoutSt1_A	688995679	98077	0	0
CheckTimeoutSt2_A	688995679	720	0	0
CheckTimeoutStTrig_A	688995679	66	0	0
ErrorStAllEscAsserted_A	688995679	1109	0	0
ErrorStIsTerminal_A	688995679	929	0	0
EscStateOut_A	688844635	688772694	0	0
u_state_regs_A	688995679	688846745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	257	0	0
T9	45987	95	0	0
T10	0	46	0	0
T11	0	50	0	0
T33	0	37	0	0
T34	0	29	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	518	0	0
T1	843072	2	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	3	0	0
T5	312106	0	0	0
T6	0	1	0	0
T12	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	1548	1	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	26	0	0
T1	843072	1	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T32	0	1	0	0
T48	0	1	0	0
T53	0	2	0	0
T87	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	241	0	0
T1	843072	1	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	3	0	0
T5	312106	0	0	0
T12	0	2	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T25	0	4	0	0
T32	0	1	0	0
T51	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688846277	295180224	0	0
T1	843072	814689	0	0
T2	4879	4786	0	0
T3	66352	11490	0	0
T4	378206	3128	0	0
T5	312106	312097	0	0
T16	1548	646	0	0
T17	33074	33000	0	0
T18	26608	13878	0	0
T19	504047	485462	0	0
T20	16998	16933	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	603	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	3	0	0
T5	312106	0	0	0
T6	0	1	0	0
T12	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	1548	1	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	594	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	3	0	0
T5	312106	0	0	0
T6	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	1548	1	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	585	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	3	0	0
T5	312106	0	0	0
T6	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	1548	1	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	573	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	3	0	0
T5	312106	0	0	0
T6	0	1	0	0
T12	0	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	1548	1	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	814	0	0
T1	843072	6	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	1	0	0
T25	0	7	0	0
T26	0	1	0	0
T45	0	1	0	0
T62	0	3	0	0
T67	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	98077	0	0
T1	843072	1463	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	101	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	803	0	0
T25	0	1724	0	0
T26	0	134	0	0
T45	0	230	0	0
T62	0	973	0	0
T67	0	55	0	0
T70	0	764	0	0
T71	0	1	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	720	0	0
T1	843072	5	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T25	0	5	0	0
T27	0	2	0	0
T32	0	7	0	0
T45	0	1	0	0
T62	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	66	0	0
T7	128670	0	0	0
T14	342558	0	0	0
T15	117376	0	0	0
T21	72084	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T32	0	1	0	0
T44	76867	0	0	0
T45	81242	0	0	0
T46	151234	0	0	0
T47	993813	0	0	0
T60	48066	0	0	0
T62	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T81	0	1	0	0
T83	948208	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	1109	0	0
T9	45987	363	0	0
T10	0	189	0	0
T11	0	174	0	0
T33	0	202	0	0
T34	0	181	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	929	0	0
T9	45987	303	0	0
T10	0	159	0	0
T11	0	144	0	0
T33	0	172	0	0
T34	0	151	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688844635	688772694	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	688846745	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T20
1	0	1	Covered	T3,T4,T19
1	1	0	Covered	T1,T2,T82
1	1	1	Covered	T1,T17,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T21,T14
0	1	Covered	T17,T21,T25
1	0	Covered	T14,T68,T32

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T17,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T14,T68,T32

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T14
1	0	Covered	T23
1	1	Covered	T17,T21,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T13,T21,T44

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T20
1	Covered	T1,T3,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T20,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T19,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T20,T21,T44

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T13

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T1,T17,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T19
IdleSt->TimeoutSt	159	Covered	T1,T17,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T104,T102,T105
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T51,T89,T101
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T106,T107
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T64,T101
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T21,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T21,T25
TimeoutSt->Phase0St	172	Covered	T17,T21,T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T104,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T51,T89,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T106,T107
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T64,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T21,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	688995679	223	0	0
CheckAccumTrig0_A	688995679	497	0	0
CheckAccumTrig1_A	688995679	29	0	0
CheckClr_A	688995679	213	0	0
CheckEn_A	688846277	276779652	0	0
CheckPhase0_A	688995679	584	0	0
CheckPhase1_A	688995679	570	0	0
CheckPhase2_A	688995679	558	0	0
CheckPhase3_A	688995679	544	0	0
CheckTimeout0_A	688995679	731	0	0
CheckTimeoutSt1_A	688995679	102503	0	0
CheckTimeoutSt2_A	688995679	638	0	0
CheckTimeoutStTrig_A	688995679	62	0	0
ErrorStAllEscAsserted_A	688995679	1101	0	0
ErrorStIsTerminal_A	688995679	921	0	0
EscStateOut_A	688844635	688772694	0	0
u_state_regs_A	688995679	688846745	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	223	0	0
T9	45987	84	0	0
T10	0	47	0	0
T11	0	34	0	0
T33	0	26	0	0
T34	0	32	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	497	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	1	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	29	0	0
T14	342558	1	0	0
T15	117376	0	0	0
T25	369887	0	0	0
T32	0	2	0	0
T35	0	2	0	0
T46	151234	0	0	0
T47	993813	0	0	0
T60	48066	0	0	0
T61	223969	0	0	0
T68	0	1	0	0
T83	948208	0	0	0
T85	10757	0	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	47733	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	213	0	0
T1	843072	2	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T14	0	2	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	2	0	0
T25	0	2	0	0
T32	0	4	0	0
T51	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T70	0	1	0	0
T115	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688846277	276779652	0	0
T1	843072	831711	0	0
T2	4879	4786	0	0
T3	66352	13450	0	0
T4	378206	3149	0	0
T5	312106	312097	0	0
T16	1548	650	0	0
T17	33074	2142	0	0
T18	26608	26515	0	0
T19	504047	11519	0	0
T20	16998	917	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	584	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	1	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	570	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	1	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	558	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	1	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	544	0	0
T1	843072	3	0	0
T2	4879	0	0	0
T3	66352	1	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T13	0	1	0	0
T14	0	3	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	1	0	0
T20	16998	1	0	0
T21	0	3	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	731	0	0
T1	843072	1	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T14	0	1	0	0
T16	1548	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	4	0	0
T25	0	6	0	0
T26	0	1	0	0
T62	0	1	0	0
T67	0	9	0	0
T68	0	3	0	0
T69	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	102503	0	0
T1	843072	20	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T14	0	6	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	117	0	0
T25	0	581	0	0
T26	0	174	0	0
T62	0	430	0	0
T67	0	432	0	0
T68	0	103	0	0
T69	0	124	0	0
T70	0	74	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	638	0	0
T1	843072	1	0	0
T2	4879	0	0	0
T3	66352	0	0	0
T4	378206	0	0	0
T5	312106	0	0	0
T16	1548	0	0	0
T17	33074	0	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	2	0	0
T25	0	2	0	0
T62	0	1	0	0
T67	0	9	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	4	0	0
T116	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	62	0	0
T5	312106	0	0	0
T6	966310	0	0	0
T8	959637	0	0	0
T12	138474	0	0	0
T13	372074	0	0	0
T17	33074	1	0	0
T18	26608	0	0	0
T19	504047	0	0	0
T20	16998	0	0	0
T21	0	2	0	0
T25	0	4	0	0
T26	0	1	0	0
T32	0	1	0	0
T35	0	4	0	0
T38	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	11188	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	1101	0	0
T9	45987	340	0	0
T10	0	173	0	0
T11	0	164	0	0
T33	0	220	0	0
T34	0	204	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	921	0	0
T9	45987	280	0	0
T10	0	143	0	0
T11	0	134	0	0
T33	0	190	0	0
T34	0	174	0	0
T35	15958	0	0	0
T36	555179	0	0	0
T37	600722	0	0	0
T38	18871	0	0	0
T39	317823	0	0	0
T40	22739	0	0	0
T41	61825	0	0	0
T42	58740	0	0	0
T43	91198	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688844635	688772694	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	688995679	688846745	0	0
T1	843072	842668	0	0
T2	4879	4787	0	0
T3	66352	66273	0	0
T4	378206	378139	0	0
T5	312106	312097	0	0
T16	1548	1488	0	0
T17	33074	33001	0	0
T18	26608	26516	0	0
T19	504047	503977	0	0
T20	16998	16934	0	0