Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66346583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32346258

1

T1

125754

T2

3013

T3

91375

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15085670	1			T1	48861		T2	1153		T3	35136
values[0x0]	40615760	1			T1	174323		T2	3938		T3	126544
values[0x1]	42991411	1			T1	173597		T2	3948		T3	126528

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56459338	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42233503

1

T1

158994

T2

3768

T3

115466

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	326047	1			T1	1451		T2	35		T3	1092
valid_sources[0x01]	320726	1			T1	1518		T2	30		T3	1146
valid_sources[0x02]	736984	1			T1	1578		T2	30		T3	1242
valid_sources[0x03]	783849	1			T1	1579		T2	30		T3	1174
valid_sources[0x04]	566379	1			T1	1540		T2	23		T3	1031
valid_sources[0x05]	602910	1			T1	1505		T2	27		T3	1225
valid_sources[0x06]	309525	1			T1	1635		T2	45		T3	1057
valid_sources[0x07]	305343	1			T1	1520		T2	44		T3	1174
valid_sources[0x08]	312692	1			T1	1607		T2	20		T3	1033
valid_sources[0x09]	520623	1			T1	1587		T2	33		T3	1179
valid_sources[0x0a]	651967	1			T1	1582		T2	22		T3	1223
valid_sources[0x0b]	313872	1			T1	1551		T2	27		T3	1127
valid_sources[0x0c]	309316	1			T1	1574		T2	28		T3	1133
valid_sources[0x0d]	652301	1			T1	1560		T2	33		T3	1149
valid_sources[0x0e]	349478	1			T1	1560		T2	39		T3	1192
valid_sources[0x0f]	317822	1			T1	1563		T2	39		T3	1156
valid_sources[0x10]	305571	1			T1	1606		T2	37		T3	1116
valid_sources[0x11]	318228	1			T1	1550		T2	43		T3	1113
valid_sources[0x12]	321957	1			T1	1576		T2	45		T3	1052
valid_sources[0x13]	770779	1			T1	1600		T2	43		T3	1150
valid_sources[0x14]	326641	1			T1	1469		T2	44		T3	1193
valid_sources[0x15]	307043	1			T1	1499		T2	42		T3	1084
valid_sources[0x16]	302970	1			T1	1480		T2	25		T3	1231
valid_sources[0x17]	574223	1			T1	1525		T2	42		T3	1190
valid_sources[0x18]	316503	1			T1	1501		T2	25		T3	1135
valid_sources[0x19]	302449	1			T1	1535		T2	34		T3	1091
valid_sources[0x1a]	349956	1			T1	1526		T2	42		T3	1216
valid_sources[0x1b]	631556	1			T1	1602		T2	37		T3	1306
valid_sources[0x1c]	309867	1			T1	1447		T2	45		T3	1063
valid_sources[0x1d]	324733	1			T1	1564		T2	25		T3	1229
valid_sources[0x1e]	314475	1			T1	1627		T2	35		T3	1011
valid_sources[0x1f]	304514	1			T1	1489		T2	40		T3	1042
valid_sources[0x20]	310673	1			T1	1608		T2	32		T3	1232
valid_sources[0x21]	315114	1			T1	1588		T2	36		T3	1026
valid_sources[0x22]	325683	1			T1	1509		T2	33		T3	1206
valid_sources[0x23]	330594	1			T1	1527		T2	27		T3	1100
valid_sources[0x24]	1205593	1			T1	1575		T2	41		T3	1172
valid_sources[0x25]	302689	1			T1	1423		T2	31		T3	1098
valid_sources[0x26]	311856	1			T1	1558		T2	32		T3	1193
valid_sources[0x27]	623605	1			T1	1535		T2	40		T3	995
valid_sources[0x28]	319334	1			T1	1574		T2	41		T3	1094
valid_sources[0x29]	320547	1			T1	1569		T2	38		T3	1134
valid_sources[0x2a]	311588	1			T1	1502		T2	32		T3	1111
valid_sources[0x2b]	578256	1			T1	1594		T2	32		T3	1115
valid_sources[0x2c]	310317	1			T1	1602		T2	28		T3	1140
valid_sources[0x2d]	788331	1			T1	1531		T2	30		T3	1098
valid_sources[0x2e]	305934	1			T1	1524		T2	30		T3	1094
valid_sources[0x2f]	314278	1			T1	1479		T2	38		T3	1122
valid_sources[0x30]	314882	1			T1	1577		T2	38		T3	1059
valid_sources[0x31]	748933	1			T1	1558		T2	28		T3	1097
valid_sources[0x32]	671590	1			T1	1521		T2	27		T3	995
valid_sources[0x33]	784092	1			T1	1530		T2	36		T3	1078
valid_sources[0x34]	309609	1			T1	1527		T2	35		T3	1120
valid_sources[0x35]	351913	1			T1	1549		T2	32		T3	992
valid_sources[0x36]	316091	1			T1	1498		T2	29		T3	1112
valid_sources[0x37]	313123	1			T1	1517		T2	30		T3	1224
valid_sources[0x38]	328902	1			T1	1556		T2	31		T3	1139
valid_sources[0x39]	312191	1			T1	1552		T2	39		T3	1167
valid_sources[0x3a]	335051	1			T1	1519		T2	34		T3	1097
valid_sources[0x3b]	310997	1			T1	1571		T2	31		T3	1136
valid_sources[0x3c]	320144	1			T1	1562		T2	18		T3	1085
valid_sources[0x3d]	298026	1			T1	1551		T2	30		T3	1063
valid_sources[0x3e]	308852	1			T1	1581		T2	30		T3	1078
valid_sources[0x3f]	306604	1			T1	1585		T2	33		T3	1134
valid_sources[0x40]	542422	1			T1	1520		T2	28		T3	1118
valid_sources[0x41]	321379	1			T1	1509		T2	29		T3	1115
valid_sources[0x42]	298273	1			T1	1612		T2	39		T3	1148
valid_sources[0x43]	315111	1			T1	1527		T2	45		T3	1099
valid_sources[0x44]	307666	1			T1	1506		T2	40		T3	1135
valid_sources[0x45]	305688	1			T1	1547		T2	29		T3	1105
valid_sources[0x46]	309293	1			T1	1522		T2	47		T3	1108
valid_sources[0x47]	308835	1			T1	1581		T2	36		T3	1044
valid_sources[0x48]	305316	1			T1	1637		T2	36		T3	1212
valid_sources[0x49]	304466	1			T1	1536		T2	29		T3	1173
valid_sources[0x4a]	307593	1			T1	1536		T2	31		T3	1041
valid_sources[0x4b]	310827	1			T1	1555		T2	39		T3	1187
valid_sources[0x4c]	309667	1			T1	1536		T2	43		T3	1036
valid_sources[0x4d]	305401	1			T1	1575		T2	50		T3	1233
valid_sources[0x4e]	308896	1			T1	1488		T2	31		T3	1207
valid_sources[0x4f]	314808	1			T1	1446		T2	28		T3	1196
valid_sources[0x50]	324759	1			T1	1478		T2	42		T3	1205
valid_sources[0x51]	314187	1			T1	1554		T2	34		T3	1131
valid_sources[0x52]	303723	1			T1	1614		T2	45		T3	1117
valid_sources[0x53]	315041	1			T1	1524		T2	46		T3	1094
valid_sources[0x54]	308990	1			T1	1522		T2	33		T3	1119
valid_sources[0x55]	309711	1			T1	1535		T2	45		T3	1105
valid_sources[0x56]	774601	1			T1	1660		T2	36		T3	1102
valid_sources[0x57]	709905	1			T1	1582		T2	36		T3	988
valid_sources[0x58]	302187	1			T1	1570		T2	40		T3	1015
valid_sources[0x59]	303206	1			T1	1551		T2	45		T3	1161
valid_sources[0x5a]	309468	1			T1	1507		T2	33		T3	1102
valid_sources[0x5b]	316283	1			T1	1593		T2	31		T3	1068
valid_sources[0x5c]	315120	1			T1	1550		T2	36		T3	1058
valid_sources[0x5d]	306540	1			T1	1546		T2	37		T3	1084
valid_sources[0x5e]	317782	1			T1	1474		T2	33		T3	1125
valid_sources[0x5f]	301475	1			T1	1599		T2	23		T3	1232
valid_sources[0x60]	313828	1			T1	1643		T2	28		T3	1085
valid_sources[0x61]	621511	1			T1	1501		T2	36		T3	1116
valid_sources[0x62]	318825	1			T1	1581		T2	47		T3	1064
valid_sources[0x63]	310728	1			T1	1550		T2	39		T3	1124
valid_sources[0x64]	341425	1			T1	1565		T2	30		T3	1107
valid_sources[0x65]	309027	1			T1	1465		T2	45		T3	1172
valid_sources[0x66]	319942	1			T1	1596		T2	39		T3	1080
valid_sources[0x67]	307450	1			T1	1609		T2	27		T3	1105
valid_sources[0x68]	304340	1			T1	1629		T2	32		T3	1067
valid_sources[0x69]	300636	1			T1	1581		T2	38		T3	1138
valid_sources[0x6a]	580906	1			T1	1652		T2	43		T3	1148
valid_sources[0x6b]	312193	1			T1	1511		T2	38		T3	1185
valid_sources[0x6c]	310015	1			T1	1560		T2	31		T3	1107
valid_sources[0x6d]	318108	1			T1	1559		T2	30		T3	1183
valid_sources[0x6e]	306048	1			T1	1512		T2	29		T3	1166
valid_sources[0x6f]	326788	1			T1	1547		T2	37		T3	1266
valid_sources[0x70]	315194	1			T1	1529		T2	37		T3	1189
valid_sources[0x71]	314486	1			T1	1551		T2	30		T3	1177
valid_sources[0x72]	313082	1			T1	1448		T2	28		T3	1060
valid_sources[0x73]	981559	1			T1	1562		T2	43		T3	1172
valid_sources[0x74]	306266	1			T1	1519		T2	29		T3	1152
valid_sources[0x75]	315606	1			T1	1529		T2	30		T3	1099
valid_sources[0x76]	748642	1			T1	1570		T2	42		T3	1103
valid_sources[0x77]	301033	1			T1	1523		T2	26		T3	1124
valid_sources[0x78]	311052	1			T1	1501		T2	36		T3	1151
valid_sources[0x79]	783481	1			T1	1551		T2	38		T3	1184
valid_sources[0x7a]	313875	1			T1	1526		T2	35		T3	1082
valid_sources[0x7b]	613280	1			T1	1549		T2	41		T3	1147
valid_sources[0x7c]	311084	1			T1	1456		T2	32		T3	1154
valid_sources[0x7d]	310148	1			T1	1551		T2	33		T3	1056
valid_sources[0x7e]	319121	1			T1	1526		T2	33		T3	1092
valid_sources[0x7f]	764395	1			T1	1587		T2	40		T3	1198
valid_sources[0x80]	309828	1			T1	1556		T2	35		T3	1095

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7521475

1

T1

24449

T2

557

T3

17636

values[0x0]

all_enables

biggest_size

15632492

1

T1

64822

T2

1562

T3

47303

values[0x1]

all_enables

biggest_size

9192291

1

T1

36483

T2

894

T3

26436