Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T39,T200
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12692	0	0
DisabledNoTrigBkwd_A	2147483647	868252	0	0
DisabledNoTrigFwd_A	2147483647	1558307757	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12692	0	0
T9	593770	0	0	0
T22	0	847	0	0
T25	369142	0	0	0
T26	408553	0	0	0
T39	3216	913	0	0
T63	62745	0	0	0
T74	0	777	0	0
T79	372440	0	0	0
T83	36635	0	0	0
T113	254373	0	0	0
T116	100373	0	0	0
T117	342749	0	0	0
T118	93413	0	0	0
T200	1188	317	0	0
T201	0	569	0	0
T202	0	510	0	0
T203	0	1449	0	0
T204	0	293	0	0
T205	0	342	0	0
T206	0	705	0	0
T207	1498	697	0	0
T208	0	544	0	0
T209	0	493	0	0
T210	0	711	0	0
T211	0	323	0	0
T212	0	435	0	0
T213	0	230	0	0
T214	0	895	0	0
T215	0	1088	0	0
T216	0	554	0	0
T217	89875	0	0	0
T218	310033	0	0	0
T219	111388	0	0	0
T220	715444	0	0	0
T221	350557	0	0	0
T222	121304	0	0	0
T223	11004	0	0	0
T224	71946	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	868252	0	0
T1	1663436	1732	0	0
T2	128548	0	0	0
T3	3772288	0	0	0
T4	897872	4628	0	0
T5	55196	5	0	0
T6	0	2007	0	0
T7	0	1	0	0
T8	0	891	0	0
T15	3326384	2978	0	0
T16	1059204	0	0	0
T17	0	2095	0	0
T18	0	4468	0	0
T19	0	11	0	0
T20	737216	51	0	0
T21	139444	0	0	0
T22	7164	20	0	0
T23	0	52	0	0
T30	0	297	0	0
T46	0	1	0	0
T47	0	74	0	0
T48	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1558307757	0	0
T1	1663436	1250158	0	0
T2	128548	14176	0	0
T3	3772288	3770695	0	0
T4	897872	261226	0	0
T5	55196	21649	0	0
T15	3326384	1671989	0	0
T16	1059204	533777	0	0
T20	737216	551027	0	0
T21	139444	90757	0	0
T22	7164	3276	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T74,T202
1	1	Covered	T1,T2,T20

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T20,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699833099	4383	0	0
DisabledNoTrigBkwd_A	699833099	313629	0	0
DisabledNoTrigFwd_A	699833099	323246627	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	4383	0	0
T9	593770	0	0	0
T25	369142	0	0	0
T26	408553	0	0	0
T74	0	777	0	0
T79	372440	0	0	0
T83	36635	0	0	0
T116	100373	0	0	0
T117	342749	0	0	0
T118	93413	0	0	0
T200	1188	317	0	0
T202	0	510	0	0
T203	0	1449	0	0
T212	0	435	0	0
T214	0	895	0	0
T217	89875	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	313629	0	0
T1	415859	1707	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1833	0	0
T5	13799	0	0	0
T15	831596	1480	0	0
T16	264801	0	0	0
T17	0	1170	0	0
T18	0	960	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	13	0	0
T30	0	108	0	0
T46	0	1	0	0
T47	0	18	0	0
T48	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	323246627	0	0
T1	415859	8900	0	0
T2	32137	4686	0	0
T3	943072	941737	0	0
T4	224468	21837	0	0
T5	13799	13739	0	0
T15	831596	1705	0	0
T16	264801	264204	0	0
T20	184304	181831	0	0
T21	34861	3125	0	0
T22	1791	813	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T3,T20
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T209,T213
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699833099	1974	0	0
DisabledNoTrigBkwd_A	699833099	191066	0	0
DisabledNoTrigFwd_A	699833099	393423280	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1974	0	0
T63	62745	0	0	0
T113	254373	0	0	0
T207	1498	697	0	0
T209	0	493	0	0
T213	0	230	0	0
T216	0	554	0	0
T218	310033	0	0	0
T219	111388	0	0	0
T220	715444	0	0	0
T221	350557	0	0	0
T222	121304	0	0	0
T223	11004	0	0	0
T224	71946	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	191066	0	0
T1	415859	3	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	992	0	0
T5	13799	3	0	0
T6	0	966	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	11	0	0
T18	0	4	0	0
T19	0	7	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	20	0	0
T30	0	96	0	0
T47	0	25	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	393423280	0	0
T1	415859	414667	0	0
T2	32137	590	0	0
T3	943072	942986	0	0
T4	224468	12262	0	0
T5	13799	2614	0	0
T15	831596	831507	0	0
T16	264801	3544	0	0
T20	184304	183109	0	0
T21	34861	34767	0	0
T22	1791	817	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T201,T204
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699833099	4823	0	0
DisabledNoTrigBkwd_A	699833099	178990	0	0
DisabledNoTrigFwd_A	699833099	430984253	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	4823	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T39	3216	913	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0
T78	3420	0	0	0
T201	0	569	0	0
T204	0	293	0	0
T206	0	705	0	0
T208	0	544	0	0
T210	0	711	0	0
T215	0	1088	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	178990	0	0
T1	415859	5	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1803	0	0
T5	13799	2	0	0
T6	0	1041	0	0
T15	831596	1498	0	0
T16	264801	0	0	0
T17	0	6	0	0
T18	0	2	0	0
T20	184304	51	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	14	0	0
T47	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	430984253	0	0
T1	415859	414566	0	0
T2	32137	8302	0	0
T3	943072	942986	0	0
T4	224468	2666	0	0
T5	13799	2637	0	0
T15	831596	7270	0	0
T16	264801	262447	0	0
T20	184304	1873	0	0
T21	34861	18098	0	0
T22	1791	821	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T3,T20
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T205,T211
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T16,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	699833099	1512	0	0
DisabledNoTrigBkwd_A	699833099	184567	0	0
DisabledNoTrigFwd_A	699833099	410653597	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1512	0	0
T6	587680	0	0	0
T17	570085	0	0	0
T18	303676	0	0	0
T22	1791	847	0	0
T23	54666	0	0	0
T30	279549	0	0	0
T46	67043	0	0	0
T47	55594	0	0	0
T48	7874	0	0	0
T67	64647	0	0	0
T205	0	342	0	0
T211	0	323	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	184567	0	0
T1	415859	17	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T7	0	1	0	0
T8	0	891	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	908	0	0
T18	0	3502	0	0
T19	0	4	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	20	0	0
T23	0	5	0	0
T30	0	93	0	0
T47	0	29	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	410653597	0	0
T1	415859	412025	0	0
T2	32137	598	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	2659	0	0
T15	831596	831507	0	0
T16	264801	3582	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	825	0	0