Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T21
1	0	1	Covered	T1,T20,T4
1	1	0	Covered	T2,T21,T23
1	1	1	Covered	T2,T5,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T21
0	1	Covered	T21,T23,T24
1	0	Covered	T23,T25,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T21
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T23,T25,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T21
1	0	Covered	T27,T28,T29
1	1	Covered	T21,T23,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T5,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T4,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T5,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T23,T30

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T5,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T4,T15

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T5,T20
Phase1St	198	Covered	T1,T5,T20
Phase2St	215	Covered	T1,T5,T20
Phase3St	233	Covered	T1,T5,T20
TerminalSt	249	Covered	T1,T5,T20
TimeoutSt	159	Covered	T2,T5,T21

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T5,T20
IdleSt->TimeoutSt	159	Covered	T2,T5,T21
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T31,T32,T33
Phase0St->Phase1St	198	Covered	T1,T5,T20
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T34,T35,T36
Phase1St->Phase2St	215	Covered	T1,T5,T20
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T4,T8,T31
Phase2St->Phase3St	233	Covered	T1,T5,T20
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T1,T4,T19
Phase3St->TerminalSt	249	Covered	T1,T5,T20
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T4,T17
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T5,T21
TimeoutSt->Phase0St	172	Covered	T21,T23,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T23,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T35,T36
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T8,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T4,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1136	0	0
CheckAccumTrig0_A	2147483647	2397	0	0
CheckAccumTrig1_A	2147483647	108	0	0
CheckClr_A	2147483647	1138	0	0
CheckEn_A	2147483647	1214643681	0	0
CheckPhase0_A	2147483647	2703	0	0
CheckPhase1_A	2147483647	2659	0	0
CheckPhase2_A	2147483647	2614	0	0
CheckPhase3_A	2147483647	2559	0	0
CheckTimeout0_A	2147483647	4880	0	0
CheckTimeoutSt1_A	2147483647	484856	0	0
CheckTimeoutSt2_A	2147483647	4516	0	0
CheckTimeoutStTrig_A	2147483647	254	0	0
ErrorStAllEscAsserted_A	2147483647	5856	0	0
ErrorStIsTerminal_A	2147483647	4896	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1136	0	0
T12	432424	228	0	0
T13	0	148	0	0
T14	0	286	0	0
T33	3870848	0	0	0
T34	524104	0	0	0
T37	0	192	0	0
T38	0	282	0	0
T39	12864	0	0	0
T40	752632	0	0	0
T41	279636	0	0	0
T42	299964	0	0	0
T43	1684328	0	0	0
T44	440088	0	0	0
T45	997092	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2397	0	0
T1	1663436	5	0	0
T2	128548	0	0	0
T3	3772288	0	0	0
T4	897872	14	0	0
T5	55196	2	0	0
T6	0	2	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	3326384	2	0	0
T16	1059204	0	0	0
T17	0	7	0	0
T18	0	5	0	0
T19	0	5	0	0
T20	737216	1	0	0
T21	139444	0	0	0
T22	7164	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T30	0	4	0	0
T31	0	3	0	0
T46	0	1	0	0
T47	0	8	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	108	0	0
T6	587680	0	0	0
T7	120937	0	0	0
T18	303676	0	0	0
T19	458925	0	0	0
T23	54666	1	0	0
T25	369142	2	0	0
T26	817106	1	0	0
T30	279549	0	0	0
T46	67043	0	0	0
T47	55594	0	0	0
T48	7874	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	64647	0	0	0
T68	1120982	0	0	0
T69	7454	0	0	0
T70	109146	0	0	0
T71	20339	0	0	0
T72	72077	0	0	0
T73	328351	0	0	0
T74	1580	0	0	0
T75	5807	0	0	0
T76	30636	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138	0	0
T1	831718	2	0	0
T2	64274	0	0	0
T3	1886144	0	0	0
T4	448936	11	0	0
T5	27598	0	0	0
T6	1175360	0	0	0
T7	120937	0	0	0
T8	117909	1	0	0
T15	1663192	0	0	0
T16	529602	0	0	0
T17	570085	1	0	0
T18	607352	1	0	0
T19	917850	1	0	0
T20	368608	0	0	0
T21	69722	0	0	0
T22	3582	0	0	0
T23	0	1	0	0
T25	0	8	0	0
T30	0	1	0	0
T31	0	6	0	0
T32	0	1	0	0
T33	0	4	0	0
T34	0	15	0	0
T42	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	134086	0	0	0
T47	111188	1	0	0
T48	15748	1	0	0
T67	129294	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	4742	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1214643681	0	0
T1	1663436	457438	0	0
T2	128548	14176	0	0
T3	3772288	3770691	0	0
T4	897872	256542	0	0
T5	55196	21648	0	0
T15	3326384	1666430	0	0
T16	1059204	533777	0	0
T20	737216	551024	0	0
T21	139444	86312	0	0
T22	7164	3276	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2703	0	0
T1	1663436	5	0	0
T2	128548	0	0	0
T3	3772288	0	0	0
T4	897872	14	0	0
T5	55196	2	0	0
T6	0	2	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	3326384	2	0	0
T16	1059204	0	0	0
T17	0	7	0	0
T18	0	5	0	0
T19	0	4	0	0
T20	737216	1	0	0
T21	139444	1	0	0
T22	7164	1	0	0
T23	0	5	0	0
T30	0	4	0	0
T46	0	1	0	0
T47	0	8	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2659	0	0
T1	1663436	5	0	0
T2	128548	0	0	0
T3	3772288	0	0	0
T4	897872	14	0	0
T5	55196	2	0	0
T6	0	2	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	3326384	2	0	0
T16	1059204	0	0	0
T17	0	7	0	0
T18	0	5	0	0
T19	0	4	0	0
T20	737216	1	0	0
T21	139444	1	0	0
T22	7164	1	0	0
T23	0	5	0	0
T30	0	4	0	0
T46	0	1	0	0
T47	0	8	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2614	0	0
T1	1663436	5	0	0
T2	128548	0	0	0
T3	3772288	0	0	0
T4	897872	13	0	0
T5	55196	2	0	0
T6	0	2	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	3326384	2	0	0
T16	1059204	0	0	0
T17	0	7	0	0
T18	0	5	0	0
T19	0	4	0	0
T20	737216	1	0	0
T21	139444	1	0	0
T22	7164	1	0	0
T23	0	5	0	0
T30	0	4	0	0
T46	0	1	0	0
T47	0	8	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2559	0	0
T1	1663436	4	0	0
T2	128548	0	0	0
T3	3772288	0	0	0
T4	897872	11	0	0
T5	55196	2	0	0
T6	0	2	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	3326384	2	0	0
T16	1059204	0	0	0
T17	0	7	0	0
T18	0	5	0	0
T19	0	3	0	0
T20	737216	1	0	0
T21	139444	1	0	0
T22	7164	1	0	0
T23	0	5	0	0
T30	0	4	0	0
T46	0	1	0	0
T47	0	8	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4880	0	0
T2	128548	29	0	0
T3	3772288	0	0	0
T4	897872	0	0	0
T5	55196	1	0	0
T15	3326384	0	0	0
T16	1059204	0	0	0
T17	2280340	0	0	0
T18	0	1	0	0
T20	737216	0	0	0
T21	139444	3	0	0
T22	7164	0	0	0
T23	0	3	0	0
T24	0	1	0	0
T25	0	10	0	0
T26	0	1	0	0
T31	0	8	0	0
T34	0	49	0	0
T42	0	4	0	0
T45	0	18	0	0
T46	0	3	0	0
T47	0	1	0	0
T67	0	9	0	0
T70	0	4	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	13	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	484856	0	0
T2	128548	2221	0	0
T3	3772288	0	0	0
T4	897872	0	0	0
T5	55196	148	0	0
T15	3326384	0	0	0
T16	1059204	0	0	0
T17	2280340	0	0	0
T18	0	100	0	0
T20	737216	0	0	0
T21	139444	358	0	0
T22	7164	0	0	0
T23	0	698	0	0
T24	0	873	0	0
T25	0	1621	0	0
T26	0	2	0	0
T31	0	927	0	0
T34	0	3595	0	0
T42	0	199	0	0
T44	0	151	0	0
T45	0	6150	0	0
T46	0	268	0	0
T67	0	1693	0	0
T70	0	592	0	0
T78	0	984	0	0
T80	0	115	0	0
T81	0	108	0	0
T83	0	1963	0	0
T84	0	125	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4516	0	0
T2	128548	29	0	0
T3	3772288	0	0	0
T4	897872	0	0	0
T5	55196	1	0	0
T15	3326384	0	0	0
T16	1059204	0	0	0
T17	2280340	0	0	0
T18	0	1	0	0
T20	737216	0	0	0
T21	139444	2	0	0
T22	7164	0	0	0
T25	0	5	0	0
T26	0	2	0	0
T31	0	7	0	0
T34	0	48	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	12	0	0
T46	0	3	0	0
T49	0	1	0	0
T67	0	9	0	0
T70	0	3	0	0
T78	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	13	0	0
T84	0	5	0	0
T85	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	254	0	0
T6	587680	0	0	0
T7	120937	0	0	0
T12	108106	0	0	0
T18	607352	0	0	0
T19	458925	0	0	0
T21	34861	1	0	0
T23	109332	1	0	0
T24	87934	1	0	0
T25	0	3	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	5	0	0
T30	559098	0	0	0
T31	197328	1	0	0
T32	937592	0	0	0
T34	0	1	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T45	0	4	0	0
T46	134086	0	0	0
T47	55594	0	0	0
T48	7874	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T57	0	1	0	0
T67	64647	0	0	0
T70	0	1	0	0
T77	322608	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	80206	0	0	0
T94	3852	0	0	0
T95	77375	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5856	0	0
T12	432424	1472	0	0
T13	0	710	0	0
T14	0	1451	0	0
T33	3870848	0	0	0
T34	524104	0	0	0
T37	0	707	0	0
T38	0	1516	0	0
T39	12864	0	0	0
T40	752632	0	0	0
T41	279636	0	0	0
T42	299964	0	0	0
T43	1684328	0	0	0
T44	440088	0	0	0
T45	997092	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4896	0	0
T12	432424	1232	0	0
T13	0	590	0	0
T14	0	1211	0	0
T33	3870848	0	0	0
T34	524104	0	0	0
T37	0	587	0	0
T38	0	1276	0	0
T39	12864	0	0	0
T40	752632	0	0	0
T41	279636	0	0	0
T42	299964	0	0	0
T43	1684328	0	0	0
T44	440088	0	0	0
T45	997092	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1663436	1663404	0	0
T2	128548	128232	0	0
T3	3772288	3771944	0	0
T4	897872	897844	0	0
T5	55196	54956	0	0
T15	3326384	3326028	0	0
T16	1059204	1059180	0	0
T20	737216	736856	0	0
T21	139444	139068	0	0
T22	7164	6932	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1663436	1663404	0	0
T2	128548	128232	0	0
T3	3772288	3771944	0	0
T4	897872	897844	0	0
T5	55196	54956	0	0
T15	3326384	3326028	0	0
T16	1059204	1059180	0	0
T20	737216	736856	0	0
T21	139444	139068	0	0
T22	7164	6932	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T21
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T21

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T21,T23
1	0	1	Covered	T20,T15,T30
1	1	0	Covered	T67,T47,T81
1	1	1	Covered	T2,T21,T23

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T46
0	1	Covered	T24,T25,T70
1	0	Covered	T23,T25,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T21,T46
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T25,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T23
1	0	Covered	T27,T29,T96
1	1	Covered	T24,T25,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T23
1	Covered	T4,T17,T48

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Covered	T23,T18,T93

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T15,T30,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T15,T17
1	Covered	T1,T46,T77

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T15,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T17,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T15,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T17,T30

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T15
Phase1St	198	Covered	T1,T4,T15
Phase2St	215	Covered	T1,T4,T15
Phase3St	233	Covered	T1,T4,T15
TerminalSt	249	Covered	T1,T4,T15
TimeoutSt	159	Covered	T2,T21,T23

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T4,T15
IdleSt->TimeoutSt	159	Covered	T2,T21,T23
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T34,T45,T97
Phase0St->Phase1St	198	Covered	T1,T4,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T34,T36,T98
Phase1St->Phase2St	215	Covered	T1,T4,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T8,T34,T25
Phase2St->Phase3St	233	Covered	T1,T4,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T25,T98
Phase3St->TerminalSt	249	Covered	T1,T4,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T18,T48,T31
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T21,T46
TimeoutSt->Phase0St	172	Covered	T23,T24,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T23
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T46
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T21,T46
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T45,T97
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T36,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T34,T25
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T25,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T48,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699833099	294	0	0
CheckAccumTrig0_A	699833099	953	0	0
CheckAccumTrig1_A	699833099	50	0	0
CheckClr_A	699833099	493	0	0
CheckEn_A	699590607	242051233	0	0
CheckPhase0_A	699833099	1046	0	0
CheckPhase1_A	699833099	1025	0	0
CheckPhase2_A	699833099	999	0	0
CheckPhase3_A	699833099	979	0	0
CheckTimeout0_A	699833099	1060	0	0
CheckTimeoutSt1_A	699833099	109551	0	0
CheckTimeoutSt2_A	699833099	951	0	0
CheckTimeoutStTrig_A	699833099	59	0	0
ErrorStAllEscAsserted_A	699833099	1419	0	0
ErrorStIsTerminal_A	699833099	1179	0	0
EscStateOut_A	699588861	699519572	0	0
u_state_regs_A	699833099	699662186	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	294	0	0
T12	108106	49	0	0
T13	0	39	0	0
T14	0	87	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	45	0	0
T38	0	74	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	953	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1	0	0
T5	13799	0	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	50	0	0
T6	587680	0	0	0
T7	120937	0	0	0
T18	303676	0	0	0
T19	458925	0	0	0
T23	54666	1	0	0
T25	0	1	0	0
T30	279549	0	0	0
T46	67043	0	0	0
T47	55594	0	0	0
T48	7874	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T67	64647	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	493	0	0
T6	587680	0	0	0
T7	120937	0	0	0
T8	117909	1	0	0
T18	303676	1	0	0
T19	458925	0	0	0
T25	0	6	0	0
T31	0	1	0	0
T34	0	14	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	67043	0	0	0
T47	55594	0	0	0
T48	7874	1	0	0
T67	64647	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	4742	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699590607	242051233	0	0
T1	415859	8900	0	0
T2	32137	4686	0	0
T3	943072	941736	0	0
T4	224468	17153	0	0
T5	13799	13738	0	0
T15	831596	1705	0	0
T16	264801	264204	0	0
T20	184304	181830	0	0
T21	34861	3125	0	0
T22	1791	813	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1046	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1	0	0
T5	13799	0	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1025	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1	0	0
T5	13799	0	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	999	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1	0	0
T5	13799	0	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	979	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1	0	0
T5	13799	0	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1060	0	0
T2	32137	5	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	2	0	0
T22	1791	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T31	0	2	0	0
T34	0	7	0	0
T42	0	1	0	0
T46	0	3	0	0
T67	0	4	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	109551	0	0
T2	32137	372	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	302	0	0
T22	1791	0	0	0
T24	0	873	0	0
T31	0	131	0	0
T34	0	324	0	0
T42	0	121	0	0
T44	0	151	0	0
T46	0	268	0	0
T67	0	742	0	0
T80	0	115	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	951	0	0
T2	32137	5	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	2	0	0
T22	1791	0	0	0
T31	0	2	0	0
T34	0	7	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	3	0	0
T67	0	4	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	59	0	0
T12	108106	0	0	0
T24	87934	1	0	0
T25	0	1	0	0
T29	0	5	0	0
T31	197328	0	0	0
T32	937592	0	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T57	0	1	0	0
T70	0	1	0	0
T77	322608	0	0	0
T88	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	80206	0	0	0
T94	3852	0	0	0
T95	77375	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1419	0	0
T12	108106	337	0	0
T13	0	168	0	0
T14	0	386	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	170	0	0
T38	0	358	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1179	0	0
T12	108106	277	0	0
T13	0	138	0	0
T14	0	326	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	140	0	0
T38	0	298	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699588861	699519572	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	699662186	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T23
1	0	1	Covered	T1,T20,T31
1	1	0	Covered	T21,T47,T24
1	1	1	Covered	T2,T23,T67

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T23,T67
0	1	Covered	T23,T31,T34
1	0	Covered	T26,T50,T59

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T23,T67
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T50,T59

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T23,T67
1	0	Covered	T28
1	1	Covered	T23,T31,T34

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T5,T4,T17
1	Covered	T1,T19,T32

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T4,T17,T30

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T17
1	Covered	T5,T4,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T4
1	Covered	T23,T30,T6

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T17,T30

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T4,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T4,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T4,T17,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T5,T4
Phase1St	198	Covered	T1,T5,T4
Phase2St	215	Covered	T1,T5,T4
Phase3St	233	Covered	T1,T5,T4
TerminalSt	249	Covered	T1,T5,T4
TimeoutSt	159	Covered	T2,T23,T67

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T5,T4
IdleSt->TimeoutSt	159	Covered	T2,T23,T67
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T32,T33,T34
Phase0St->Phase1St	198	Covered	T1,T5,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T59,T99,T100
Phase1St->Phase2St	215	Covered	T1,T5,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T101,T102,T103
Phase2St->Phase3St	233	Covered	T1,T5,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T19,T42,T88
Phase3St->TerminalSt	249	Covered	T1,T5,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T17
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T67,T31
TimeoutSt->Phase0St	172	Covered	T23,T31,T34

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T67
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T31,T34
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T67
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T67,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T32,T33,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T99,T100,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T101,T102,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T19,T42,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699833099	253	0	0
CheckAccumTrig0_A	699833099	469	0	0
CheckAccumTrig1_A	699833099	15	0	0
CheckClr_A	699833099	193	0	0
CheckEn_A	699590607	295798761	0	0
CheckPhase0_A	699833099	537	0	0
CheckPhase1_A	699833099	530	0	0
CheckPhase2_A	699833099	527	0	0
CheckPhase3_A	699833099	515	0	0
CheckTimeout0_A	699833099	1029	0	0
CheckTimeoutSt1_A	699833099	127108	0	0
CheckTimeoutSt2_A	699833099	946	0	0
CheckTimeoutStTrig_A	699833099	68	0	0
ErrorStAllEscAsserted_A	699833099	1446	0	0
ErrorStIsTerminal_A	699833099	1206	0	0
EscStateOut_A	699588861	699519572	0	0
u_state_regs_A	699833099	699662186	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	253	0	0
T12	108106	78	0	0
T13	0	25	0	0
T14	0	41	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	43	0	0
T38	0	66	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	469	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	2	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T30	0	2	0	0
T31	0	3	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	15	0	0
T26	408553	1	0	0
T50	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	560491	0	0	0
T69	3727	0	0	0
T70	54573	0	0	0
T71	20339	0	0	0
T72	72077	0	0	0
T73	328351	0	0	0
T74	1580	0	0	0
T75	5807	0	0	0
T76	30636	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	193	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	1	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	1	0	0
T19	0	1	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T42	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699590607	295798761	0	0
T1	415859	414667	0	0
T2	32137	590	0	0
T3	943072	942985	0	0
T4	224468	12262	0	0
T5	13799	2614	0	0
T15	831596	831506	0	0
T16	264801	3544	0	0
T20	184304	183108	0	0
T21	34861	34766	0	0
T22	1791	817	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	537	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	2	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	530	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	2	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	527	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	2	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	515	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	2	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T30	0	2	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1029	0	0
T2	32137	7	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T31	0	2	0	0
T34	0	10	0	0
T45	0	4	0	0
T67	0	5	0	0
T78	0	1	0	0
T83	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	127108	0	0
T2	32137	535	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	695	0	0
T25	0	78	0	0
T26	0	2	0	0
T31	0	668	0	0
T34	0	1807	0	0
T45	0	967	0	0
T67	0	951	0	0
T78	0	977	0	0
T83	0	1041	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	946	0	0
T2	32137	7	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T31	0	1	0	0
T34	0	9	0	0
T45	0	2	0	0
T49	0	1	0	0
T67	0	5	0	0
T78	0	1	0	0
T83	0	7	0	0
T84	0	3	0	0
T85	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	68	0	0
T6	587680	0	0	0
T7	120937	0	0	0
T18	303676	0	0	0
T19	458925	0	0	0
T23	54666	1	0	0
T25	0	1	0	0
T28	0	1	0	0
T30	279549	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T45	0	2	0	0
T46	67043	0	0	0
T47	55594	0	0	0
T48	7874	0	0	0
T50	0	1	0	0
T67	64647	0	0	0
T86	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1446	0	0
T12	108106	353	0	0
T13	0	173	0	0
T14	0	338	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	178	0	0
T38	0	404	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1206	0	0
T12	108106	293	0	0
T13	0	143	0	0
T14	0	278	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	148	0	0
T38	0	344	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699588861	699519572	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	699662186	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T21
1	0	1	Covered	T20,T4,T17
1	1	0	Covered	T2,T21,T23
1	1	1	Covered	T2,T5,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T21
0	1	Covered	T21,T45,T25
1	0	Covered	T25,T53,T101

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T5,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T53,T101

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T21
1	0	Covered	T105
1	1	Covered	T21,T45,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T20,T4
1	Covered	T5,T21,T15

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T23,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T21
1	Covered	T1,T20,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T6,T31,T33

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T5,T20,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T5,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T15,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T5,T20
Phase1St	198	Covered	T1,T5,T20
Phase2St	215	Covered	T1,T5,T20
Phase3St	233	Covered	T1,T5,T20
TerminalSt	249	Covered	T1,T5,T20
TimeoutSt	159	Covered	T2,T5,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T5,T20
IdleSt->TimeoutSt	159	Covered	T2,T5,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T31,T51,T106
Phase0St->Phase1St	198	Covered	T1,T5,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T107,T108,T100
Phase1St->Phase2St	215	Covered	T1,T5,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T4,T31,T109
Phase2St->Phase3St	233	Covered	T1,T5,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T1,T4,T25
Phase3St->TerminalSt	249	Covered	T1,T5,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T23,T47
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T5,T18
TimeoutSt->Phase0St	172	Covered	T21,T45,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T45,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T51,T106,T110
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T107,T108,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T31,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T4,T25
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T23,T47
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699833099	312	0	0
CheckAccumTrig0_A	699833099	467	0	0
CheckAccumTrig1_A	699833099	21	0	0
CheckClr_A	699833099	199	0	0
CheckEn_A	699590607	349168106	0	0
CheckPhase0_A	699833099	545	0	0
CheckPhase1_A	699833099	541	0	0
CheckPhase2_A	699833099	534	0	0
CheckPhase3_A	699833099	523	0	0
CheckTimeout0_A	699833099	1219	0	0
CheckTimeoutSt1_A	699833099	113541	0	0
CheckTimeoutSt2_A	699833099	1129	0	0
CheckTimeoutStTrig_A	699833099	68	0	0
ErrorStAllEscAsserted_A	699833099	1485	0	0
ErrorStIsTerminal_A	699833099	1245	0	0
EscStateOut_A	699588861	699519572	0	0
u_state_regs_A	699833099	699662186	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	312	0	0
T12	108106	53	0	0
T13	0	50	0	0
T14	0	84	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	61	0	0
T38	0	64	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	467	0	0
T1	415859	2	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	11	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	184304	1	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	2	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	21	0	0
T25	369142	1	0	0
T26	408553	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T68	560491	0	0	0
T69	3727	0	0	0
T70	54573	0	0	0
T79	372440	0	0	0
T83	36635	0	0	0
T89	0	1	0	0
T101	0	1	0	0
T111	0	1	0	0
T112	0	3	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	100373	0	0	0
T117	342749	0	0	0
T118	93413	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	199	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	10	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T31	0	3	0	0
T33	0	1	0	0
T47	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T116	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699590607	349168106	0	0
T1	415859	19180	0	0
T2	32137	8302	0	0
T3	943072	942985	0	0
T4	224468	2666	0	0
T5	13799	2637	0	0
T15	831596	1713	0	0
T16	264801	262447	0	0
T20	184304	1873	0	0
T21	34861	13655	0	0
T22	1791	821	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	545	0	0
T1	415859	2	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	11	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	184304	1	0	0
T21	34861	1	0	0
T22	1791	0	0	0
T23	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	541	0	0
T1	415859	2	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	11	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	184304	1	0	0
T21	34861	1	0	0
T22	1791	0	0	0
T23	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	534	0	0
T1	415859	2	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	10	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	184304	1	0	0
T21	34861	1	0	0
T22	1791	0	0	0
T23	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	523	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	8	0	0
T5	13799	1	0	0
T6	0	1	0	0
T15	831596	1	0	0
T16	264801	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	184304	1	0	0
T21	34861	1	0	0
T22	1791	0	0	0
T23	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1219	0	0
T2	32137	8	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T18	0	1	0	0
T20	184304	0	0	0
T21	34861	1	0	0
T22	1791	0	0	0
T25	0	2	0	0
T31	0	4	0	0
T34	0	11	0	0
T45	0	10	0	0
T78	0	1	0	0
T83	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	113541	0	0
T2	32137	639	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	148	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T18	0	100	0	0
T20	184304	0	0	0
T21	34861	56	0	0
T22	1791	0	0	0
T25	0	753	0	0
T31	0	128	0	0
T34	0	516	0	0
T45	0	2922	0	0
T78	0	7	0	0
T83	0	922	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1129	0	0
T2	32137	8	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T18	0	1	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T26	0	2	0	0
T31	0	4	0	0
T34	0	11	0	0
T45	0	8	0	0
T78	0	1	0	0
T83	0	6	0	0
T84	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	68	0	0
T4	224468	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T18	303676	0	0	0
T21	34861	1	0	0
T22	1791	0	0	0
T23	54666	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T30	279549	0	0	0
T45	0	2	0	0
T46	67043	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T87	0	1	0	0
T101	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1485	0	0
T12	108106	375	0	0
T13	0	187	0	0
T14	0	373	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	186	0	0
T38	0	364	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1245	0	0
T12	108106	315	0	0
T13	0	157	0	0
T14	0	313	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	156	0	0
T38	0	304	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699588861	699519572	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	699662186	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T23
1	0	1	Covered	T16,T22,T17
1	1	0	Covered	T21,T67,T24
1	1	1	Covered	T2,T23,T47

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T23,T81
0	1	Covered	T23,T42,T45
1	0	Covered	T47,T42,T82

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T23,T81
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T42,T82

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T23,T47
1	0	Covered	T65
1	1	Covered	T23,T42,T45

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T47
1	Covered	T22,T17,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T17
1	Covered	T17,T7,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T22,T17
1	Covered	T17,T19,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T22,T17,T23
1	Covered	T1,T47,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T22,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T22,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T1,T22,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T22,T17,T23

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T12,T13,T14
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T22,T17
Phase1St	198	Covered	T1,T22,T17
Phase2St	215	Covered	T1,T22,T17
Phase3St	233	Covered	T1,T22,T17
TerminalSt	249	Covered	T1,T22,T17
TimeoutSt	159	Covered	T2,T23,T47

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T12,T13,T14
IdleSt->Phase0St	152	Covered	T1,T22,T17
IdleSt->TimeoutSt	159	Covered	T2,T23,T47
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T121,T99,T122
Phase0St->Phase1St	198	Covered	T1,T22,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T34,T35,T121
Phase1St->Phase2St	215	Covered	T1,T22,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T121,T107,T123
Phase2St->Phase3St	233	Covered	T1,T22,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T97,T124,T125
Phase3St->TerminalSt	249	Covered	T1,T22,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T47,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T81,T34
TimeoutSt->Phase0St	172	Covered	T23,T47,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T47
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T47,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T81
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T81,T34
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T121,T99,T122
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T22,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T17,T23
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T34,T35,T121
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T22,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T17,T23
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T121,T107,T123
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T22,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T17,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T97,T124,T125
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T22,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T17,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T47,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T22,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	699833099	277	0	0
CheckAccumTrig0_A	699833099	508	0	0
CheckAccumTrig1_A	699833099	22	0	0
CheckClr_A	699833099	253	0	0
CheckEn_A	699590607	327625581	0	0
CheckPhase0_A	699833099	575	0	0
CheckPhase1_A	699833099	563	0	0
CheckPhase2_A	699833099	554	0	0
CheckPhase3_A	699833099	542	0	0
CheckTimeout0_A	699833099	1572	0	0
CheckTimeoutSt1_A	699833099	134656	0	0
CheckTimeoutSt2_A	699833099	1490	0	0
CheckTimeoutStTrig_A	699833099	59	0	0
ErrorStAllEscAsserted_A	699833099	1506	0	0
ErrorStIsTerminal_A	699833099	1266	0	0
EscStateOut_A	699588861	699519572	0	0
u_state_regs_A	699833099	699662186	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	277	0	0
T12	108106	48	0	0
T13	0	34	0	0
T14	0	74	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	43	0	0
T38	0	78	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	508	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	1	0	0
T24	0	1	0	0
T30	0	1	0	0
T47	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	22	0	0
T7	120937	0	0	0
T8	117909	0	0	0
T19	458925	0	0	0
T24	87934	0	0	0
T29	0	1	0	0
T31	197328	0	0	0
T42	0	1	0	0
T47	55594	1	0	0
T48	7874	0	0	0
T57	0	1	0	0
T80	4742	0	0	0
T81	4469	0	0	0
T82	0	1	0	0
T93	80206	0	0	0
T97	0	1	0	0
T100	0	4	0	0
T112	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	253	0	0
T6	587680	0	0	0
T7	0	1	0	0
T17	570085	2	0	0
T18	303676	0	0	0
T19	458925	1	0	0
T23	54666	0	0	0
T30	279549	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T42	0	3	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	67043	0	0	0
T47	55594	5	0	0
T48	7874	0	0	0
T67	64647	0	0	0
T82	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699590607	327625581	0	0
T1	415859	14691	0	0
T2	32137	598	0	0
T3	943072	942985	0	0
T4	224468	224461	0	0
T5	13799	2659	0	0
T15	831596	831506	0	0
T16	264801	3582	0	0
T20	184304	184213	0	0
T21	34861	34766	0	0
T22	1791	825	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	575	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	1	0	0
T23	0	1	0	0
T30	0	1	0	0
T47	0	6	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	563	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	1	0	0
T23	0	1	0	0
T30	0	1	0	0
T47	0	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	554	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	1	0	0
T23	0	1	0	0
T30	0	1	0	0
T47	0	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	542	0	0
T1	415859	1	0	0
T2	32137	0	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	2	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	1	0	0
T23	0	1	0	0
T30	0	1	0	0
T47	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1572	0	0
T2	32137	9	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	1	0	0
T25	0	7	0	0
T34	0	21	0	0
T42	0	3	0	0
T45	0	4	0	0
T47	0	1	0	0
T70	0	4	0	0
T81	0	1	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	134656	0	0
T2	32137	675	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T23	0	3	0	0
T25	0	790	0	0
T34	0	948	0	0
T42	0	78	0	0
T45	0	2261	0	0
T70	0	592	0	0
T81	0	108	0	0
T84	0	125	0	0
T85	0	150	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1490	0	0
T2	32137	9	0	0
T3	943072	0	0	0
T4	224468	0	0	0
T5	13799	0	0	0
T15	831596	0	0	0
T16	264801	0	0	0
T17	570085	0	0	0
T20	184304	0	0	0
T21	34861	0	0	0
T22	1791	0	0	0
T25	0	5	0	0
T34	0	21	0	0
T45	0	1	0	0
T70	0	3	0	0
T81	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T97	0	11	0	0
T98	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	59	0	0
T6	587680	0	0	0
T7	120937	0	0	0
T18	303676	0	0	0
T19	458925	0	0	0
T23	54666	1	0	0
T25	0	2	0	0
T28	0	1	0	0
T30	279549	0	0	0
T42	0	2	0	0
T45	0	3	0	0
T46	67043	0	0	0
T47	55594	0	0	0
T48	7874	0	0	0
T51	0	1	0	0
T67	64647	0	0	0
T70	0	1	0	0
T86	0	1	0	0
T98	0	1	0	0
T124	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1506	0	0
T12	108106	407	0	0
T13	0	182	0	0
T14	0	354	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	173	0	0
T38	0	390	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	1266	0	0
T12	108106	347	0	0
T13	0	152	0	0
T14	0	294	0	0
T33	967712	0	0	0
T34	131026	0	0	0
T37	0	143	0	0
T38	0	330	0	0
T39	3216	0	0	0
T40	188158	0	0	0
T41	69909	0	0	0
T42	74991	0	0	0
T43	421082	0	0	0
T44	110022	0	0	0
T45	249273	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699588861	699519572	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	699833099	699662186	0	0
T1	415859	415851	0	0
T2	32137	32058	0	0
T3	943072	942986	0	0
T4	224468	224461	0	0
T5	13799	13739	0	0
T15	831596	831507	0	0
T16	264801	264795	0	0
T20	184304	184214	0	0
T21	34861	34767	0	0
T22	1791	1733	0	0