Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T45,T187
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12712	0	0
DisabledNoTrigBkwd_A	2147483647	730387	0	0
DisabledNoTrigFwd_A	2147483647	1469471399	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12712	0	0
T5	381811	0	0	0
T12	449414	0	0	0
T13	599888	0	0	0
T16	3599	1079	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	262692	0	0	0
T33	21809	0	0	0
T43	1479	0	0	0
T45	2482	287	0	0
T62	19218	0	0	0
T187	0	162	0	0
T188	0	491	0	0
T189	0	838	0	0
T190	0	774	0	0
T191	0	683	0	0
T192	0	548	0	0
T193	1116	436	0	0
T194	2535	319	0	0
T195	0	772	0	0
T196	0	624	0	0
T197	0	908	0	0
T198	0	639	0	0
T199	0	900	0	0
T200	0	783	0	0
T201	0	644	0	0
T202	0	1039	0	0
T203	0	404	0	0
T204	0	382	0	0
T205	159811	0	0	0
T206	118224	0	0	0
T207	202334	0	0	0
T208	124860	0	0	0
T209	412955	0	0	0
T210	74473	0	0	0
T211	19522	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	730387	0	0
T1	966052	4194	0	0
T2	81028	0	0	0
T3	157728	14	0	0
T4	1724876	1934	0	0
T5	1527244	0	0	0
T11	1985044	3	0	0
T12	1797656	2949	0	0
T13	0	1557	0	0
T14	0	4672	0	0
T15	0	12250	0	0
T16	14396	21	0	0
T17	737308	533	0	0
T18	43996	0	0	0
T21	0	3988	0	0
T22	0	37	0	0
T24	0	1004	0	0
T43	0	2	0	0
T44	0	367	0	0
T45	0	3	0	0
T46	0	3	0	0
T47	0	39	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1469471399	0	0
T1	966052	255762	0	0
T2	81028	48705	0	0
T3	157728	89018	0	0
T4	1724876	1323613	0	0
T5	1527244	692880	0	0
T11	1985044	1983686	0	0
T12	1797656	1116328	0	0
T16	14396	8589	0	0
T17	737308	185224	0	0
T18	43996	28220	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T193,T196,T198
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672685460	2981	0	0
DisabledNoTrigBkwd_A	672685460	197614	0	0
DisabledNoTrigFwd_A	672685460	339757381	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	2981	0	0
T33	21809	0	0	0
T193	1116	436	0	0
T194	2535	0	0	0
T196	0	624	0	0
T198	0	639	0	0
T199	0	900	0	0
T204	0	382	0	0
T205	159811	0	0	0
T206	118224	0	0	0
T207	202334	0	0	0
T208	124860	0	0	0
T209	412955	0	0	0
T210	74473	0	0	0
T211	19522	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	197614	0	0
T1	241513	951	0	0
T2	20257	0	0	0
T3	39432	3	0	0
T4	431219	1474	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	17	0	0
T14	0	4	0	0
T16	3599	0	0	0
T17	184327	227	0	0
T18	10999	0	0	0
T21	0	3965	0	0
T22	0	37	0	0
T44	0	66	0	0
T46	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	339757381	0	0
T1	241513	14808	0	0
T2	20257	20126	0	0
T3	39432	7532	0	0
T4	431219	40533	0	0
T5	381811	360822	0	0
T11	496261	496256	0	0
T12	449414	181212	0	0
T16	3599	2132	0	0
T17	184327	717	0	0
T18	10999	7516	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T11
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T188,T189
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672685460	6360	0	0
DisabledNoTrigBkwd_A	672685460	170463	0	0
DisabledNoTrigFwd_A	672685460	400966260	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	6360	0	0
T5	381811	0	0	0
T12	449414	0	0	0
T13	599888	0	0	0
T16	3599	1079	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	262692	0	0	0
T43	1479	0	0	0
T62	19218	0	0	0
T188	0	491	0	0
T189	0	838	0	0
T190	0	774	0	0
T191	0	683	0	0
T192	0	548	0	0
T197	0	908	0	0
T202	0	1039	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	170463	0	0
T1	241513	1195	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	417	0	0
T5	381811	0	0	0
T11	496261	2	0	0
T12	449414	806	0	0
T13	0	8	0	0
T14	0	2586	0	0
T15	0	9595	0	0
T16	3599	21	0	0
T17	184327	198	0	0
T18	10999	0	0	0
T24	0	1004	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	400966260	0	0
T1	241513	2043	0	0
T2	20257	4217	0	0
T3	39432	39360	0	0
T4	431219	427553	0	0
T5	381811	330466	0	0
T11	496261	495623	0	0
T12	449414	253530	0	0
T16	3599	2143	0	0
T17	184327	721	0	0
T18	10999	6791	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T194
1	1	Covered	T1,T4,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T43

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672685460	606	0	0
DisabledNoTrigBkwd_A	672685460	192392	0	0
DisabledNoTrigFwd_A	672685460	339752750	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	606	0	0
T6	249788	0	0	0
T15	248170	0	0	0
T45	2482	287	0	0
T46	97780	0	0	0
T47	32126	0	0	0
T64	29369	0	0	0
T70	13819	0	0	0
T75	14350	0	0	0
T187	843	0	0	0
T194	0	319	0	0
T212	22598	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	192392	0	0
T1	241513	19	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	32	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	0	1543	0	0
T14	0	2069	0	0
T15	0	2655	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T21	0	16	0	0
T43	0	2	0	0
T44	0	175	0	0
T45	0	3	0	0
T47	0	39	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	339752750	0	0
T1	241513	236849	0	0
T2	20257	4236	0	0
T3	39432	39360	0	0
T4	431219	427783	0	0
T5	381811	794	0	0
T11	496261	496256	0	0
T12	449414	447113	0	0
T16	3599	2149	0	0
T17	184327	183057	0	0
T18	10999	8077	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T11,T12
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T195,T200
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672685460	2765	0	0
DisabledNoTrigBkwd_A	672685460	169918	0	0
DisabledNoTrigFwd_A	672685460	388995008	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	2765	0	0
T7	545490	0	0	0
T15	248170	0	0	0
T24	702708	0	0	0
T30	688288	0	0	0
T65	37889	0	0	0
T66	95409	0	0	0
T67	953032	0	0	0
T70	13819	0	0	0
T75	14350	0	0	0
T187	843	162	0	0
T195	0	772	0	0
T200	0	783	0	0
T201	0	644	0	0
T203	0	404	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	169918	0	0
T1	241513	2029	0	0
T2	20257	0	0	0
T3	39432	11	0	0
T4	431219	11	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	2126	0	0
T13	0	6	0	0
T14	0	13	0	0
T16	3599	0	0	0
T17	184327	108	0	0
T18	10999	0	0	0
T21	0	7	0	0
T44	0	126	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	388995008	0	0
T1	241513	2062	0	0
T2	20257	20126	0	0
T3	39432	2766	0	0
T4	431219	427744	0	0
T5	381811	798	0	0
T11	496261	495551	0	0
T12	449414	234473	0	0
T16	3599	2165	0	0
T17	184327	729	0	0
T18	10999	5836	0	0