Module Definition
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Module Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.30 100.00 100.00 100.00 u_ping_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ping_timer.u_prim_count_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.30 100.00 100.00 100.00 u_ping_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[0].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[0].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[1].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.11 100.00 95.56 100.00 100.00 100.00 gen_classes[1].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[2].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.11 100.00 95.56 100.00 100.00 100.00 gen_classes[2].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[3].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[3].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=5,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_ping_timer.u_prim_count_esc_cnt

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=10,NumCnt=2 + Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_ping_timer.u_prim_count_cnt

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[0].u_accu.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[1].u_accu.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[2].u_accu.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[3].u_accu.u_prim_count

TotalCoveredPercent
Totals 9 9 100.00
Total Bits 108 108 100.00
Total Bits 0->1 54 54 100.00
Total Bits 1->0 54 54 100.00

Ports 9 9 100.00
Port Bits 108 108 100.00
Port Bits 0->1 54 54 100.00
Port Bits 1->0 54 54 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_cnt_i[15:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=7,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[0].u_esc_timer.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[1].u_esc_timer.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[2].u_esc_timer.u_prim_count

SCORETOGGLE
100.00 100.00
tb.dut.gen_classes[3].u_esc_timer.u_prim_count

TotalCoveredPercent
Totals 8 8 100.00
Total Bits 140 140 100.00
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 70 100.00

Ports 8 8 100.00
Port Bits 140 140 100.00
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 70 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 104 104 100.00
Total Bits 0->1 52 52 100.00
Total Bits 1->0 52 52 100.00

Ports 7 7 100.00
Port Bits 104 104 100.00
Port Bits 0->1 52 52 100.00
Port Bits 1->0 52 52 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
set_cnt_i[15:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 74 74 100.00
Total Bits 0->1 37 37 100.00
Total Bits 1->0 37 37 100.00

Ports 7 7 100.00
Port Bits 74 74 100.00
Port Bits 0->1 37 37 100.00
Port Bits 1->0 37 37 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T4,T11 Yes T3,T4,T11 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 140 140 100.00
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 70 100.00

Ports 8 8 100.00
Port Bits 140 140 100.00
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 70 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 74 74 100.00
Total Bits 0->1 37 37 100.00
Total Bits 1->0 37 37 100.00

Ports 7 7 100.00
Port Bits 74 74 100.00
Port Bits 0->1 37 37 100.00
Port Bits 1->0 37 37 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T3,T4,T12 Yes T3,T4,T12 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T11 Yes T1,T4,T11 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T4,T11 Yes T1,T4,T11 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T4,T11 Yes T1,T4,T11 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 140 140 100.00
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 70 100.00

Ports 8 8 100.00
Port Bits 140 140 100.00
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 70 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T4,T11 Yes T1,T4,T11 INPUT
set_i Yes Yes T1,T4,T11 Yes T1,T4,T11 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T11 Yes T1,T4,T11 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T1,T4,T11 Yes T1,T4,T11 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T1,T4,T11 Yes T1,T4,T11 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 74 74 100.00
Total Bits 0->1 37 37 100.00
Total Bits 1->0 37 37 100.00

Ports 7 7 100.00
Port Bits 74 74 100.00
Port Bits 0->1 37 37 100.00
Port Bits 1->0 37 37 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T12 Yes T1,T4,T12 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T4,T12 Yes T1,T4,T12 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T4,T12 Yes T1,T4,T12 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 140 140 100.00
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 70 100.00

Ports 8 8 100.00
Port Bits 140 140 100.00
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 70 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T4,T12 Yes T1,T4,T12 INPUT
set_i Yes Yes T1,T4,T12 Yes T1,T4,T12 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T4,T12 Yes T1,T4,T12 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T1,T4,T12 Yes T1,T4,T12 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T1,T4,T12 Yes T1,T4,T12 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 74 74 100.00
Total Bits 0->1 37 37 100.00
Total Bits 1->0 37 37 100.00

Ports 7 7 100.00
Port Bits 74 74 100.00
Port Bits 0->1 37 37 100.00
Port Bits 1->0 37 37 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 8 100.00
Total Bits 140 140 100.00
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 70 100.00

Ports 8 8 100.00
Port Bits 140 140 100.00
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 70 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T12 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
err_o Yes Yes T8,T9,T10 Yes T8,T9,T10 OUTPUT

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