Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T11,T12
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T4,T11,T12
1	1	1	Covered	T4,T12,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T18
0	1	Covered	T4,T12,T20
1	0	Covered	T4,T21,T22

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T21,T22

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T18
1	0	Covered	T23
1	1	Covered	T4,T12,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T13,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T11,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T4,T12,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T4,T12,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T24,T25,T26
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T27,T28,T29
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T24,T30,T31
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T31,T25,T28
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T4,T12
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T4,T12,T18
TimeoutSt->Phase0St	172	Covered	T4,T12,T20

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T25,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	817	0	0
CheckAccumTrig0_A	2147483647	2405	0	0
CheckAccumTrig1_A	2147483647	117	0	0
CheckClr_A	2147483647	1124	0	0
CheckEn_A	2147483647	1169605398	0	0
CheckPhase0_A	2147483647	2688	0	0
CheckPhase1_A	2147483647	2629	0	0
CheckPhase2_A	2147483647	2563	0	0
CheckPhase3_A	2147483647	2510	0	0
CheckTimeout0_A	2147483647	4044	0	0
CheckTimeoutSt1_A	2147483647	419216	0	0
CheckTimeoutSt2_A	2147483647	3695	0	0
CheckTimeoutStTrig_A	2147483647	225	0	0
ErrorStAllEscAsserted_A	2147483647	4293	0	0
ErrorStIsTerminal_A	2147483647	3573	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	817	0	0
T8	122932	278	0	0
T9	0	145	0	0
T10	0	126	0	0
T32	0	142	0	0
T33	0	126	0	0
T34	933204	0	0	0
T35	143180	0	0	0
T36	1566300	0	0	0
T37	506500	0	0	0
T38	429668	0	0	0
T39	642180	0	0	0
T40	567296	0	0	0
T41	1153084	0	0	0
T42	3002244	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2405	0	0
T1	966052	5	0	0
T2	81028	0	0	0
T3	157728	2	0	0
T4	1724876	13	0	0
T5	1527244	0	0	0
T11	1985044	2	0	0
T12	1797656	11	0	0
T13	0	4	0	0
T14	0	5	0	0
T15	0	2	0	0
T16	14396	1	0	0
T17	737308	3	0	0
T18	43996	0	0	0
T21	0	4	0	0
T22	0	5	0	0
T24	0	4	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117	0	0
T4	431219	1	0	0
T6	249788	0	0	0
T7	545490	0	0	0
T14	370385	0	0	0
T15	248170	2	0	0
T21	262692	1	0	0
T22	21622	1	0	0
T24	702708	0	0	0
T26	0	1	0	0
T27	0	3	0	0
T30	688288	0	0	0
T31	385950	3	0	0
T44	531790	0	0	0
T45	2482	0	0	0
T46	97780	0	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	19218	0	0	0
T63	42210	0	0	0
T64	29369	0	0	0
T65	37889	0	0	0
T66	95409	0	0	0
T67	953032	0	0	0
T68	19474	0	0	0
T69	115797	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1124	0	0
T1	241513	1	0	0
T4	862438	6	0	0
T5	763622	0	0	0
T7	545490	0	0	0
T11	992522	0	0	0
T12	898828	0	0	0
T13	599888	0	0	0
T14	0	2	0	0
T15	248170	2	0	0
T16	7198	0	0	0
T17	368654	0	0	0
T18	21998	0	0	0
T20	5172	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T24	702708	8	0	0
T25	0	7	0	0
T27	0	4	0	0
T28	0	6	0	0
T30	688288	1	0	0
T31	385950	8	0	0
T43	1479	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T65	37889	0	0	0
T66	95409	2	0	0
T67	953032	1	0	0
T68	19474	0	0	0
T70	13819	2	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1169605398	0	0
T1	966052	12028	0	0
T2	81028	48699	0	0
T3	157728	89016	0	0
T4	1724876	523259	0	0
T5	1527244	692878	0	0
T11	1985044	1004940	0	0
T12	1797656	1114194	0	0
T16	14396	8589	0	0
T17	737308	185223	0	0
T18	43996	28218	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2688	0	0
T1	966052	5	0	0
T2	81028	0	0	0
T3	157728	2	0	0
T4	1724876	16	0	0
T5	1527244	0	0	0
T11	1985044	2	0	0
T12	1797656	12	0	0
T13	0	4	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	14396	1	0	0
T17	737308	3	0	0
T18	43996	0	0	0
T21	0	7	0	0
T22	0	6	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T70	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2629	0	0
T1	966052	5	0	0
T2	81028	0	0	0
T3	157728	2	0	0
T4	1724876	16	0	0
T5	1527244	0	0	0
T11	1985044	2	0	0
T12	1797656	12	0	0
T13	0	3	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	14396	1	0	0
T17	737308	3	0	0
T18	43996	0	0	0
T21	0	7	0	0
T22	0	6	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T70	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2563	0	0
T1	966052	5	0	0
T2	81028	0	0	0
T3	157728	2	0	0
T4	1724876	16	0	0
T5	1527244	0	0	0
T11	1985044	2	0	0
T12	1797656	12	0	0
T13	0	3	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	14396	1	0	0
T17	737308	3	0	0
T18	43996	0	0	0
T21	0	7	0	0
T22	0	6	0	0
T43	0	1	0	0
T44	0	5	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T70	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2510	0	0
T1	966052	5	0	0
T2	81028	0	0	0
T3	157728	2	0	0
T4	1724876	16	0	0
T5	1527244	0	0	0
T11	1985044	2	0	0
T12	1797656	12	0	0
T13	0	3	0	0
T14	0	5	0	0
T15	0	4	0	0
T16	14396	1	0	0
T17	737308	3	0	0
T18	43996	0	0	0
T21	0	7	0	0
T22	0	6	0	0
T43	0	1	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T70	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4044	0	0
T4	1293657	11	0	0
T5	1527244	0	0	0
T11	1488783	0	0	0
T12	1797656	175	0	0
T13	2399552	1	0	0
T14	370385	0	0	0
T15	0	7	0	0
T16	10797	0	0	0
T17	737308	0	0	0
T18	43996	4	0	0
T20	20688	2	0	0
T21	262692	35	0	0
T22	0	1	0	0
T24	0	3	0	0
T25	0	1	0	0
T27	0	3	0	0
T31	0	10	0	0
T43	5916	0	0	0
T48	0	47	0	0
T62	19218	0	0	0
T63	0	19	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T70	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	419216	0	0
T4	1293657	3054	0	0
T5	1527244	0	0	0
T11	1488783	0	0	0
T12	1797656	14712	0	0
T13	2399552	11	0	0
T14	370385	0	0	0
T15	0	741	0	0
T16	10797	0	0	0
T17	737308	0	0	0
T18	43996	240	0	0
T20	20688	480	0	0
T21	262692	4229	0	0
T22	0	2	0	0
T24	0	313	0	0
T25	0	43	0	0
T27	0	1498	0	0
T31	0	2138	0	0
T43	5916	0	0	0
T48	0	3532	0	0
T62	19218	0	0	0
T63	0	1068	0	0
T64	0	287	0	0
T65	0	136	0	0
T66	0	655	0	0
T70	0	343	0	0
T75	0	213	0	0
T76	0	109	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3695	0	0
T4	1293657	8	0	0
T5	1527244	0	0	0
T11	1488783	0	0	0
T12	1797656	174	0	0
T13	2399552	1	0	0
T14	370385	0	0	0
T15	0	5	0	0
T16	10797	0	0	0
T17	737308	0	0	0
T18	43996	4	0	0
T20	20688	1	0	0
T21	262692	32	0	0
T24	0	5	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T31	0	5	0	0
T43	5916	0	0	0
T48	0	48	0	0
T62	19218	0	0	0
T63	0	19	0	0
T64	0	1	0	0
T65	0	2	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225	0	0
T4	862438	2	0	0
T5	1145433	0	0	0
T11	992522	0	0	0
T12	1348242	1	0	0
T13	2399552	0	0	0
T14	740770	0	0	0
T16	7198	0	0	0
T17	552981	0	0	0
T18	32997	0	0	0
T20	20688	1	0	0
T21	525384	2	0	0
T22	21622	0	0	0
T24	0	1	0	0
T27	0	7	0	0
T31	0	4	0	0
T43	5916	0	0	0
T44	531790	0	0	0
T45	2482	0	0	0
T49	0	6	0	0
T50	0	6	0	0
T51	0	1	0	0
T52	0	1	0	0
T62	38436	0	0	0
T63	42210	0	0	0
T66	0	1	0	0
T70	0	2	0	0
T74	0	2	0	0
T77	0	1	0	0
T78	0	7	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4293	0	0
T8	122932	1415	0	0
T9	0	701	0	0
T10	0	705	0	0
T32	0	753	0	0
T33	0	719	0	0
T34	933204	0	0	0
T35	143180	0	0	0
T36	1566300	0	0	0
T37	506500	0	0	0
T38	429668	0	0	0
T39	642180	0	0	0
T40	567296	0	0	0
T41	1153084	0	0	0
T42	3002244	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3573	0	0
T8	122932	1175	0	0
T9	0	581	0	0
T10	0	585	0	0
T32	0	633	0	0
T33	0	599	0	0
T34	933204	0	0	0
T35	143180	0	0	0
T36	1566300	0	0	0
T37	506500	0	0	0
T38	429668	0	0	0
T39	642180	0	0	0
T40	567296	0	0	0
T41	1153084	0	0	0
T42	3002244	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	966052	966032	0	0
T2	81028	80504	0	0
T3	157728	157440	0	0
T4	1724876	1724800	0	0
T5	1527244	1526992	0	0
T11	1985044	1985024	0	0
T12	1797656	1797556	0	0
T16	14396	14072	0	0
T17	737308	736964	0	0
T18	43996	43788	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	966052	966032	0	0
T2	81028	80504	0	0
T3	157728	157440	0	0
T4	1724876	1724800	0	0
T5	1527244	1526992	0	0
T11	1985044	1985024	0	0
T12	1797656	1797556	0	0
T16	14396	14072	0	0
T17	737308	736964	0	0
T18	43996	43788	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T18
1	0	1	Covered	T3,T12,T17
1	1	0	Covered	T4,T11,T12
1	1	1	Covered	T4,T12,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T18
0	1	Covered	T12,T21,T70
1	0	Covered	T21,T22,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T12,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T22,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T18
1	0	Not Covered
1	1	Covered	T12,T21,T70

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T3,T4,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T21,T22

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T14,T44

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T12
1	Covered	T1,T4,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T21,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T4,T12,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T4,T12,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T84,T49
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T85,T51
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T86,T49
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T49,T83,T87
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T12,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T12,T18
TimeoutSt->Phase0St	172	Covered	T12,T21,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T21,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T84,T49
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T85,T51
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T86,T49
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T83,T87
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T21,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672685460	218	0	0
CheckAccumTrig0_A	672685460	853	0	0
CheckAccumTrig1_A	672685460	45	0	0
CheckClr_A	672685460	422	0	0
CheckEn_A	672572582	296519208	0	0
CheckPhase0_A	672685460	931	0	0
CheckPhase1_A	672685460	910	0	0
CheckPhase2_A	672685460	888	0	0
CheckPhase3_A	672685460	875	0	0
CheckTimeout0_A	672685460	1097	0	0
CheckTimeoutSt1_A	672685460	95632	0	0
CheckTimeoutSt2_A	672685460	994	0	0
CheckTimeoutStTrig_A	672685460	55	0	0
ErrorStAllEscAsserted_A	672685460	1082	0	0
ErrorStIsTerminal_A	672685460	902	0	0
EscStateOut_A	672571226	672502280	0	0
u_state_regs_A	672685460	672540247	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	218	0	0
T8	30733	81	0	0
T9	0	35	0	0
T10	0	39	0	0
T32	0	28	0	0
T33	0	35	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	853	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	6	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	2	0	0
T14	0	2	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T44	0	2	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	45	0	0
T6	249788	0	0	0
T14	370385	0	0	0
T21	262692	1	0	0
T22	21622	1	0	0
T27	0	2	0	0
T31	0	1	0	0
T44	531790	0	0	0
T45	2482	0	0	0
T46	97780	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T54	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	19218	0	0	0
T63	42210	0	0	0
T64	29369	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	422	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	599888	0	0	0
T14	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	0	2	0	0
T22	0	5	0	0
T24	0	6	0	0
T31	0	1	0	0
T43	1479	0	0	0
T44	0	1	0	0
T66	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672572582	296519208	0	0
T1	241513	2028	0	0
T2	20257	20124	0	0
T3	39432	7532	0	0
T4	431219	40533	0	0
T5	381811	360821	0	0
T11	496261	496256	0	0
T12	449414	179080	0	0
T16	3599	2132	0	0
T17	184327	717	0	0
T18	10999	7515	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	931	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	6	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	3	0	0
T14	0	2	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	4	0	0
T22	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	910	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	6	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	3	0	0
T14	0	2	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	4	0	0
T22	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	888	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	6	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	3	0	0
T14	0	2	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	4	0	0
T22	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	875	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	6	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	3	0	0
T14	0	2	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	4	0	0
T22	0	6	0	0
T44	0	2	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1097	0	0
T4	431219	4	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	54	0	0
T13	599888	1	0	0
T15	0	4	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	1	0	0
T20	5172	0	0	0
T21	0	12	0	0
T22	0	1	0	0
T43	1479	0	0	0
T63	0	3	0	0
T64	0	1	0	0
T70	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	95632	0	0
T4	431219	581	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	4456	0	0
T13	599888	11	0	0
T15	0	620	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	82	0	0
T20	5172	0	0	0
T21	0	1205	0	0
T22	0	2	0	0
T43	1479	0	0	0
T63	0	169	0	0
T64	0	287	0	0
T70	0	94	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	994	0	0
T4	431219	4	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	53	0	0
T13	599888	1	0	0
T15	0	4	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	1	0	0
T20	5172	0	0	0
T21	0	10	0	0
T24	0	3	0	0
T43	1479	0	0	0
T63	0	3	0	0
T64	0	1	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	55	0	0
T5	381811	0	0	0
T12	449414	1	0	0
T13	599888	0	0	0
T14	370385	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	262692	1	0	0
T27	0	2	0	0
T31	0	1	0	0
T43	1479	0	0	0
T49	0	2	0	0
T62	19218	0	0	0
T70	0	1	0	0
T74	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1082	0	0
T8	30733	344	0	0
T9	0	186	0	0
T10	0	172	0	0
T32	0	198	0	0
T33	0	182	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	902	0	0
T8	30733	284	0	0
T9	0	156	0	0
T10	0	142	0	0
T32	0	168	0	0
T33	0	152	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672571226	672502280	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	672540247	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T11,T12
1	0	1	Covered	T1,T4,T12
1	1	0	Covered	T4,T12,T18
1	1	1	Covered	T12,T18,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T18,T20
0	1	Covered	T20,T31,T27
1	0	Covered	T88,T81,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T88,T81,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T18,T20
1	0	Not Covered
1	1	Covered	T20,T31,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T12,T20
1	Covered	T1,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T13,T21

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T44,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T13,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T12,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T12,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T12,T18,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T20,T51,T89
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T13,T78,T19
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T40,T90,T89
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T44,T55,T40
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T12,T13
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T18,T20
TimeoutSt->Phase0St	172	Covered	T20,T31,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T31,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T18,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T89,T19
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T78,T19
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T40,T90,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T44,T55,T40
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T13,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672685460	181	0	0
CheckAccumTrig0_A	672685460	531	0	0
CheckAccumTrig1_A	672685460	27	0	0
CheckClr_A	672685460	261	0	0
CheckEn_A	672572582	299188607	0	0
CheckPhase0_A	672685460	605	0	0
CheckPhase1_A	672685460	585	0	0
CheckPhase2_A	672685460	573	0	0
CheckPhase3_A	672685460	560	0	0
CheckTimeout0_A	672685460	603	0	0
CheckTimeoutSt1_A	672685460	80699	0	0
CheckTimeoutSt2_A	672685460	514	0	0
CheckTimeoutStTrig_A	672685460	62	0	0
ErrorStAllEscAsserted_A	672685460	1085	0	0
ErrorStIsTerminal_A	672685460	905	0	0
EscStateOut_A	672571226	672502280	0	0
u_state_regs_A	672685460	672540247	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	181	0	0
T8	30733	51	0	0
T9	0	38	0	0
T10	0	34	0	0
T32	0	31	0	0
T33	0	27	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	531	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	5	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	27	0	0
T51	0	1	0	0
T55	0	1	0	0
T80	72813	0	0	0
T81	0	1	0	0
T83	0	1	0	0
T87	0	2	0	0
T88	205295	1	0	0
T91	0	2	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	215015	0	0	0
T96	4101	0	0	0
T97	12104	0	0	0
T98	350408	0	0	0
T99	18133	0	0	0
T100	69902	0	0	0
T101	34583	0	0	0
T102	300976	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	261	0	0
T5	381811	0	0	0
T12	449414	1	0	0
T13	599888	2	0	0
T14	370385	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	1	0	0
T21	262692	0	0	0
T24	0	1	0	0
T27	0	3	0	0
T31	0	4	0	0
T43	1479	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T62	19218	0	0	0
T73	0	3	0	0
T103	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672572582	299188607	0	0
T1	241513	2062	0	0
T2	20257	20124	0	0
T3	39432	2766	0	0
T4	431219	37893	0	0
T5	381811	798	0	0
T11	496261	9402	0	0
T12	449414	234473	0	0
T16	3599	2165	0	0
T17	184327	729	0	0
T18	10999	5836	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	605	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	5	0	0
T13	0	2	0	0
T14	0	1	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	585	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	5	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	573	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	5	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	1	0	0
T44	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	560	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	1	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	5	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	3599	0	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T21	0	1	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	603	0	0
T5	381811	0	0	0
T12	449414	66	0	0
T13	599888	0	0	0
T14	370385	0	0	0
T17	184327	0	0	0
T18	10999	2	0	0
T20	5172	2	0	0
T21	262692	3	0	0
T25	0	1	0	0
T27	0	3	0	0
T31	0	2	0	0
T43	1479	0	0	0
T48	0	45	0	0
T62	19218	0	0	0
T63	0	9	0	0
T76	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	80699	0	0
T5	381811	0	0	0
T12	449414	5355	0	0
T13	599888	0	0	0
T14	370385	0	0	0
T17	184327	0	0	0
T18	10999	103	0	0
T20	5172	480	0	0
T21	262692	431	0	0
T25	0	43	0	0
T27	0	1498	0	0
T31	0	1048	0	0
T43	1479	0	0	0
T48	0	3521	0	0
T62	19218	0	0	0
T63	0	499	0	0
T76	0	109	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	514	0	0
T5	381811	0	0	0
T12	449414	66	0	0
T13	599888	0	0	0
T14	370385	0	0	0
T17	184327	0	0	0
T18	10999	2	0	0
T20	5172	1	0	0
T21	262692	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0
T43	1479	0	0	0
T48	0	45	0	0
T62	19218	0	0	0
T63	0	9	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	62	0	0
T13	599888	0	0	0
T14	370385	0	0	0
T20	5172	1	0	0
T21	262692	0	0	0
T22	21622	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T43	1479	0	0	0
T44	531790	0	0	0
T45	2482	0	0	0
T49	0	1	0	0
T50	0	4	0	0
T53	0	1	0	0
T62	19218	0	0	0
T63	42210	0	0	0
T78	0	4	0	0
T80	0	1	0	0
T88	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1085	0	0
T8	30733	357	0	0
T9	0	160	0	0
T10	0	179	0	0
T32	0	191	0	0
T33	0	198	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	905	0	0
T8	30733	297	0	0
T9	0	130	0	0
T10	0	149	0	0
T32	0	161	0	0
T33	0	168	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672571226	672502280	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	672540247	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T19
1	1	1	Covered	T1,T2,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T11,T12
1	0	1	Covered	T1,T16,T12
1	1	0	Covered	T4,T12,T18
1	1	1	Covered	T4,T12,T21

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T21
0	1	Covered	T4,T70,T27
1	0	Covered	T15,T31,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T12,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T31,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T21
1	0	Not Covered
1	1	Covered	T4,T70,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T11,T12
1	Covered	T1,T4,T16

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T14,T70,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T4,T11,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T12,T24,T31

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T11,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T11,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T16,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T16

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T11
Phase1St	198	Covered	T1,T4,T11
Phase2St	215	Covered	T1,T4,T11
Phase3St	233	Covered	T1,T4,T11
TerminalSt	249	Covered	T1,T4,T11
TimeoutSt	159	Covered	T4,T12,T21

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T4,T11
IdleSt->TimeoutSt	159	Covered	T4,T12,T21
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T25,T26,T49
Phase0St->Phase1St	198	Covered	T1,T4,T11
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T105,T89,T106
Phase1St->Phase2St	215	Covered	T1,T4,T11
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T30,T72,T55
Phase2St->Phase3St	233	Covered	T1,T4,T11
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T31,T25,T57
Phase3St->TerminalSt	249	Covered	T1,T4,T11
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T12,T70
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T12,T21
TimeoutSt->Phase0St	172	Covered	T4,T70,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T21
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T70,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T21
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T25,T26,T49
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T105,T89,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T30,T72,T55
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T31,T25,T57
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T70,T15,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672685460	212	0	0
CheckAccumTrig0_A	672685460	471	0	0
CheckAccumTrig1_A	672685460	26	0	0
CheckClr_A	672685460	203	0	0
CheckEn_A	672572582	302259417	0	0
CheckPhase0_A	672685460	542	0	0
CheckPhase1_A	672685460	534	0	0
CheckPhase2_A	672685460	518	0	0
CheckPhase3_A	672685460	504	0	0
CheckTimeout0_A	672685460	1246	0	0
CheckTimeoutSt1_A	672685460	122763	0	0
CheckTimeoutSt2_A	672685460	1162	0	0
CheckTimeoutStTrig_A	672685460	56	0	0
ErrorStAllEscAsserted_A	672685460	1038	0	0
ErrorStIsTerminal_A	672685460	858	0	0
EscStateOut_A	672571226	672502280	0	0
u_state_regs_A	672685460	672540247	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	212	0	0
T8	30733	74	0	0
T9	0	32	0	0
T10	0	31	0	0
T32	0	42	0	0
T33	0	33	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	471	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	2	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	4	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	3599	1	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T24	0	4	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	26	0	0
T7	545490	0	0	0
T15	248170	1	0	0
T24	702708	0	0	0
T26	0	1	0	0
T30	688288	0	0	0
T31	385950	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T59	0	1	0	0
T65	37889	0	0	0
T66	95409	0	0	0
T67	953032	0	0	0
T68	19474	0	0	0
T69	115797	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	203	0	0
T7	545490	0	0	0
T15	248170	1	0	0
T24	702708	2	0	0
T25	0	4	0	0
T30	688288	1	0	0
T31	385950	3	0	0
T48	0	1	0	0
T65	37889	0	0	0
T66	95409	0	0	0
T67	953032	1	0	0
T68	19474	0	0	0
T70	13819	1	0	0
T72	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672572582	302259417	0	0
T1	241513	2043	0	0
T2	20257	4216	0	0
T3	39432	39359	0	0
T4	431219	17050	0	0
T5	381811	330465	0	0
T11	496261	3026	0	0
T12	449414	253529	0	0
T16	3599	2143	0	0
T17	184327	721	0	0
T18	10999	6790	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	542	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	4	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	1	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T70	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	534	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	4	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	1	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T70	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	518	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	4	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	1	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T70	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	504	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	1	0	0
T12	449414	4	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	1	0	0
T17	184327	1	0	0
T18	10999	0	0	0
T70	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1246	0	0
T4	431219	2	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	54	0	0
T13	599888	0	0	0
T15	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	0	14	0	0
T24	0	1	0	0
T31	0	5	0	0
T43	1479	0	0	0
T48	0	2	0	0
T63	0	5	0	0
T70	0	1	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	122763	0	0
T4	431219	729	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	4839	0	0
T13	599888	0	0	0
T15	0	119	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	0	1697	0	0
T24	0	42	0	0
T31	0	683	0	0
T43	1479	0	0	0
T48	0	11	0	0
T63	0	287	0	0
T70	0	249	0	0
T75	0	213	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1162	0	0
T4	431219	1	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	54	0	0
T13	599888	0	0	0
T15	0	1	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	0	14	0	0
T24	0	1	0	0
T31	0	3	0	0
T43	1479	0	0	0
T48	0	1	0	0
T63	0	5	0	0
T73	0	1	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	56	0	0
T4	431219	1	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	599888	0	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T27	0	1	0	0
T43	1479	0	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1038	0	0
T8	30733	352	0	0
T9	0	158	0	0
T10	0	182	0	0
T32	0	164	0	0
T33	0	182	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	858	0	0
T8	30733	292	0	0
T9	0	128	0	0
T10	0	152	0	0
T32	0	134	0	0
T33	0	152	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672571226	672502280	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	672540247	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T43

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T12,T18
1	0	1	Covered	T12,T17,T13
1	1	0	Covered	T4,T11,T12
1	1	1	Covered	T4,T12,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T12,T18
0	1	Covered	T4,T21,T24
1	0	Covered	T4,T15,T27

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T12,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T15,T27

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T18
1	0	Covered	T23
1	1	Covered	T4,T21,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T43,T13
1	Covered	T1,T45,T66

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T43
1	Covered	T4,T21,T47

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T21
1	Covered	T4,T43,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T43
1	Covered	T4,T21,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T43

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T43
Phase1St	198	Covered	T1,T4,T43
Phase2St	215	Covered	T1,T4,T43
Phase3St	233	Covered	T1,T4,T43
TerminalSt	249	Covered	T1,T4,T43
TimeoutSt	159	Covered	T4,T12,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T4,T43
IdleSt->TimeoutSt	159	Covered	T4,T12,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T84,T89,T107
Phase0St->Phase1St	198	Covered	T1,T4,T43
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T28,T108
Phase1St->Phase2St	215	Covered	T1,T4,T43
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T25,T28
Phase2St->Phase3St	233	Covered	T1,T4,T43
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T109,T110
Phase3St->TerminalSt	249	Covered	T1,T4,T43
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T12,T18
TimeoutSt->Phase0St	172	Covered	T4,T21,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T43
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T84,T89,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T43
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T43
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T28,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T43
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T43
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T25,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T43
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T43
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T109,T110
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T43
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T43
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672685460	206	0	0
CheckAccumTrig0_A	672685460	550	0	0
CheckAccumTrig1_A	672685460	19	0	0
CheckClr_A	672685460	238	0	0
CheckEn_A	672572582	271638166	0	0
CheckPhase0_A	672685460	610	0	0
CheckPhase1_A	672685460	600	0	0
CheckPhase2_A	672685460	584	0	0
CheckPhase3_A	672685460	571	0	0
CheckTimeout0_A	672685460	1098	0	0
CheckTimeoutSt1_A	672685460	120122	0	0
CheckTimeoutSt2_A	672685460	1025	0	0
CheckTimeoutStTrig_A	672685460	52	0	0
ErrorStAllEscAsserted_A	672685460	1088	0	0
ErrorStIsTerminal_A	672685460	908	0	0
EscStateOut_A	672571226	672502280	0	0
u_state_regs_A	672685460	672540247	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	206	0	0
T8	30733	72	0	0
T9	0	40	0	0
T10	0	22	0	0
T32	0	41	0	0
T33	0	31	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	550	0	0
T1	241513	2	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	2	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T21	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	19	0	0
T4	431219	1	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	599888	0	0	0
T15	0	1	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T27	0	1	0	0
T43	1479	0	0	0
T52	0	1	0	0
T58	0	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T111	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	238	0	0
T1	241513	1	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T15	0	1	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T25	0	3	0	0
T27	0	4	0	0
T28	0	6	0	0
T31	0	4	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672572582	271638166	0	0
T1	241513	5895	0	0
T2	20257	4235	0	0
T3	39432	39359	0	0
T4	431219	427783	0	0
T5	381811	794	0	0
T11	496261	496256	0	0
T12	449414	447112	0	0
T16	3599	2149	0	0
T17	184327	183056	0	0
T18	10999	8077	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	610	0	0
T1	241513	2	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	4	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T21	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	600	0	0
T1	241513	2	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	4	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T21	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	584	0	0
T1	241513	2	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	4	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T21	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	571	0	0
T1	241513	2	0	0
T2	20257	0	0	0
T3	39432	0	0	0
T4	431219	4	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T21	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1098	0	0
T4	431219	5	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	1	0	0
T13	599888	0	0	0
T15	0	1	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	1	0	0
T20	5172	0	0	0
T21	0	6	0	0
T24	0	2	0	0
T31	0	3	0	0
T43	1479	0	0	0
T63	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	120122	0	0
T4	431219	1744	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	62	0	0
T13	599888	0	0	0
T15	0	2	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	55	0	0
T20	5172	0	0	0
T21	0	896	0	0
T24	0	271	0	0
T31	0	407	0	0
T43	1479	0	0	0
T63	0	113	0	0
T65	0	136	0	0
T66	0	655	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1025	0	0
T4	431219	3	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	1	0	0
T13	599888	0	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	1	0	0
T20	5172	0	0	0
T21	0	5	0	0
T24	0	1	0	0
T31	0	2	0	0
T43	1479	0	0	0
T48	0	2	0	0
T63	0	2	0	0
T65	0	1	0	0
T73	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	52	0	0
T4	431219	1	0	0
T5	381811	0	0	0
T11	496261	0	0	0
T12	449414	0	0	0
T13	599888	0	0	0
T16	3599	0	0	0
T17	184327	0	0	0
T18	10999	0	0	0
T20	5172	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T27	0	2	0	0
T31	0	1	0	0
T43	1479	0	0	0
T50	0	2	0	0
T66	0	1	0	0
T74	0	1	0	0
T78	0	2	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	1088	0	0
T8	30733	362	0	0
T9	0	197	0	0
T10	0	172	0	0
T32	0	200	0	0
T33	0	157	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	908	0	0
T8	30733	302	0	0
T9	0	167	0	0
T10	0	142	0	0
T32	0	170	0	0
T33	0	127	0	0
T34	233301	0	0	0
T35	35795	0	0	0
T36	391575	0	0	0
T37	126625	0	0	0
T38	107417	0	0	0
T39	160545	0	0	0
T40	141824	0	0	0
T41	288271	0	0	0
T42	750561	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672571226	672502280	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672685460	672540247	0	0
T1	241513	241508	0	0
T2	20257	20126	0	0
T3	39432	39360	0	0
T4	431219	431200	0	0
T5	381811	381748	0	0
T11	496261	496256	0	0
T12	449414	449389	0	0
T16	3599	3518	0	0
T17	184327	184241	0	0
T18	10999	10947	0	0