Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66278297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32186424

1

T1

95583

T2

143952

T3

142217

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14945848	1			T1	37995		T2	56085		T3	56141
values[0x0]	40694437	1			T1	132068		T2	198269		T3	197392
values[0x1]	42824436	1			T1	132442		T2	197949		T3	197918

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56544048	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41920673

1

T1

120932

T2

182067

T3

180079

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	331914	1			T1	1222		T3	1654		T15	34
valid_sources[0x01]	677408	1			T1	1240		T3	1669		T15	23
valid_sources[0x02]	321804	1			T1	1212		T3	2240		T15	16
valid_sources[0x03]	320964	1			T1	1160		T3	1651		T15	15
valid_sources[0x04]	320416	1			T1	1107		T3	1514		T15	23
valid_sources[0x05]	515947	1			T1	1060		T3	1886		T15	17
valid_sources[0x06]	320876	1			T1	1050		T3	1475		T15	7
valid_sources[0x07]	393499	1			T1	1095		T3	1702		T15	16
valid_sources[0x08]	325471	1			T1	1220		T3	1581		T15	28
valid_sources[0x09]	363217	1			T1	1116		T3	1560		T15	27
valid_sources[0x0a]	546633	1			T1	1146		T3	1895		T15	14
valid_sources[0x0b]	321900	1			T1	1141		T3	1899		T15	25
valid_sources[0x0c]	314953	1			T1	1205		T3	1700		T15	19
valid_sources[0x0d]	327807	1			T1	1075		T3	1569		T15	13
valid_sources[0x0e]	336425	1			T1	1249		T3	1609		T15	44
valid_sources[0x0f]	329750	1			T1	1145		T3	1714		T15	17
valid_sources[0x10]	722712	1			T1	1187		T3	1715		T15	17
valid_sources[0x11]	331998	1			T1	1217		T3	1709		T15	17
valid_sources[0x12]	325897	1			T1	1174		T3	1865		T15	16
valid_sources[0x13]	334824	1			T1	1165		T3	1798		T15	14
valid_sources[0x14]	332456	1			T1	1223		T3	1509		T15	12
valid_sources[0x15]	323822	1			T1	1193		T3	1994		T15	16
valid_sources[0x16]	322060	1			T1	1178		T3	1750		T15	39
valid_sources[0x17]	798513	1			T1	1126		T3	1702		T15	13
valid_sources[0x18]	320225	1			T1	1125		T3	1524		T15	12
valid_sources[0x19]	350616	1			T1	1175		T3	1958		T15	15
valid_sources[0x1a]	323987	1			T1	1157		T3	1879		T15	19
valid_sources[0x1b]	325534	1			T1	1146		T3	2046		T15	15
valid_sources[0x1c]	323420	1			T1	1237		T3	1762		T15	17
valid_sources[0x1d]	323829	1			T1	1171		T3	1659		T15	30
valid_sources[0x1e]	321735	1			T1	1163		T3	1832		T15	12
valid_sources[0x1f]	405802	1			T1	1146		T3	1522		T15	21
valid_sources[0x20]	318916	1			T1	1205		T3	1882		T15	9
valid_sources[0x21]	336629	1			T1	1122		T3	2006		T15	5
valid_sources[0x22]	326517	1			T1	1117		T3	1942		T15	15
valid_sources[0x23]	319646	1			T1	1178		T3	1893		T15	28
valid_sources[0x24]	323430	1			T1	1175		T3	1829		T15	21
valid_sources[0x25]	317939	1			T1	1115		T3	1892		T15	12
valid_sources[0x26]	318725	1			T1	1164		T3	1566		T15	24
valid_sources[0x27]	320329	1			T1	1168		T3	1718		T15	29
valid_sources[0x28]	336755	1			T1	1274		T3	1573		T15	26
valid_sources[0x29]	603633	1			T1	1179		T3	1610		T15	20
valid_sources[0x2a]	321902	1			T1	1220		T3	2007		T15	12
valid_sources[0x2b]	323108	1			T1	1203		T3	1727		T15	22
valid_sources[0x2c]	873313	1			T1	1094		T3	1844		T15	13
valid_sources[0x2d]	326787	1			T1	1127		T3	1653		T15	7
valid_sources[0x2e]	316742	1			T1	1128		T3	1784		T15	24
valid_sources[0x2f]	322871	1			T1	1270		T3	1749		T15	27
valid_sources[0x30]	342754	1			T1	1155		T3	1678		T15	12
valid_sources[0x31]	321851	1			T1	1253		T3	1850		T15	21
valid_sources[0x32]	326782	1			T1	1205		T3	1829		T15	13
valid_sources[0x33]	324840	1			T1	1260		T3	1850		T15	22
valid_sources[0x34]	667274	1			T1	1174		T3	1651		T15	15
valid_sources[0x35]	322182	1			T1	1197		T3	1679		T15	7
valid_sources[0x36]	317581	1			T1	1154		T3	1979		T15	18
valid_sources[0x37]	322585	1			T1	1223		T3	1495		T15	14
valid_sources[0x38]	593168	1			T1	1228		T3	1604		T15	23
valid_sources[0x39]	318163	1			T1	1211		T3	1871		T15	7
valid_sources[0x3a]	318444	1			T1	1229		T3	1596		T15	12
valid_sources[0x3b]	318411	1			T1	1248		T3	1734		T15	16
valid_sources[0x3c]	332051	1			T1	1178		T3	1599		T15	23
valid_sources[0x3d]	319687	1			T1	1102		T3	1645		T15	18
valid_sources[0x3e]	318443	1			T1	1177		T3	1571		T15	12
valid_sources[0x3f]	320334	1			T1	1131		T3	1847		T15	22
valid_sources[0x40]	316249	1			T1	1228		T3	1746		T15	23
valid_sources[0x41]	326010	1			T1	1253		T3	1894		T15	29
valid_sources[0x42]	319502	1			T1	1205		T3	2133		T15	17
valid_sources[0x43]	324301	1			T1	1156		T3	1850		T15	17
valid_sources[0x44]	318589	1			T1	1112		T3	1466		T15	7
valid_sources[0x45]	317708	1			T1	1223		T3	1752		T15	23
valid_sources[0x46]	325677	1			T1	1170		T3	1751		T15	8
valid_sources[0x47]	739835	1			T1	1139		T3	1644		T15	21
valid_sources[0x48]	320501	1			T1	1180		T3	1974		T15	13
valid_sources[0x49]	317203	1			T1	1148		T3	1594		T15	18
valid_sources[0x4a]	320186	1			T1	1283		T3	1796		T15	13
valid_sources[0x4b]	328993	1			T1	1234		T3	1890		T15	24
valid_sources[0x4c]	326676	1			T1	1312		T3	1734		T15	33
valid_sources[0x4d]	319592	1			T1	1201		T3	1719		T15	32
valid_sources[0x4e]	323420	1			T1	1177		T3	2027		T15	23
valid_sources[0x4f]	326485	1			T1	1188		T3	1543		T15	21
valid_sources[0x50]	787901	1			T1	1282		T3	1594		T15	32
valid_sources[0x51]	573316	1			T1	1168		T3	1948		T15	17
valid_sources[0x52]	328154	1			T1	1303		T3	1940		T4	13939
valid_sources[0x53]	321590	1			T1	1219		T3	1613		T15	15
valid_sources[0x54]	320279	1			T1	1194		T3	1764		T15	26
valid_sources[0x55]	803303	1			T1	1065		T3	1411		T15	11
valid_sources[0x56]	315493	1			T1	1179		T3	1834		T15	19
valid_sources[0x57]	325363	1			T1	1217		T3	1600		T15	33
valid_sources[0x58]	322971	1			T1	1198		T3	2125		T15	14
valid_sources[0x59]	332296	1			T1	1107		T3	2030		T15	6
valid_sources[0x5a]	318243	1			T1	1126		T3	1925		T15	24
valid_sources[0x5b]	323972	1			T1	1205		T3	1917		T15	12
valid_sources[0x5c]	320465	1			T1	1141		T3	2013		T15	37
valid_sources[0x5d]	321461	1			T1	1101		T3	1630		T15	16
valid_sources[0x5e]	313278	1			T1	1248		T3	1652		T15	20
valid_sources[0x5f]	323181	1			T1	1174		T3	2044		T15	9
valid_sources[0x60]	696487	1			T1	1169		T3	1538		T15	18
valid_sources[0x61]	320072	1			T1	1160		T3	1551		T15	23
valid_sources[0x62]	333092	1			T1	1186		T3	1828		T15	28
valid_sources[0x63]	323161	1			T1	1183		T3	1814		T15	16
valid_sources[0x64]	324177	1			T1	1189		T3	1614		T15	12
valid_sources[0x65]	330939	1			T1	1195		T3	1562		T15	10
valid_sources[0x66]	361723	1			T1	1105		T3	2133		T15	9
valid_sources[0x67]	316822	1			T1	1124		T3	1475		T15	10
valid_sources[0x68]	780356	1			T1	1148		T3	1726		T15	13
valid_sources[0x69]	324958	1			T1	1154		T3	1848		T15	8
valid_sources[0x6a]	650800	1			T1	1231		T3	1993		T15	23
valid_sources[0x6b]	317918	1			T1	1246		T3	1764		T15	21
valid_sources[0x6c]	322212	1			T1	1180		T3	1744		T15	25
valid_sources[0x6d]	1047147	1			T1	1260		T3	1736		T15	14
valid_sources[0x6e]	712404	1			T1	1159		T3	2115		T15	18
valid_sources[0x6f]	799521	1			T1	1266		T3	1862		T15	20
valid_sources[0x70]	319442	1			T1	1172		T3	1646		T15	12
valid_sources[0x71]	314948	1			T1	1079		T3	1687		T15	15
valid_sources[0x72]	331905	1			T1	1273		T3	1598		T15	12
valid_sources[0x73]	319786	1			T1	1171		T3	1886		T15	17
valid_sources[0x74]	322557	1			T1	1173		T3	1708		T15	17
valid_sources[0x75]	322260	1			T1	1174		T3	1656		T15	10
valid_sources[0x76]	314413	1			T1	1161		T3	1708		T15	19
valid_sources[0x77]	717443	1			T1	1205		T3	2019		T15	9
valid_sources[0x78]	800984	1			T1	1255		T3	2066		T15	12
valid_sources[0x79]	323031	1			T1	1165		T3	1785		T15	18
valid_sources[0x7a]	318256	1			T1	1205		T3	1779		T15	26
valid_sources[0x7b]	320861	1			T1	1223		T3	1729		T15	13
valid_sources[0x7c]	321578	1			T1	1195		T3	1892		T15	21
valid_sources[0x7d]	314144	1			T1	1269		T3	1825		T15	33
valid_sources[0x7e]	338768	1			T1	1198		T3	1712		T15	12
valid_sources[0x7f]	331826	1			T1	1066		T3	2079		T15	32
valid_sources[0x80]	324755	1			T1	1182		T3	1794		T15	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7440955

1

T1

18933

T2

28201

T3

28123

values[0x0]

all_enables

biggest_size

15608389

1

T1

48952

T2

74101

T3

73216

values[0x1]

all_enables

biggest_size

9137080

1

T1

27698

T2

41650

T3

40878